efm32gg900_pac/uart0/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXENS` reader - Receiver Enable Status"]
17pub type RXENS_R = crate::BitReader<bool>;
18#[doc = "Field `TXENS` reader - Transmitter Enable Status"]
19pub type TXENS_R = crate::BitReader<bool>;
20#[doc = "Field `MASTER` reader - SPI Master Mode"]
21pub type MASTER_R = crate::BitReader<bool>;
22#[doc = "Field `RXBLOCK` reader - Block Incoming Data"]
23pub type RXBLOCK_R = crate::BitReader<bool>;
24#[doc = "Field `TXTRI` reader - Transmitter Tristated"]
25pub type TXTRI_R = crate::BitReader<bool>;
26#[doc = "Field `TXC` reader - TX Complete"]
27pub type TXC_R = crate::BitReader<bool>;
28#[doc = "Field `TXBL` reader - TX Buffer Level"]
29pub type TXBL_R = crate::BitReader<bool>;
30#[doc = "Field `RXDATAV` reader - RX Data Valid"]
31pub type RXDATAV_R = crate::BitReader<bool>;
32#[doc = "Field `RXFULL` reader - RX FIFO Full"]
33pub type RXFULL_R = crate::BitReader<bool>;
34#[doc = "Field `TXBDRIGHT` reader - TX Buffer Expects Double Right Data"]
35pub type TXBDRIGHT_R = crate::BitReader<bool>;
36#[doc = "Field `TXBSRIGHT` reader - TX Buffer Expects Single Right Data"]
37pub type TXBSRIGHT_R = crate::BitReader<bool>;
38#[doc = "Field `RXDATAVRIGHT` reader - RX Data Right"]
39pub type RXDATAVRIGHT_R = crate::BitReader<bool>;
40#[doc = "Field `RXFULLRIGHT` reader - RX Full of Right Data"]
41pub type RXFULLRIGHT_R = crate::BitReader<bool>;
42impl R {
43    #[doc = "Bit 0 - Receiver Enable Status"]
44    #[inline(always)]
45    pub fn rxens(&self) -> RXENS_R {
46        RXENS_R::new((self.bits & 1) != 0)
47    }
48    #[doc = "Bit 1 - Transmitter Enable Status"]
49    #[inline(always)]
50    pub fn txens(&self) -> TXENS_R {
51        TXENS_R::new(((self.bits >> 1) & 1) != 0)
52    }
53    #[doc = "Bit 2 - SPI Master Mode"]
54    #[inline(always)]
55    pub fn master(&self) -> MASTER_R {
56        MASTER_R::new(((self.bits >> 2) & 1) != 0)
57    }
58    #[doc = "Bit 3 - Block Incoming Data"]
59    #[inline(always)]
60    pub fn rxblock(&self) -> RXBLOCK_R {
61        RXBLOCK_R::new(((self.bits >> 3) & 1) != 0)
62    }
63    #[doc = "Bit 4 - Transmitter Tristated"]
64    #[inline(always)]
65    pub fn txtri(&self) -> TXTRI_R {
66        TXTRI_R::new(((self.bits >> 4) & 1) != 0)
67    }
68    #[doc = "Bit 5 - TX Complete"]
69    #[inline(always)]
70    pub fn txc(&self) -> TXC_R {
71        TXC_R::new(((self.bits >> 5) & 1) != 0)
72    }
73    #[doc = "Bit 6 - TX Buffer Level"]
74    #[inline(always)]
75    pub fn txbl(&self) -> TXBL_R {
76        TXBL_R::new(((self.bits >> 6) & 1) != 0)
77    }
78    #[doc = "Bit 7 - RX Data Valid"]
79    #[inline(always)]
80    pub fn rxdatav(&self) -> RXDATAV_R {
81        RXDATAV_R::new(((self.bits >> 7) & 1) != 0)
82    }
83    #[doc = "Bit 8 - RX FIFO Full"]
84    #[inline(always)]
85    pub fn rxfull(&self) -> RXFULL_R {
86        RXFULL_R::new(((self.bits >> 8) & 1) != 0)
87    }
88    #[doc = "Bit 9 - TX Buffer Expects Double Right Data"]
89    #[inline(always)]
90    pub fn txbdright(&self) -> TXBDRIGHT_R {
91        TXBDRIGHT_R::new(((self.bits >> 9) & 1) != 0)
92    }
93    #[doc = "Bit 10 - TX Buffer Expects Single Right Data"]
94    #[inline(always)]
95    pub fn txbsright(&self) -> TXBSRIGHT_R {
96        TXBSRIGHT_R::new(((self.bits >> 10) & 1) != 0)
97    }
98    #[doc = "Bit 11 - RX Data Right"]
99    #[inline(always)]
100    pub fn rxdatavright(&self) -> RXDATAVRIGHT_R {
101        RXDATAVRIGHT_R::new(((self.bits >> 11) & 1) != 0)
102    }
103    #[doc = "Bit 12 - RX Full of Right Data"]
104    #[inline(always)]
105    pub fn rxfullright(&self) -> RXFULLRIGHT_R {
106        RXFULLRIGHT_R::new(((self.bits >> 12) & 1) != 0)
107    }
108}
109#[doc = "USART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
110pub struct STATUS_SPEC;
111impl crate::RegisterSpec for STATUS_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [status::R](R) reader structure"]
115impl crate::Readable for STATUS_SPEC {
116    type Reader = R;
117}
118#[doc = "`reset()` method sets STATUS to value 0x40"]
119impl crate::Resettable for STATUS_SPEC {
120    #[inline(always)]
121    fn reset_value() -> Self::Ux {
122        0x40
123    }
124}
efm32gg900_pac/uart0/status.rs

efm32gg900_pac/uart0/
status.rs
