efm32gg330_pac/usb/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VBUSENAP` reader - VBUSEN Active Polarity"]
38pub type VBUSENAP_R = crate::BitReader<bool>;
39#[doc = "Field `VBUSENAP` writer - VBUSEN Active Polarity"]
40pub type VBUSENAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `DMPUAP` reader - DMPU Active Polarity"]
42pub type DMPUAP_R = crate::BitReader<bool>;
43#[doc = "Field `DMPUAP` writer - DMPU Active Polarity"]
44pub type DMPUAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `VREGDIS` reader - Voltage Regulator Disable"]
46pub type VREGDIS_R = crate::BitReader<bool>;
47#[doc = "Field `VREGDIS` writer - Voltage Regulator Disable"]
48pub type VREGDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
49#[doc = "Field `VREGOSEN` reader - VREGO Sense Enable"]
50pub type VREGOSEN_R = crate::BitReader<bool>;
51#[doc = "Field `VREGOSEN` writer - VREGO Sense Enable"]
52pub type VREGOSEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
53#[doc = "Field `BIASPROGEM01` reader - Regulator Bias Programming Value in EM0/1"]
54pub type BIASPROGEM01_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `BIASPROGEM01` writer - Regulator Bias Programming Value in EM0/1"]
56pub type BIASPROGEM01_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 2, 20>;
57#[doc = "Field `BIASPROGEM23` reader - Regulator Bias Programming Value in EM2/3"]
58pub type BIASPROGEM23_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `BIASPROGEM23` writer - Regulator Bias Programming Value in EM2/3"]
60pub type BIASPROGEM23_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 2, 24>;
61impl R {
62    #[doc = "Bit 0 - VBUSEN Active Polarity"]
63    #[inline(always)]
64    pub fn vbusenap(&self) -> VBUSENAP_R {
65        VBUSENAP_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - DMPU Active Polarity"]
68    #[inline(always)]
69    pub fn dmpuap(&self) -> DMPUAP_R {
70        DMPUAP_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 16 - Voltage Regulator Disable"]
73    #[inline(always)]
74    pub fn vregdis(&self) -> VREGDIS_R {
75        VREGDIS_R::new(((self.bits >> 16) & 1) != 0)
76    }
77    #[doc = "Bit 17 - VREGO Sense Enable"]
78    #[inline(always)]
79    pub fn vregosen(&self) -> VREGOSEN_R {
80        VREGOSEN_R::new(((self.bits >> 17) & 1) != 0)
81    }
82    #[doc = "Bits 20:21 - Regulator Bias Programming Value in EM0/1"]
83    #[inline(always)]
84    pub fn biasprogem01(&self) -> BIASPROGEM01_R {
85        BIASPROGEM01_R::new(((self.bits >> 20) & 3) as u8)
86    }
87    #[doc = "Bits 24:25 - Regulator Bias Programming Value in EM2/3"]
88    #[inline(always)]
89    pub fn biasprogem23(&self) -> BIASPROGEM23_R {
90        BIASPROGEM23_R::new(((self.bits >> 24) & 3) as u8)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - VBUSEN Active Polarity"]
95    #[inline(always)]
96    pub fn vbusenap(&mut self) -> VBUSENAP_W {
97        VBUSENAP_W::new(self)
98    }
99    #[doc = "Bit 1 - DMPU Active Polarity"]
100    #[inline(always)]
101    pub fn dmpuap(&mut self) -> DMPUAP_W {
102        DMPUAP_W::new(self)
103    }
104    #[doc = "Bit 16 - Voltage Regulator Disable"]
105    #[inline(always)]
106    pub fn vregdis(&mut self) -> VREGDIS_W {
107        VREGDIS_W::new(self)
108    }
109    #[doc = "Bit 17 - VREGO Sense Enable"]
110    #[inline(always)]
111    pub fn vregosen(&mut self) -> VREGOSEN_W {
112        VREGOSEN_W::new(self)
113    }
114    #[doc = "Bits 20:21 - Regulator Bias Programming Value in EM0/1"]
115    #[inline(always)]
116    pub fn biasprogem01(&mut self) -> BIASPROGEM01_W {
117        BIASPROGEM01_W::new(self)
118    }
119    #[doc = "Bits 24:25 - Regulator Bias Programming Value in EM2/3"]
120    #[inline(always)]
121    pub fn biasprogem23(&mut self) -> BIASPROGEM23_W {
122        BIASPROGEM23_W::new(self)
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
132pub struct CTRL_SPEC;
133impl crate::RegisterSpec for CTRL_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
137impl crate::Readable for CTRL_SPEC {
138    type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
141impl crate::Writable for CTRL_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets CTRL to value 0"]
145impl crate::Resettable for CTRL_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0
149    }
150}
efm32gg330_pac/usb/ctrl.rs

efm32gg330_pac/usb/
ctrl.rs
