efm32gg290_pac/cmu/
hfperclken0.rs

1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type USART0_R = crate::BitReader<bool>;
39#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type USART1_R = crate::BitReader<bool>;
43#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
46pub type USART2_R = crate::BitReader<bool>;
47#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
48pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
50pub type UART0_R = crate::BitReader<bool>;
51#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
52pub type UART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `UART1` reader - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
54pub type UART1_R = crate::BitReader<bool>;
55#[doc = "Field `UART1` writer - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
56pub type UART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
58pub type TIMER0_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
60pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
62pub type TIMER1_R = crate::BitReader<bool>;
63#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
64pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
66pub type TIMER2_R = crate::BitReader<bool>;
67#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
68pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `TIMER3` reader - Timer 3 Clock Enable"]
70pub type TIMER3_R = crate::BitReader<bool>;
71#[doc = "Field `TIMER3` writer - Timer 3 Clock Enable"]
72pub type TIMER3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
74pub type ACMP0_R = crate::BitReader<bool>;
75#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
76pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
78pub type ACMP1_R = crate::BitReader<bool>;
79#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
80pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
81#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
82pub type I2C0_R = crate::BitReader<bool>;
83#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
84pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
85#[doc = "Field `I2C1` reader - I2C 1 Clock Enable"]
86pub type I2C1_R = crate::BitReader<bool>;
87#[doc = "Field `I2C1` writer - I2C 1 Clock Enable"]
88pub type I2C1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
89#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
90pub type GPIO_R = crate::BitReader<bool>;
91#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
92pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 13>;
93#[doc = "Field `VCMP` reader - Voltage Comparator Clock Enable"]
94pub type VCMP_R = crate::BitReader<bool>;
95#[doc = "Field `VCMP` writer - Voltage Comparator Clock Enable"]
96pub type VCMP_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 14>;
97#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
98pub type PRS_R = crate::BitReader<bool>;
99#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
100pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 15>;
101#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
102pub type ADC0_R = crate::BitReader<bool>;
103#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
104pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 16>;
105#[doc = "Field `DAC0` reader - Digital to Analog Converter 0 Clock Enable"]
106pub type DAC0_R = crate::BitReader<bool>;
107#[doc = "Field `DAC0` writer - Digital to Analog Converter 0 Clock Enable"]
108pub type DAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 17>;
109impl R {
110    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
111    #[inline(always)]
112    pub fn usart0(&self) -> USART0_R {
113        USART0_R::new((self.bits & 1) != 0)
114    }
115    #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
116    #[inline(always)]
117    pub fn usart1(&self) -> USART1_R {
118        USART1_R::new(((self.bits >> 1) & 1) != 0)
119    }
120    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
121    #[inline(always)]
122    pub fn usart2(&self) -> USART2_R {
123        USART2_R::new(((self.bits >> 2) & 1) != 0)
124    }
125    #[doc = "Bit 3 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
126    #[inline(always)]
127    pub fn uart0(&self) -> UART0_R {
128        UART0_R::new(((self.bits >> 3) & 1) != 0)
129    }
130    #[doc = "Bit 4 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
131    #[inline(always)]
132    pub fn uart1(&self) -> UART1_R {
133        UART1_R::new(((self.bits >> 4) & 1) != 0)
134    }
135    #[doc = "Bit 5 - Timer 0 Clock Enable"]
136    #[inline(always)]
137    pub fn timer0(&self) -> TIMER0_R {
138        TIMER0_R::new(((self.bits >> 5) & 1) != 0)
139    }
140    #[doc = "Bit 6 - Timer 1 Clock Enable"]
141    #[inline(always)]
142    pub fn timer1(&self) -> TIMER1_R {
143        TIMER1_R::new(((self.bits >> 6) & 1) != 0)
144    }
145    #[doc = "Bit 7 - Timer 2 Clock Enable"]
146    #[inline(always)]
147    pub fn timer2(&self) -> TIMER2_R {
148        TIMER2_R::new(((self.bits >> 7) & 1) != 0)
149    }
150    #[doc = "Bit 8 - Timer 3 Clock Enable"]
151    #[inline(always)]
152    pub fn timer3(&self) -> TIMER3_R {
153        TIMER3_R::new(((self.bits >> 8) & 1) != 0)
154    }
155    #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
156    #[inline(always)]
157    pub fn acmp0(&self) -> ACMP0_R {
158        ACMP0_R::new(((self.bits >> 9) & 1) != 0)
159    }
160    #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
161    #[inline(always)]
162    pub fn acmp1(&self) -> ACMP1_R {
163        ACMP1_R::new(((self.bits >> 10) & 1) != 0)
164    }
165    #[doc = "Bit 11 - I2C 0 Clock Enable"]
166    #[inline(always)]
167    pub fn i2c0(&self) -> I2C0_R {
168        I2C0_R::new(((self.bits >> 11) & 1) != 0)
169    }
170    #[doc = "Bit 12 - I2C 1 Clock Enable"]
171    #[inline(always)]
172    pub fn i2c1(&self) -> I2C1_R {
173        I2C1_R::new(((self.bits >> 12) & 1) != 0)
174    }
175    #[doc = "Bit 13 - General purpose Input/Output Clock Enable"]
176    #[inline(always)]
177    pub fn gpio(&self) -> GPIO_R {
178        GPIO_R::new(((self.bits >> 13) & 1) != 0)
179    }
180    #[doc = "Bit 14 - Voltage Comparator Clock Enable"]
181    #[inline(always)]
182    pub fn vcmp(&self) -> VCMP_R {
183        VCMP_R::new(((self.bits >> 14) & 1) != 0)
184    }
185    #[doc = "Bit 15 - Peripheral Reflex System Clock Enable"]
186    #[inline(always)]
187    pub fn prs(&self) -> PRS_R {
188        PRS_R::new(((self.bits >> 15) & 1) != 0)
189    }
190    #[doc = "Bit 16 - Analog to Digital Converter 0 Clock Enable"]
191    #[inline(always)]
192    pub fn adc0(&self) -> ADC0_R {
193        ADC0_R::new(((self.bits >> 16) & 1) != 0)
194    }
195    #[doc = "Bit 17 - Digital to Analog Converter 0 Clock Enable"]
196    #[inline(always)]
197    pub fn dac0(&self) -> DAC0_R {
198        DAC0_R::new(((self.bits >> 17) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bit 0 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
203    #[inline(always)]
204    pub fn usart0(&mut self) -> USART0_W {
205        USART0_W::new(self)
206    }
207    #[doc = "Bit 1 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
208    #[inline(always)]
209    pub fn usart1(&mut self) -> USART1_W {
210        USART1_W::new(self)
211    }
212    #[doc = "Bit 2 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
213    #[inline(always)]
214    pub fn usart2(&mut self) -> USART2_W {
215        USART2_W::new(self)
216    }
217    #[doc = "Bit 3 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
218    #[inline(always)]
219    pub fn uart0(&mut self) -> UART0_W {
220        UART0_W::new(self)
221    }
222    #[doc = "Bit 4 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
223    #[inline(always)]
224    pub fn uart1(&mut self) -> UART1_W {
225        UART1_W::new(self)
226    }
227    #[doc = "Bit 5 - Timer 0 Clock Enable"]
228    #[inline(always)]
229    pub fn timer0(&mut self) -> TIMER0_W {
230        TIMER0_W::new(self)
231    }
232    #[doc = "Bit 6 - Timer 1 Clock Enable"]
233    #[inline(always)]
234    pub fn timer1(&mut self) -> TIMER1_W {
235        TIMER1_W::new(self)
236    }
237    #[doc = "Bit 7 - Timer 2 Clock Enable"]
238    #[inline(always)]
239    pub fn timer2(&mut self) -> TIMER2_W {
240        TIMER2_W::new(self)
241    }
242    #[doc = "Bit 8 - Timer 3 Clock Enable"]
243    #[inline(always)]
244    pub fn timer3(&mut self) -> TIMER3_W {
245        TIMER3_W::new(self)
246    }
247    #[doc = "Bit 9 - Analog Comparator 0 Clock Enable"]
248    #[inline(always)]
249    pub fn acmp0(&mut self) -> ACMP0_W {
250        ACMP0_W::new(self)
251    }
252    #[doc = "Bit 10 - Analog Comparator 1 Clock Enable"]
253    #[inline(always)]
254    pub fn acmp1(&mut self) -> ACMP1_W {
255        ACMP1_W::new(self)
256    }
257    #[doc = "Bit 11 - I2C 0 Clock Enable"]
258    #[inline(always)]
259    pub fn i2c0(&mut self) -> I2C0_W {
260        I2C0_W::new(self)
261    }
262    #[doc = "Bit 12 - I2C 1 Clock Enable"]
263    #[inline(always)]
264    pub fn i2c1(&mut self) -> I2C1_W {
265        I2C1_W::new(self)
266    }
267    #[doc = "Bit 13 - General purpose Input/Output Clock Enable"]
268    #[inline(always)]
269    pub fn gpio(&mut self) -> GPIO_W {
270        GPIO_W::new(self)
271    }
272    #[doc = "Bit 14 - Voltage Comparator Clock Enable"]
273    #[inline(always)]
274    pub fn vcmp(&mut self) -> VCMP_W {
275        VCMP_W::new(self)
276    }
277    #[doc = "Bit 15 - Peripheral Reflex System Clock Enable"]
278    #[inline(always)]
279    pub fn prs(&mut self) -> PRS_W {
280        PRS_W::new(self)
281    }
282    #[doc = "Bit 16 - Analog to Digital Converter 0 Clock Enable"]
283    #[inline(always)]
284    pub fn adc0(&mut self) -> ADC0_W {
285        ADC0_W::new(self)
286    }
287    #[doc = "Bit 17 - Digital to Analog Converter 0 Clock Enable"]
288    #[inline(always)]
289    pub fn dac0(&mut self) -> DAC0_W {
290        DAC0_W::new(self)
291    }
292    #[doc = "Writes raw bits to the register."]
293    #[inline(always)]
294    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
295        self.0.bits(bits);
296        self
297    }
298}
299#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
300pub struct HFPERCLKEN0_SPEC;
301impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
302    type Ux = u32;
303}
304#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
305impl crate::Readable for HFPERCLKEN0_SPEC {
306    type Reader = R;
307}
308#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
309impl crate::Writable for HFPERCLKEN0_SPEC {
310    type Writer = W;
311}
312#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
313impl crate::Resettable for HFPERCLKEN0_SPEC {
314    #[inline(always)]
315    fn reset_value() -> Self::Ux {
316        0
317    }
318}
efm32gg290_pac/cmu/hfperclken0.rs

efm32gg290_pac/cmu/
hfperclken0.rs
