efm32gg290_pac/ebi/
tftctrl.rs

1#[doc = "Register `TFTCTRL` reader"]
2pub struct R(crate::R<TFTCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TFTCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TFTCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TFTCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TFTCTRL` writer"]
17pub struct W(crate::W<TFTCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TFTCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TFTCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TFTCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "TFT Direct Drive Mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum DD_A {
41    #[doc = "0: Direct Drive is disabled."]
42    DISABLED = 0,
43    #[doc = "1: Direct Drive from internal memory enabled and started."]
44    INTERNAL = 1,
45    #[doc = "2: Direct Drive from external memory enabled and started."]
46    EXTERNAL = 2,
47}
48impl From<DD_A> for u8 {
49    #[inline(always)]
50    fn from(variant: DD_A) -> Self {
51        variant as _
52    }
53}
54#[doc = "Field `DD` reader - TFT Direct Drive Mode"]
55pub type DD_R = crate::FieldReader<u8, DD_A>;
56impl DD_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<DD_A> {
60        match self.bits {
61            0 => Some(DD_A::DISABLED),
62            1 => Some(DD_A::INTERNAL),
63            2 => Some(DD_A::EXTERNAL),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `DISABLED`"]
68    #[inline(always)]
69    pub fn is_disabled(&self) -> bool {
70        *self == DD_A::DISABLED
71    }
72    #[doc = "Checks if the value of the field is `INTERNAL`"]
73    #[inline(always)]
74    pub fn is_internal(&self) -> bool {
75        *self == DD_A::INTERNAL
76    }
77    #[doc = "Checks if the value of the field is `EXTERNAL`"]
78    #[inline(always)]
79    pub fn is_external(&self) -> bool {
80        *self == DD_A::EXTERNAL
81    }
82}
83#[doc = "Field `DD` writer - TFT Direct Drive Mode"]
84pub type DD_W<'a> = crate::FieldWriter<'a, u32, TFTCTRL_SPEC, u8, DD_A, 2, 0>;
85impl<'a> DD_W<'a> {
86    #[doc = "Direct Drive is disabled."]
87    #[inline(always)]
88    pub fn disabled(self) -> &'a mut W {
89        self.variant(DD_A::DISABLED)
90    }
91    #[doc = "Direct Drive from internal memory enabled and started."]
92    #[inline(always)]
93    pub fn internal(self) -> &'a mut W {
94        self.variant(DD_A::INTERNAL)
95    }
96    #[doc = "Direct Drive from external memory enabled and started."]
97    #[inline(always)]
98    pub fn external(self) -> &'a mut W {
99        self.variant(DD_A::EXTERNAL)
100    }
101}
102#[doc = "TFT Mask and Blend Mode\n\nValue on reset: 0"]
103#[derive(Clone, Copy, Debug, PartialEq)]
104#[repr(u8)]
105pub enum MASKBLEND_A {
106    #[doc = "0: Masking and Blending are disabled."]
107    DISABLED = 0,
108    #[doc = "1: Internal Masking is enabled."]
109    IMASK = 1,
110    #[doc = "2: Internal Alpha Blending is enabled."]
111    IALPHA = 2,
112    #[doc = "3: Internal Masking and Alpha Blending are enabled."]
113    IMASKIALPHA = 3,
114    #[doc = "5: External Masking is enabled."]
115    EMASK = 5,
116    #[doc = "6: External Alpha Blending is enabled."]
117    EALPHA = 6,
118    #[doc = "7: External Masking and Alpha Blending are enabled."]
119    EMASKEALPHA = 7,
120}
121impl From<MASKBLEND_A> for u8 {
122    #[inline(always)]
123    fn from(variant: MASKBLEND_A) -> Self {
124        variant as _
125    }
126}
127#[doc = "Field `MASKBLEND` reader - TFT Mask and Blend Mode"]
128pub type MASKBLEND_R = crate::FieldReader<u8, MASKBLEND_A>;
129impl MASKBLEND_R {
130    #[doc = "Get enumerated values variant"]
131    #[inline(always)]
132    pub fn variant(&self) -> Option<MASKBLEND_A> {
133        match self.bits {
134            0 => Some(MASKBLEND_A::DISABLED),
135            1 => Some(MASKBLEND_A::IMASK),
136            2 => Some(MASKBLEND_A::IALPHA),
137            3 => Some(MASKBLEND_A::IMASKIALPHA),
138            5 => Some(MASKBLEND_A::EMASK),
139            6 => Some(MASKBLEND_A::EALPHA),
140            7 => Some(MASKBLEND_A::EMASKEALPHA),
141            _ => None,
142        }
143    }
144    #[doc = "Checks if the value of the field is `DISABLED`"]
145    #[inline(always)]
146    pub fn is_disabled(&self) -> bool {
147        *self == MASKBLEND_A::DISABLED
148    }
149    #[doc = "Checks if the value of the field is `IMASK`"]
150    #[inline(always)]
151    pub fn is_imask(&self) -> bool {
152        *self == MASKBLEND_A::IMASK
153    }
154    #[doc = "Checks if the value of the field is `IALPHA`"]
155    #[inline(always)]
156    pub fn is_ialpha(&self) -> bool {
157        *self == MASKBLEND_A::IALPHA
158    }
159    #[doc = "Checks if the value of the field is `IMASKIALPHA`"]
160    #[inline(always)]
161    pub fn is_imaskialpha(&self) -> bool {
162        *self == MASKBLEND_A::IMASKIALPHA
163    }
164    #[doc = "Checks if the value of the field is `EMASK`"]
165    #[inline(always)]
166    pub fn is_emask(&self) -> bool {
167        *self == MASKBLEND_A::EMASK
168    }
169    #[doc = "Checks if the value of the field is `EALPHA`"]
170    #[inline(always)]
171    pub fn is_ealpha(&self) -> bool {
172        *self == MASKBLEND_A::EALPHA
173    }
174    #[doc = "Checks if the value of the field is `EMASKEALPHA`"]
175    #[inline(always)]
176    pub fn is_emaskealpha(&self) -> bool {
177        *self == MASKBLEND_A::EMASKEALPHA
178    }
179}
180#[doc = "Field `MASKBLEND` writer - TFT Mask and Blend Mode"]
181pub type MASKBLEND_W<'a> = crate::FieldWriter<'a, u32, TFTCTRL_SPEC, u8, MASKBLEND_A, 3, 2>;
182impl<'a> MASKBLEND_W<'a> {
183    #[doc = "Masking and Blending are disabled."]
184    #[inline(always)]
185    pub fn disabled(self) -> &'a mut W {
186        self.variant(MASKBLEND_A::DISABLED)
187    }
188    #[doc = "Internal Masking is enabled."]
189    #[inline(always)]
190    pub fn imask(self) -> &'a mut W {
191        self.variant(MASKBLEND_A::IMASK)
192    }
193    #[doc = "Internal Alpha Blending is enabled."]
194    #[inline(always)]
195    pub fn ialpha(self) -> &'a mut W {
196        self.variant(MASKBLEND_A::IALPHA)
197    }
198    #[doc = "Internal Masking and Alpha Blending are enabled."]
199    #[inline(always)]
200    pub fn imaskialpha(self) -> &'a mut W {
201        self.variant(MASKBLEND_A::IMASKIALPHA)
202    }
203    #[doc = "External Masking is enabled."]
204    #[inline(always)]
205    pub fn emask(self) -> &'a mut W {
206        self.variant(MASKBLEND_A::EMASK)
207    }
208    #[doc = "External Alpha Blending is enabled."]
209    #[inline(always)]
210    pub fn ealpha(self) -> &'a mut W {
211        self.variant(MASKBLEND_A::EALPHA)
212    }
213    #[doc = "External Masking and Alpha Blending are enabled."]
214    #[inline(always)]
215    pub fn emaskealpha(self) -> &'a mut W {
216        self.variant(MASKBLEND_A::EMASKEALPHA)
217    }
218}
219#[doc = "Field `SHIFTDCLKEN` reader - TFT EBI_DCLK Shift Enable"]
220pub type SHIFTDCLKEN_R = crate::BitReader<bool>;
221#[doc = "Field `SHIFTDCLKEN` writer - TFT EBI_DCLK Shift Enable"]
222pub type SHIFTDCLKEN_W<'a> = crate::BitWriter<'a, u32, TFTCTRL_SPEC, bool, 8>;
223#[doc = "Field `FBCTRIG` reader - TFT Frame Base Copy Trigger"]
224pub type FBCTRIG_R = crate::BitReader<bool>;
225#[doc = "Field `FBCTRIG` writer - TFT Frame Base Copy Trigger"]
226pub type FBCTRIG_W<'a> = crate::BitWriter<'a, u32, TFTCTRL_SPEC, bool, 9>;
227#[doc = "Interleave Mode\n\nValue on reset: 0"]
228#[derive(Clone, Copy, Debug, PartialEq)]
229#[repr(u8)]
230pub enum INTERLEAVE_A {
231    #[doc = "0: Allow unlimited interleaved EBI accesses per EBI_DCLK period. This can cause jitter on the EBI_DCLK"]
232    UNLIMITED = 0,
233    #[doc = "1: Allow 1 interleaved EBI access per EBI_DCLK period."]
234    ONEPERDCLK = 1,
235    #[doc = "2: Only allow EBI accesses during TFT porches."]
236    PORCH = 2,
237}
238impl From<INTERLEAVE_A> for u8 {
239    #[inline(always)]
240    fn from(variant: INTERLEAVE_A) -> Self {
241        variant as _
242    }
243}
244#[doc = "Field `INTERLEAVE` reader - Interleave Mode"]
245pub type INTERLEAVE_R = crate::FieldReader<u8, INTERLEAVE_A>;
246impl INTERLEAVE_R {
247    #[doc = "Get enumerated values variant"]
248    #[inline(always)]
249    pub fn variant(&self) -> Option<INTERLEAVE_A> {
250        match self.bits {
251            0 => Some(INTERLEAVE_A::UNLIMITED),
252            1 => Some(INTERLEAVE_A::ONEPERDCLK),
253            2 => Some(INTERLEAVE_A::PORCH),
254            _ => None,
255        }
256    }
257    #[doc = "Checks if the value of the field is `UNLIMITED`"]
258    #[inline(always)]
259    pub fn is_unlimited(&self) -> bool {
260        *self == INTERLEAVE_A::UNLIMITED
261    }
262    #[doc = "Checks if the value of the field is `ONEPERDCLK`"]
263    #[inline(always)]
264    pub fn is_oneperdclk(&self) -> bool {
265        *self == INTERLEAVE_A::ONEPERDCLK
266    }
267    #[doc = "Checks if the value of the field is `PORCH`"]
268    #[inline(always)]
269    pub fn is_porch(&self) -> bool {
270        *self == INTERLEAVE_A::PORCH
271    }
272}
273#[doc = "Field `INTERLEAVE` writer - Interleave Mode"]
274pub type INTERLEAVE_W<'a> = crate::FieldWriter<'a, u32, TFTCTRL_SPEC, u8, INTERLEAVE_A, 2, 10>;
275impl<'a> INTERLEAVE_W<'a> {
276    #[doc = "Allow unlimited interleaved EBI accesses per EBI_DCLK period. This can cause jitter on the EBI_DCLK"]
277    #[inline(always)]
278    pub fn unlimited(self) -> &'a mut W {
279        self.variant(INTERLEAVE_A::UNLIMITED)
280    }
281    #[doc = "Allow 1 interleaved EBI access per EBI_DCLK period."]
282    #[inline(always)]
283    pub fn oneperdclk(self) -> &'a mut W {
284        self.variant(INTERLEAVE_A::ONEPERDCLK)
285    }
286    #[doc = "Only allow EBI accesses during TFT porches."]
287    #[inline(always)]
288    pub fn porch(self) -> &'a mut W {
289        self.variant(INTERLEAVE_A::PORCH)
290    }
291}
292#[doc = "Field `COLOR1SRC` reader - Masking/Alpha Blending Color1 Source"]
293pub type COLOR1SRC_R = crate::BitReader<bool>;
294#[doc = "Field `COLOR1SRC` writer - Masking/Alpha Blending Color1 Source"]
295pub type COLOR1SRC_W<'a> = crate::BitWriter<'a, u32, TFTCTRL_SPEC, bool, 12>;
296#[doc = "Field `WIDTH` reader - TFT Transaction Width"]
297pub type WIDTH_R = crate::BitReader<bool>;
298#[doc = "Field `WIDTH` writer - TFT Transaction Width"]
299pub type WIDTH_W<'a> = crate::BitWriter<'a, u32, TFTCTRL_SPEC, bool, 16>;
300#[doc = "Graphics Bank\n\nValue on reset: 0"]
301#[derive(Clone, Copy, Debug, PartialEq)]
302#[repr(u8)]
303pub enum BANKSEL_A {
304    #[doc = "0: Memory bank 0 is used for Direct Drive, Masking, and Alpha Blending."]
305    BANK0 = 0,
306    #[doc = "1: Memory bank 1 is used for Direct Drive, Masking, and Alpha Blending."]
307    BANK1 = 1,
308    #[doc = "2: Memory bank 2 is used for Direct Drive, Masking, and Alpha Blending."]
309    BANK2 = 2,
310    #[doc = "3: Memory bank 3 is used for Direct Drive, Masking, and Alpha Blending."]
311    BANK3 = 3,
312}
313impl From<BANKSEL_A> for u8 {
314    #[inline(always)]
315    fn from(variant: BANKSEL_A) -> Self {
316        variant as _
317    }
318}
319#[doc = "Field `BANKSEL` reader - Graphics Bank"]
320pub type BANKSEL_R = crate::FieldReader<u8, BANKSEL_A>;
321impl BANKSEL_R {
322    #[doc = "Get enumerated values variant"]
323    #[inline(always)]
324    pub fn variant(&self) -> BANKSEL_A {
325        match self.bits {
326            0 => BANKSEL_A::BANK0,
327            1 => BANKSEL_A::BANK1,
328            2 => BANKSEL_A::BANK2,
329            3 => BANKSEL_A::BANK3,
330            _ => unreachable!(),
331        }
332    }
333    #[doc = "Checks if the value of the field is `BANK0`"]
334    #[inline(always)]
335    pub fn is_bank0(&self) -> bool {
336        *self == BANKSEL_A::BANK0
337    }
338    #[doc = "Checks if the value of the field is `BANK1`"]
339    #[inline(always)]
340    pub fn is_bank1(&self) -> bool {
341        *self == BANKSEL_A::BANK1
342    }
343    #[doc = "Checks if the value of the field is `BANK2`"]
344    #[inline(always)]
345    pub fn is_bank2(&self) -> bool {
346        *self == BANKSEL_A::BANK2
347    }
348    #[doc = "Checks if the value of the field is `BANK3`"]
349    #[inline(always)]
350    pub fn is_bank3(&self) -> bool {
351        *self == BANKSEL_A::BANK3
352    }
353}
354#[doc = "Field `BANKSEL` writer - Graphics Bank"]
355pub type BANKSEL_W<'a> = crate::FieldWriterSafe<'a, u32, TFTCTRL_SPEC, u8, BANKSEL_A, 2, 20>;
356impl<'a> BANKSEL_W<'a> {
357    #[doc = "Memory bank 0 is used for Direct Drive, Masking, and Alpha Blending."]
358    #[inline(always)]
359    pub fn bank0(self) -> &'a mut W {
360        self.variant(BANKSEL_A::BANK0)
361    }
362    #[doc = "Memory bank 1 is used for Direct Drive, Masking, and Alpha Blending."]
363    #[inline(always)]
364    pub fn bank1(self) -> &'a mut W {
365        self.variant(BANKSEL_A::BANK1)
366    }
367    #[doc = "Memory bank 2 is used for Direct Drive, Masking, and Alpha Blending."]
368    #[inline(always)]
369    pub fn bank2(self) -> &'a mut W {
370        self.variant(BANKSEL_A::BANK2)
371    }
372    #[doc = "Memory bank 3 is used for Direct Drive, Masking, and Alpha Blending."]
373    #[inline(always)]
374    pub fn bank3(self) -> &'a mut W {
375        self.variant(BANKSEL_A::BANK3)
376    }
377}
378#[doc = "Field `RGBMODE` reader - TFT RGB Mode"]
379pub type RGBMODE_R = crate::BitReader<bool>;
380#[doc = "Field `RGBMODE` writer - TFT RGB Mode"]
381pub type RGBMODE_W<'a> = crate::BitWriter<'a, u32, TFTCTRL_SPEC, bool, 24>;
382impl R {
383    #[doc = "Bits 0:1 - TFT Direct Drive Mode"]
384    #[inline(always)]
385    pub fn dd(&self) -> DD_R {
386        DD_R::new((self.bits & 3) as u8)
387    }
388    #[doc = "Bits 2:4 - TFT Mask and Blend Mode"]
389    #[inline(always)]
390    pub fn maskblend(&self) -> MASKBLEND_R {
391        MASKBLEND_R::new(((self.bits >> 2) & 7) as u8)
392    }
393    #[doc = "Bit 8 - TFT EBI_DCLK Shift Enable"]
394    #[inline(always)]
395    pub fn shiftdclken(&self) -> SHIFTDCLKEN_R {
396        SHIFTDCLKEN_R::new(((self.bits >> 8) & 1) != 0)
397    }
398    #[doc = "Bit 9 - TFT Frame Base Copy Trigger"]
399    #[inline(always)]
400    pub fn fbctrig(&self) -> FBCTRIG_R {
401        FBCTRIG_R::new(((self.bits >> 9) & 1) != 0)
402    }
403    #[doc = "Bits 10:11 - Interleave Mode"]
404    #[inline(always)]
405    pub fn interleave(&self) -> INTERLEAVE_R {
406        INTERLEAVE_R::new(((self.bits >> 10) & 3) as u8)
407    }
408    #[doc = "Bit 12 - Masking/Alpha Blending Color1 Source"]
409    #[inline(always)]
410    pub fn color1src(&self) -> COLOR1SRC_R {
411        COLOR1SRC_R::new(((self.bits >> 12) & 1) != 0)
412    }
413    #[doc = "Bit 16 - TFT Transaction Width"]
414    #[inline(always)]
415    pub fn width(&self) -> WIDTH_R {
416        WIDTH_R::new(((self.bits >> 16) & 1) != 0)
417    }
418    #[doc = "Bits 20:21 - Graphics Bank"]
419    #[inline(always)]
420    pub fn banksel(&self) -> BANKSEL_R {
421        BANKSEL_R::new(((self.bits >> 20) & 3) as u8)
422    }
423    #[doc = "Bit 24 - TFT RGB Mode"]
424    #[inline(always)]
425    pub fn rgbmode(&self) -> RGBMODE_R {
426        RGBMODE_R::new(((self.bits >> 24) & 1) != 0)
427    }
428}
429impl W {
430    #[doc = "Bits 0:1 - TFT Direct Drive Mode"]
431    #[inline(always)]
432    pub fn dd(&mut self) -> DD_W {
433        DD_W::new(self)
434    }
435    #[doc = "Bits 2:4 - TFT Mask and Blend Mode"]
436    #[inline(always)]
437    pub fn maskblend(&mut self) -> MASKBLEND_W {
438        MASKBLEND_W::new(self)
439    }
440    #[doc = "Bit 8 - TFT EBI_DCLK Shift Enable"]
441    #[inline(always)]
442    pub fn shiftdclken(&mut self) -> SHIFTDCLKEN_W {
443        SHIFTDCLKEN_W::new(self)
444    }
445    #[doc = "Bit 9 - TFT Frame Base Copy Trigger"]
446    #[inline(always)]
447    pub fn fbctrig(&mut self) -> FBCTRIG_W {
448        FBCTRIG_W::new(self)
449    }
450    #[doc = "Bits 10:11 - Interleave Mode"]
451    #[inline(always)]
452    pub fn interleave(&mut self) -> INTERLEAVE_W {
453        INTERLEAVE_W::new(self)
454    }
455    #[doc = "Bit 12 - Masking/Alpha Blending Color1 Source"]
456    #[inline(always)]
457    pub fn color1src(&mut self) -> COLOR1SRC_W {
458        COLOR1SRC_W::new(self)
459    }
460    #[doc = "Bit 16 - TFT Transaction Width"]
461    #[inline(always)]
462    pub fn width(&mut self) -> WIDTH_W {
463        WIDTH_W::new(self)
464    }
465    #[doc = "Bits 20:21 - Graphics Bank"]
466    #[inline(always)]
467    pub fn banksel(&mut self) -> BANKSEL_W {
468        BANKSEL_W::new(self)
469    }
470    #[doc = "Bit 24 - TFT RGB Mode"]
471    #[inline(always)]
472    pub fn rgbmode(&mut self) -> RGBMODE_W {
473        RGBMODE_W::new(self)
474    }
475    #[doc = "Writes raw bits to the register."]
476    #[inline(always)]
477    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
478        self.0.bits(bits);
479        self
480    }
481}
482#[doc = "TFT Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tftctrl](index.html) module"]
483pub struct TFTCTRL_SPEC;
484impl crate::RegisterSpec for TFTCTRL_SPEC {
485    type Ux = u32;
486}
487#[doc = "`read()` method returns [tftctrl::R](R) reader structure"]
488impl crate::Readable for TFTCTRL_SPEC {
489    type Reader = R;
490}
491#[doc = "`write(|w| ..)` method takes [tftctrl::W](W) writer structure"]
492impl crate::Writable for TFTCTRL_SPEC {
493    type Writer = W;
494}
495#[doc = "`reset()` method sets TFTCTRL to value 0"]
496impl crate::Resettable for TFTCTRL_SPEC {
497    #[inline(always)]
498    fn reset_value() -> Self::Ux {
499        0
500    }
501}
efm32gg290_pac/ebi/tftctrl.rs

efm32gg290_pac/ebi/
tftctrl.rs
