1#[doc = "Register `IFCR` reader"]
2pub struct R(crate::R<IFCR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IFCR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IFCR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IFCR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IFCR` writer"]
17pub struct W(crate::W<IFCR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IFCR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IFCR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IFCR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CMDCOM` reader - Command Complete"]
38pub type CMDCOM_R = crate::BitReader<bool>;
39#[doc = "Field `CMDCOM` writer - Command Complete"]
40pub type CMDCOM_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 0>;
41#[doc = "Field `TRANCOM` reader - Transfer Complete"]
42pub type TRANCOM_R = crate::BitReader<bool>;
43#[doc = "Field `TRANCOM` writer - Transfer Complete"]
44pub type TRANCOM_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 1>;
45#[doc = "Field `BLKGAPEVT` reader - Block Gap Event"]
46pub type BLKGAPEVT_R = crate::BitReader<bool>;
47#[doc = "Field `BLKGAPEVT` writer - Block Gap Event"]
48pub type BLKGAPEVT_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 2>;
49#[doc = "Field `DMAINT` reader - DMA Interrupt"]
50pub type DMAINT_R = crate::BitReader<bool>;
51#[doc = "Field `DMAINT` writer - DMA Interrupt"]
52pub type DMAINT_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 3>;
53#[doc = "Field `BFRWRRDY` reader - Buffer Write Ready"]
54pub type BFRWRRDY_R = crate::BitReader<bool>;
55#[doc = "Field `BFRWRRDY` writer - Buffer Write Ready"]
56pub type BFRWRRDY_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 4>;
57#[doc = "Field `BFRRDRDY` reader - Buffer Read Ready"]
58pub type BFRRDRDY_R = crate::BitReader<bool>;
59#[doc = "Field `BFRRDRDY` writer - Buffer Read Ready"]
60pub type BFRRDRDY_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 5>;
61#[doc = "Field `CARDINS` reader - Card Insertion"]
62pub type CARDINS_R = crate::BitReader<bool>;
63#[doc = "Field `CARDINS` writer - Card Insertion"]
64pub type CARDINS_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 6>;
65#[doc = "Field `CARDRM` reader - Card Removal"]
66pub type CARDRM_R = crate::BitReader<bool>;
67#[doc = "Field `CARDRM` writer - Card Removal"]
68pub type CARDRM_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 7>;
69#[doc = "Field `CARDINT` reader - Card Interrupt"]
70pub type CARDINT_R = crate::BitReader<bool>;
71#[doc = "Field `RETUNINGEVT` reader - Re-Tunning Event"]
72pub type RETUNINGEVT_R = crate::BitReader<bool>;
73#[doc = "Field `BOOTACKRCV` reader - Boot Ack Received"]
74pub type BOOTACKRCV_R = crate::BitReader<bool>;
75#[doc = "Field `BOOTACKRCV` writer - Boot Ack Received"]
76pub type BOOTACKRCV_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 13>;
77#[doc = "Field `BOOTTERMINATE` reader - Boot Terminate Interrupt"]
78pub type BOOTTERMINATE_R = crate::BitReader<bool>;
79#[doc = "Field `BOOTTERMINATE` writer - Boot Terminate Interrupt"]
80pub type BOOTTERMINATE_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 14>;
81#[doc = "Field `ERRINT` reader - Error Interrupt"]
82pub type ERRINT_R = crate::BitReader<bool>;
83#[doc = "Field `CMDTOUTERR` reader - Command Timeout Error"]
84pub type CMDTOUTERR_R = crate::BitReader<bool>;
85#[doc = "Field `CMDTOUTERR` writer - Command Timeout Error"]
86pub type CMDTOUTERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 16>;
87#[doc = "Field `CMDCRCERR` reader - CMD CRC Error"]
88pub type CMDCRCERR_R = crate::BitReader<bool>;
89#[doc = "Field `CMDCRCERR` writer - CMD CRC Error"]
90pub type CMDCRCERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 17>;
91#[doc = "Field `CMDENDBITERR` reader - Command End Bit Error"]
92pub type CMDENDBITERR_R = crate::BitReader<bool>;
93#[doc = "Field `CMDENDBITERR` writer - Command End Bit Error"]
94pub type CMDENDBITERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 18>;
95#[doc = "Field `CMDINDEXERR` reader - Command Index Error"]
96pub type CMDINDEXERR_R = crate::BitReader<bool>;
97#[doc = "Field `CMDINDEXERR` writer - Command Index Error"]
98pub type CMDINDEXERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 19>;
99#[doc = "Field `DATTOUTERR` reader - Data Time-out Error"]
100pub type DATTOUTERR_R = crate::BitReader<bool>;
101#[doc = "Field `DATTOUTERR` writer - Data Time-out Error"]
102pub type DATTOUTERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 20>;
103#[doc = "Field `DATCRCERR` reader - Data CRC Error"]
104pub type DATCRCERR_R = crate::BitReader<bool>;
105#[doc = "Field `DATCRCERR` writer - Data CRC Error"]
106pub type DATCRCERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 21>;
107#[doc = "Field `DATENDBITERR` reader - Data End Bit Error"]
108pub type DATENDBITERR_R = crate::BitReader<bool>;
109#[doc = "Field `DATENDBITERR` writer - Data End Bit Error"]
110pub type DATENDBITERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 22>;
111#[doc = "Field `CURRENTLIMITERR` reader - Current Limit Error"]
112pub type CURRENTLIMITERR_R = crate::BitReader<bool>;
113#[doc = "Field `CURRENTLIMITERR` writer - Current Limit Error"]
114pub type CURRENTLIMITERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 23>;
115#[doc = "Field `AUTOCMDERR` reader - Auto CMD Error"]
116pub type AUTOCMDERR_R = crate::BitReader<bool>;
117#[doc = "Field `AUTOCMDERR` writer - Auto CMD Error"]
118pub type AUTOCMDERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 24>;
119#[doc = "Field `ADMAERR` reader - ADMA Error"]
120pub type ADMAERR_R = crate::BitReader<bool>;
121#[doc = "Field `ADMAERR` writer - ADMA Error"]
122pub type ADMAERR_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 25>;
123#[doc = "Field `TARGETRESP` reader - Specific Error STAT"]
124pub type TARGETRESP_R = crate::BitReader<bool>;
125#[doc = "Field `TARGETRESP` writer - Specific Error STAT"]
126pub type TARGETRESP_W<'a> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, 28>;
127impl R {
128 #[doc = "Bit 0 - Command Complete"]
129 #[inline(always)]
130 pub fn cmdcom(&self) -> CMDCOM_R {
131 CMDCOM_R::new((self.bits & 1) != 0)
132 }
133 #[doc = "Bit 1 - Transfer Complete"]
134 #[inline(always)]
135 pub fn trancom(&self) -> TRANCOM_R {
136 TRANCOM_R::new(((self.bits >> 1) & 1) != 0)
137 }
138 #[doc = "Bit 2 - Block Gap Event"]
139 #[inline(always)]
140 pub fn blkgapevt(&self) -> BLKGAPEVT_R {
141 BLKGAPEVT_R::new(((self.bits >> 2) & 1) != 0)
142 }
143 #[doc = "Bit 3 - DMA Interrupt"]
144 #[inline(always)]
145 pub fn dmaint(&self) -> DMAINT_R {
146 DMAINT_R::new(((self.bits >> 3) & 1) != 0)
147 }
148 #[doc = "Bit 4 - Buffer Write Ready"]
149 #[inline(always)]
150 pub fn bfrwrrdy(&self) -> BFRWRRDY_R {
151 BFRWRRDY_R::new(((self.bits >> 4) & 1) != 0)
152 }
153 #[doc = "Bit 5 - Buffer Read Ready"]
154 #[inline(always)]
155 pub fn bfrrdrdy(&self) -> BFRRDRDY_R {
156 BFRRDRDY_R::new(((self.bits >> 5) & 1) != 0)
157 }
158 #[doc = "Bit 6 - Card Insertion"]
159 #[inline(always)]
160 pub fn cardins(&self) -> CARDINS_R {
161 CARDINS_R::new(((self.bits >> 6) & 1) != 0)
162 }
163 #[doc = "Bit 7 - Card Removal"]
164 #[inline(always)]
165 pub fn cardrm(&self) -> CARDRM_R {
166 CARDRM_R::new(((self.bits >> 7) & 1) != 0)
167 }
168 #[doc = "Bit 8 - Card Interrupt"]
169 #[inline(always)]
170 pub fn cardint(&self) -> CARDINT_R {
171 CARDINT_R::new(((self.bits >> 8) & 1) != 0)
172 }
173 #[doc = "Bit 12 - Re-Tunning Event"]
174 #[inline(always)]
175 pub fn retuningevt(&self) -> RETUNINGEVT_R {
176 RETUNINGEVT_R::new(((self.bits >> 12) & 1) != 0)
177 }
178 #[doc = "Bit 13 - Boot Ack Received"]
179 #[inline(always)]
180 pub fn bootackrcv(&self) -> BOOTACKRCV_R {
181 BOOTACKRCV_R::new(((self.bits >> 13) & 1) != 0)
182 }
183 #[doc = "Bit 14 - Boot Terminate Interrupt"]
184 #[inline(always)]
185 pub fn bootterminate(&self) -> BOOTTERMINATE_R {
186 BOOTTERMINATE_R::new(((self.bits >> 14) & 1) != 0)
187 }
188 #[doc = "Bit 15 - Error Interrupt"]
189 #[inline(always)]
190 pub fn errint(&self) -> ERRINT_R {
191 ERRINT_R::new(((self.bits >> 15) & 1) != 0)
192 }
193 #[doc = "Bit 16 - Command Timeout Error"]
194 #[inline(always)]
195 pub fn cmdtouterr(&self) -> CMDTOUTERR_R {
196 CMDTOUTERR_R::new(((self.bits >> 16) & 1) != 0)
197 }
198 #[doc = "Bit 17 - CMD CRC Error"]
199 #[inline(always)]
200 pub fn cmdcrcerr(&self) -> CMDCRCERR_R {
201 CMDCRCERR_R::new(((self.bits >> 17) & 1) != 0)
202 }
203 #[doc = "Bit 18 - Command End Bit Error"]
204 #[inline(always)]
205 pub fn cmdendbiterr(&self) -> CMDENDBITERR_R {
206 CMDENDBITERR_R::new(((self.bits >> 18) & 1) != 0)
207 }
208 #[doc = "Bit 19 - Command Index Error"]
209 #[inline(always)]
210 pub fn cmdindexerr(&self) -> CMDINDEXERR_R {
211 CMDINDEXERR_R::new(((self.bits >> 19) & 1) != 0)
212 }
213 #[doc = "Bit 20 - Data Time-out Error"]
214 #[inline(always)]
215 pub fn dattouterr(&self) -> DATTOUTERR_R {
216 DATTOUTERR_R::new(((self.bits >> 20) & 1) != 0)
217 }
218 #[doc = "Bit 21 - Data CRC Error"]
219 #[inline(always)]
220 pub fn datcrcerr(&self) -> DATCRCERR_R {
221 DATCRCERR_R::new(((self.bits >> 21) & 1) != 0)
222 }
223 #[doc = "Bit 22 - Data End Bit Error"]
224 #[inline(always)]
225 pub fn datendbiterr(&self) -> DATENDBITERR_R {
226 DATENDBITERR_R::new(((self.bits >> 22) & 1) != 0)
227 }
228 #[doc = "Bit 23 - Current Limit Error"]
229 #[inline(always)]
230 pub fn currentlimiterr(&self) -> CURRENTLIMITERR_R {
231 CURRENTLIMITERR_R::new(((self.bits >> 23) & 1) != 0)
232 }
233 #[doc = "Bit 24 - Auto CMD Error"]
234 #[inline(always)]
235 pub fn autocmderr(&self) -> AUTOCMDERR_R {
236 AUTOCMDERR_R::new(((self.bits >> 24) & 1) != 0)
237 }
238 #[doc = "Bit 25 - ADMA Error"]
239 #[inline(always)]
240 pub fn admaerr(&self) -> ADMAERR_R {
241 ADMAERR_R::new(((self.bits >> 25) & 1) != 0)
242 }
243 #[doc = "Bit 28 - Specific Error STAT"]
244 #[inline(always)]
245 pub fn targetresp(&self) -> TARGETRESP_R {
246 TARGETRESP_R::new(((self.bits >> 28) & 1) != 0)
247 }
248}
249impl W {
250 #[doc = "Bit 0 - Command Complete"]
251 #[inline(always)]
252 pub fn cmdcom(&mut self) -> CMDCOM_W {
253 CMDCOM_W::new(self)
254 }
255 #[doc = "Bit 1 - Transfer Complete"]
256 #[inline(always)]
257 pub fn trancom(&mut self) -> TRANCOM_W {
258 TRANCOM_W::new(self)
259 }
260 #[doc = "Bit 2 - Block Gap Event"]
261 #[inline(always)]
262 pub fn blkgapevt(&mut self) -> BLKGAPEVT_W {
263 BLKGAPEVT_W::new(self)
264 }
265 #[doc = "Bit 3 - DMA Interrupt"]
266 #[inline(always)]
267 pub fn dmaint(&mut self) -> DMAINT_W {
268 DMAINT_W::new(self)
269 }
270 #[doc = "Bit 4 - Buffer Write Ready"]
271 #[inline(always)]
272 pub fn bfrwrrdy(&mut self) -> BFRWRRDY_W {
273 BFRWRRDY_W::new(self)
274 }
275 #[doc = "Bit 5 - Buffer Read Ready"]
276 #[inline(always)]
277 pub fn bfrrdrdy(&mut self) -> BFRRDRDY_W {
278 BFRRDRDY_W::new(self)
279 }
280 #[doc = "Bit 6 - Card Insertion"]
281 #[inline(always)]
282 pub fn cardins(&mut self) -> CARDINS_W {
283 CARDINS_W::new(self)
284 }
285 #[doc = "Bit 7 - Card Removal"]
286 #[inline(always)]
287 pub fn cardrm(&mut self) -> CARDRM_W {
288 CARDRM_W::new(self)
289 }
290 #[doc = "Bit 13 - Boot Ack Received"]
291 #[inline(always)]
292 pub fn bootackrcv(&mut self) -> BOOTACKRCV_W {
293 BOOTACKRCV_W::new(self)
294 }
295 #[doc = "Bit 14 - Boot Terminate Interrupt"]
296 #[inline(always)]
297 pub fn bootterminate(&mut self) -> BOOTTERMINATE_W {
298 BOOTTERMINATE_W::new(self)
299 }
300 #[doc = "Bit 16 - Command Timeout Error"]
301 #[inline(always)]
302 pub fn cmdtouterr(&mut self) -> CMDTOUTERR_W {
303 CMDTOUTERR_W::new(self)
304 }
305 #[doc = "Bit 17 - CMD CRC Error"]
306 #[inline(always)]
307 pub fn cmdcrcerr(&mut self) -> CMDCRCERR_W {
308 CMDCRCERR_W::new(self)
309 }
310 #[doc = "Bit 18 - Command End Bit Error"]
311 #[inline(always)]
312 pub fn cmdendbiterr(&mut self) -> CMDENDBITERR_W {
313 CMDENDBITERR_W::new(self)
314 }
315 #[doc = "Bit 19 - Command Index Error"]
316 #[inline(always)]
317 pub fn cmdindexerr(&mut self) -> CMDINDEXERR_W {
318 CMDINDEXERR_W::new(self)
319 }
320 #[doc = "Bit 20 - Data Time-out Error"]
321 #[inline(always)]
322 pub fn dattouterr(&mut self) -> DATTOUTERR_W {
323 DATTOUTERR_W::new(self)
324 }
325 #[doc = "Bit 21 - Data CRC Error"]
326 #[inline(always)]
327 pub fn datcrcerr(&mut self) -> DATCRCERR_W {
328 DATCRCERR_W::new(self)
329 }
330 #[doc = "Bit 22 - Data End Bit Error"]
331 #[inline(always)]
332 pub fn datendbiterr(&mut self) -> DATENDBITERR_W {
333 DATENDBITERR_W::new(self)
334 }
335 #[doc = "Bit 23 - Current Limit Error"]
336 #[inline(always)]
337 pub fn currentlimiterr(&mut self) -> CURRENTLIMITERR_W {
338 CURRENTLIMITERR_W::new(self)
339 }
340 #[doc = "Bit 24 - Auto CMD Error"]
341 #[inline(always)]
342 pub fn autocmderr(&mut self) -> AUTOCMDERR_W {
343 AUTOCMDERR_W::new(self)
344 }
345 #[doc = "Bit 25 - ADMA Error"]
346 #[inline(always)]
347 pub fn admaerr(&mut self) -> ADMAERR_W {
348 ADMAERR_W::new(self)
349 }
350 #[doc = "Bit 28 - Specific Error STAT"]
351 #[inline(always)]
352 pub fn targetresp(&mut self) -> TARGETRESP_W {
353 TARGETRESP_W::new(self)
354 }
355 #[doc = "Writes raw bits to the register."]
356 #[inline(always)]
357 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
358 self.0.bits(bits);
359 self
360 }
361}
362#[doc = "Normal and Error Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifcr](index.html) module"]
363pub struct IFCR_SPEC;
364impl crate::RegisterSpec for IFCR_SPEC {
365 type Ux = u32;
366}
367#[doc = "`read()` method returns [ifcr::R](R) reader structure"]
368impl crate::Readable for IFCR_SPEC {
369 type Reader = R;
370}
371#[doc = "`write(|w| ..)` method takes [ifcr::W](W) writer structure"]
372impl crate::Writable for IFCR_SPEC {
373 type Writer = W;
374}
375#[doc = "`reset()` method sets IFCR to value 0"]
376impl crate::Resettable for IFCR_SPEC {
377 #[inline(always)]
378 fn reset_value() -> Self::Ux {
379 0
380 }
381}