1#[doc = "Register `PPUPATD0` reader"]
2pub struct R(crate::R<PPUPATD0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD0` writer"]
17pub struct W(crate::W<PPUPATD0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 access control bit"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 access control bit"]
40pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 0>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 access control bit"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 access control bit"]
44pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 1>;
45#[doc = "Field `ACMP2` reader - Analog Comparator 2 access control bit"]
46pub type ACMP2_R = crate::BitReader<bool>;
47#[doc = "Field `ACMP2` writer - Analog Comparator 2 access control bit"]
48pub type ACMP2_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 2>;
49#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 access control bit"]
50pub type ADC0_R = crate::BitReader<bool>;
51#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 access control bit"]
52pub type ADC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 3>;
53#[doc = "Field `ADC1` reader - Analog to Digital Converter 0 access control bit"]
54pub type ADC1_R = crate::BitReader<bool>;
55#[doc = "Field `ADC1` writer - Analog to Digital Converter 0 access control bit"]
56pub type ADC1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 4>;
57#[doc = "Field `CAN0` reader - CAN 0 access control bit"]
58pub type CAN0_R = crate::BitReader<bool>;
59#[doc = "Field `CAN0` writer - CAN 0 access control bit"]
60pub type CAN0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 5>;
61#[doc = "Field `CAN1` reader - CAN 1 access control bit"]
62pub type CAN1_R = crate::BitReader<bool>;
63#[doc = "Field `CAN1` writer - CAN 1 access control bit"]
64pub type CAN1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 6>;
65#[doc = "Field `CMU` reader - Clock Management Unit access control bit"]
66pub type CMU_R = crate::BitReader<bool>;
67#[doc = "Field `CMU` writer - Clock Management Unit access control bit"]
68pub type CMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 7>;
69#[doc = "Field `CRYOTIMER` reader - CRYOTIMER access control bit"]
70pub type CRYOTIMER_R = crate::BitReader<bool>;
71#[doc = "Field `CRYOTIMER` writer - CRYOTIMER access control bit"]
72pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 8>;
73#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator access control bit"]
74pub type CRYPTO0_R = crate::BitReader<bool>;
75#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator access control bit"]
76pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 9>;
77#[doc = "Field `CSEN` reader - Capacitive touch sense module access control bit"]
78pub type CSEN_R = crate::BitReader<bool>;
79#[doc = "Field `CSEN` writer - Capacitive touch sense module access control bit"]
80pub type CSEN_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 10>;
81#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 access control bit"]
82pub type VDAC0_R = crate::BitReader<bool>;
83#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 access control bit"]
84pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 11>;
85#[doc = "Field `PRS` reader - Peripheral Reflex System access control bit"]
86pub type PRS_R = crate::BitReader<bool>;
87#[doc = "Field `PRS` writer - Peripheral Reflex System access control bit"]
88pub type PRS_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 12>;
89#[doc = "Field `EBI` reader - External Bus Interface access control bit"]
90pub type EBI_R = crate::BitReader<bool>;
91#[doc = "Field `EBI` writer - External Bus Interface access control bit"]
92pub type EBI_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 13>;
93#[doc = "Field `EMU` reader - Energy Management Unit access control bit"]
94pub type EMU_R = crate::BitReader<bool>;
95#[doc = "Field `EMU` writer - Energy Management Unit access control bit"]
96pub type EMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 14>;
97#[doc = "Field `FPUEH` reader - FPU Exception Handler access control bit"]
98pub type FPUEH_R = crate::BitReader<bool>;
99#[doc = "Field `FPUEH` writer - FPU Exception Handler access control bit"]
100pub type FPUEH_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 15>;
101#[doc = "Field `GPCRC` reader - General Purpose CRC access control bit"]
102pub type GPCRC_R = crate::BitReader<bool>;
103#[doc = "Field `GPCRC` writer - General Purpose CRC access control bit"]
104pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 16>;
105#[doc = "Field `GPIO` reader - General purpose Input/Output access control bit"]
106pub type GPIO_R = crate::BitReader<bool>;
107#[doc = "Field `GPIO` writer - General purpose Input/Output access control bit"]
108pub type GPIO_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 17>;
109#[doc = "Field `I2C0` reader - I2C 0 access control bit"]
110pub type I2C0_R = crate::BitReader<bool>;
111#[doc = "Field `I2C0` writer - I2C 0 access control bit"]
112pub type I2C0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 18>;
113#[doc = "Field `I2C1` reader - I2C 1 access control bit"]
114pub type I2C1_R = crate::BitReader<bool>;
115#[doc = "Field `I2C1` writer - I2C 1 access control bit"]
116pub type I2C1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 19>;
117#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 access control bit"]
118pub type IDAC0_R = crate::BitReader<bool>;
119#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 access control bit"]
120pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 20>;
121#[doc = "Field `MSC` reader - Memory System Controller access control bit"]
122pub type MSC_R = crate::BitReader<bool>;
123#[doc = "Field `MSC` writer - Memory System Controller access control bit"]
124pub type MSC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 21>;
125#[doc = "Field `LCD` reader - Liquid Crystal Display Controller access control bit"]
126pub type LCD_R = crate::BitReader<bool>;
127#[doc = "Field `LCD` writer - Liquid Crystal Display Controller access control bit"]
128pub type LCD_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 22>;
129#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller access control bit"]
130pub type LDMA_R = crate::BitReader<bool>;
131#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller access control bit"]
132pub type LDMA_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 23>;
133#[doc = "Field `LESENSE` reader - Low Energy Sensor Interface access control bit"]
134pub type LESENSE_R = crate::BitReader<bool>;
135#[doc = "Field `LESENSE` writer - Low Energy Sensor Interface access control bit"]
136pub type LESENSE_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 24>;
137#[doc = "Field `LETIMER0` reader - Low Energy Timer 0 access control bit"]
138pub type LETIMER0_R = crate::BitReader<bool>;
139#[doc = "Field `LETIMER0` writer - Low Energy Timer 0 access control bit"]
140pub type LETIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 25>;
141#[doc = "Field `LETIMER1` reader - Low Energy Timer 1 access control bit"]
142pub type LETIMER1_R = crate::BitReader<bool>;
143#[doc = "Field `LETIMER1` writer - Low Energy Timer 1 access control bit"]
144pub type LETIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 26>;
145#[doc = "Field `LEUART0` reader - Low Energy UART 0 access control bit"]
146pub type LEUART0_R = crate::BitReader<bool>;
147#[doc = "Field `LEUART0` writer - Low Energy UART 0 access control bit"]
148pub type LEUART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 27>;
149#[doc = "Field `LEUART1` reader - Low Energy UART 1 access control bit"]
150pub type LEUART1_R = crate::BitReader<bool>;
151#[doc = "Field `LEUART1` writer - Low Energy UART 1 access control bit"]
152pub type LEUART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 28>;
153impl R {
154 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
155 #[inline(always)]
156 pub fn acmp0(&self) -> ACMP0_R {
157 ACMP0_R::new((self.bits & 1) != 0)
158 }
159 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
160 #[inline(always)]
161 pub fn acmp1(&self) -> ACMP1_R {
162 ACMP1_R::new(((self.bits >> 1) & 1) != 0)
163 }
164 #[doc = "Bit 2 - Analog Comparator 2 access control bit"]
165 #[inline(always)]
166 pub fn acmp2(&self) -> ACMP2_R {
167 ACMP2_R::new(((self.bits >> 2) & 1) != 0)
168 }
169 #[doc = "Bit 3 - Analog to Digital Converter 0 access control bit"]
170 #[inline(always)]
171 pub fn adc0(&self) -> ADC0_R {
172 ADC0_R::new(((self.bits >> 3) & 1) != 0)
173 }
174 #[doc = "Bit 4 - Analog to Digital Converter 0 access control bit"]
175 #[inline(always)]
176 pub fn adc1(&self) -> ADC1_R {
177 ADC1_R::new(((self.bits >> 4) & 1) != 0)
178 }
179 #[doc = "Bit 5 - CAN 0 access control bit"]
180 #[inline(always)]
181 pub fn can0(&self) -> CAN0_R {
182 CAN0_R::new(((self.bits >> 5) & 1) != 0)
183 }
184 #[doc = "Bit 6 - CAN 1 access control bit"]
185 #[inline(always)]
186 pub fn can1(&self) -> CAN1_R {
187 CAN1_R::new(((self.bits >> 6) & 1) != 0)
188 }
189 #[doc = "Bit 7 - Clock Management Unit access control bit"]
190 #[inline(always)]
191 pub fn cmu(&self) -> CMU_R {
192 CMU_R::new(((self.bits >> 7) & 1) != 0)
193 }
194 #[doc = "Bit 8 - CRYOTIMER access control bit"]
195 #[inline(always)]
196 pub fn cryotimer(&self) -> CRYOTIMER_R {
197 CRYOTIMER_R::new(((self.bits >> 8) & 1) != 0)
198 }
199 #[doc = "Bit 9 - Advanced Encryption Standard Accelerator access control bit"]
200 #[inline(always)]
201 pub fn crypto0(&self) -> CRYPTO0_R {
202 CRYPTO0_R::new(((self.bits >> 9) & 1) != 0)
203 }
204 #[doc = "Bit 10 - Capacitive touch sense module access control bit"]
205 #[inline(always)]
206 pub fn csen(&self) -> CSEN_R {
207 CSEN_R::new(((self.bits >> 10) & 1) != 0)
208 }
209 #[doc = "Bit 11 - Digital to Analog Converter 0 access control bit"]
210 #[inline(always)]
211 pub fn vdac0(&self) -> VDAC0_R {
212 VDAC0_R::new(((self.bits >> 11) & 1) != 0)
213 }
214 #[doc = "Bit 12 - Peripheral Reflex System access control bit"]
215 #[inline(always)]
216 pub fn prs(&self) -> PRS_R {
217 PRS_R::new(((self.bits >> 12) & 1) != 0)
218 }
219 #[doc = "Bit 13 - External Bus Interface access control bit"]
220 #[inline(always)]
221 pub fn ebi(&self) -> EBI_R {
222 EBI_R::new(((self.bits >> 13) & 1) != 0)
223 }
224 #[doc = "Bit 14 - Energy Management Unit access control bit"]
225 #[inline(always)]
226 pub fn emu(&self) -> EMU_R {
227 EMU_R::new(((self.bits >> 14) & 1) != 0)
228 }
229 #[doc = "Bit 15 - FPU Exception Handler access control bit"]
230 #[inline(always)]
231 pub fn fpueh(&self) -> FPUEH_R {
232 FPUEH_R::new(((self.bits >> 15) & 1) != 0)
233 }
234 #[doc = "Bit 16 - General Purpose CRC access control bit"]
235 #[inline(always)]
236 pub fn gpcrc(&self) -> GPCRC_R {
237 GPCRC_R::new(((self.bits >> 16) & 1) != 0)
238 }
239 #[doc = "Bit 17 - General purpose Input/Output access control bit"]
240 #[inline(always)]
241 pub fn gpio(&self) -> GPIO_R {
242 GPIO_R::new(((self.bits >> 17) & 1) != 0)
243 }
244 #[doc = "Bit 18 - I2C 0 access control bit"]
245 #[inline(always)]
246 pub fn i2c0(&self) -> I2C0_R {
247 I2C0_R::new(((self.bits >> 18) & 1) != 0)
248 }
249 #[doc = "Bit 19 - I2C 1 access control bit"]
250 #[inline(always)]
251 pub fn i2c1(&self) -> I2C1_R {
252 I2C1_R::new(((self.bits >> 19) & 1) != 0)
253 }
254 #[doc = "Bit 20 - Current Digital to Analog Converter 0 access control bit"]
255 #[inline(always)]
256 pub fn idac0(&self) -> IDAC0_R {
257 IDAC0_R::new(((self.bits >> 20) & 1) != 0)
258 }
259 #[doc = "Bit 21 - Memory System Controller access control bit"]
260 #[inline(always)]
261 pub fn msc(&self) -> MSC_R {
262 MSC_R::new(((self.bits >> 21) & 1) != 0)
263 }
264 #[doc = "Bit 22 - Liquid Crystal Display Controller access control bit"]
265 #[inline(always)]
266 pub fn lcd(&self) -> LCD_R {
267 LCD_R::new(((self.bits >> 22) & 1) != 0)
268 }
269 #[doc = "Bit 23 - Linked Direct Memory Access Controller access control bit"]
270 #[inline(always)]
271 pub fn ldma(&self) -> LDMA_R {
272 LDMA_R::new(((self.bits >> 23) & 1) != 0)
273 }
274 #[doc = "Bit 24 - Low Energy Sensor Interface access control bit"]
275 #[inline(always)]
276 pub fn lesense(&self) -> LESENSE_R {
277 LESENSE_R::new(((self.bits >> 24) & 1) != 0)
278 }
279 #[doc = "Bit 25 - Low Energy Timer 0 access control bit"]
280 #[inline(always)]
281 pub fn letimer0(&self) -> LETIMER0_R {
282 LETIMER0_R::new(((self.bits >> 25) & 1) != 0)
283 }
284 #[doc = "Bit 26 - Low Energy Timer 1 access control bit"]
285 #[inline(always)]
286 pub fn letimer1(&self) -> LETIMER1_R {
287 LETIMER1_R::new(((self.bits >> 26) & 1) != 0)
288 }
289 #[doc = "Bit 27 - Low Energy UART 0 access control bit"]
290 #[inline(always)]
291 pub fn leuart0(&self) -> LEUART0_R {
292 LEUART0_R::new(((self.bits >> 27) & 1) != 0)
293 }
294 #[doc = "Bit 28 - Low Energy UART 1 access control bit"]
295 #[inline(always)]
296 pub fn leuart1(&self) -> LEUART1_R {
297 LEUART1_R::new(((self.bits >> 28) & 1) != 0)
298 }
299}
300impl W {
301 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
302 #[inline(always)]
303 pub fn acmp0(&mut self) -> ACMP0_W {
304 ACMP0_W::new(self)
305 }
306 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
307 #[inline(always)]
308 pub fn acmp1(&mut self) -> ACMP1_W {
309 ACMP1_W::new(self)
310 }
311 #[doc = "Bit 2 - Analog Comparator 2 access control bit"]
312 #[inline(always)]
313 pub fn acmp2(&mut self) -> ACMP2_W {
314 ACMP2_W::new(self)
315 }
316 #[doc = "Bit 3 - Analog to Digital Converter 0 access control bit"]
317 #[inline(always)]
318 pub fn adc0(&mut self) -> ADC0_W {
319 ADC0_W::new(self)
320 }
321 #[doc = "Bit 4 - Analog to Digital Converter 0 access control bit"]
322 #[inline(always)]
323 pub fn adc1(&mut self) -> ADC1_W {
324 ADC1_W::new(self)
325 }
326 #[doc = "Bit 5 - CAN 0 access control bit"]
327 #[inline(always)]
328 pub fn can0(&mut self) -> CAN0_W {
329 CAN0_W::new(self)
330 }
331 #[doc = "Bit 6 - CAN 1 access control bit"]
332 #[inline(always)]
333 pub fn can1(&mut self) -> CAN1_W {
334 CAN1_W::new(self)
335 }
336 #[doc = "Bit 7 - Clock Management Unit access control bit"]
337 #[inline(always)]
338 pub fn cmu(&mut self) -> CMU_W {
339 CMU_W::new(self)
340 }
341 #[doc = "Bit 8 - CRYOTIMER access control bit"]
342 #[inline(always)]
343 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
344 CRYOTIMER_W::new(self)
345 }
346 #[doc = "Bit 9 - Advanced Encryption Standard Accelerator access control bit"]
347 #[inline(always)]
348 pub fn crypto0(&mut self) -> CRYPTO0_W {
349 CRYPTO0_W::new(self)
350 }
351 #[doc = "Bit 10 - Capacitive touch sense module access control bit"]
352 #[inline(always)]
353 pub fn csen(&mut self) -> CSEN_W {
354 CSEN_W::new(self)
355 }
356 #[doc = "Bit 11 - Digital to Analog Converter 0 access control bit"]
357 #[inline(always)]
358 pub fn vdac0(&mut self) -> VDAC0_W {
359 VDAC0_W::new(self)
360 }
361 #[doc = "Bit 12 - Peripheral Reflex System access control bit"]
362 #[inline(always)]
363 pub fn prs(&mut self) -> PRS_W {
364 PRS_W::new(self)
365 }
366 #[doc = "Bit 13 - External Bus Interface access control bit"]
367 #[inline(always)]
368 pub fn ebi(&mut self) -> EBI_W {
369 EBI_W::new(self)
370 }
371 #[doc = "Bit 14 - Energy Management Unit access control bit"]
372 #[inline(always)]
373 pub fn emu(&mut self) -> EMU_W {
374 EMU_W::new(self)
375 }
376 #[doc = "Bit 15 - FPU Exception Handler access control bit"]
377 #[inline(always)]
378 pub fn fpueh(&mut self) -> FPUEH_W {
379 FPUEH_W::new(self)
380 }
381 #[doc = "Bit 16 - General Purpose CRC access control bit"]
382 #[inline(always)]
383 pub fn gpcrc(&mut self) -> GPCRC_W {
384 GPCRC_W::new(self)
385 }
386 #[doc = "Bit 17 - General purpose Input/Output access control bit"]
387 #[inline(always)]
388 pub fn gpio(&mut self) -> GPIO_W {
389 GPIO_W::new(self)
390 }
391 #[doc = "Bit 18 - I2C 0 access control bit"]
392 #[inline(always)]
393 pub fn i2c0(&mut self) -> I2C0_W {
394 I2C0_W::new(self)
395 }
396 #[doc = "Bit 19 - I2C 1 access control bit"]
397 #[inline(always)]
398 pub fn i2c1(&mut self) -> I2C1_W {
399 I2C1_W::new(self)
400 }
401 #[doc = "Bit 20 - Current Digital to Analog Converter 0 access control bit"]
402 #[inline(always)]
403 pub fn idac0(&mut self) -> IDAC0_W {
404 IDAC0_W::new(self)
405 }
406 #[doc = "Bit 21 - Memory System Controller access control bit"]
407 #[inline(always)]
408 pub fn msc(&mut self) -> MSC_W {
409 MSC_W::new(self)
410 }
411 #[doc = "Bit 22 - Liquid Crystal Display Controller access control bit"]
412 #[inline(always)]
413 pub fn lcd(&mut self) -> LCD_W {
414 LCD_W::new(self)
415 }
416 #[doc = "Bit 23 - Linked Direct Memory Access Controller access control bit"]
417 #[inline(always)]
418 pub fn ldma(&mut self) -> LDMA_W {
419 LDMA_W::new(self)
420 }
421 #[doc = "Bit 24 - Low Energy Sensor Interface access control bit"]
422 #[inline(always)]
423 pub fn lesense(&mut self) -> LESENSE_W {
424 LESENSE_W::new(self)
425 }
426 #[doc = "Bit 25 - Low Energy Timer 0 access control bit"]
427 #[inline(always)]
428 pub fn letimer0(&mut self) -> LETIMER0_W {
429 LETIMER0_W::new(self)
430 }
431 #[doc = "Bit 26 - Low Energy Timer 1 access control bit"]
432 #[inline(always)]
433 pub fn letimer1(&mut self) -> LETIMER1_W {
434 LETIMER1_W::new(self)
435 }
436 #[doc = "Bit 27 - Low Energy UART 0 access control bit"]
437 #[inline(always)]
438 pub fn leuart0(&mut self) -> LEUART0_W {
439 LEUART0_W::new(self)
440 }
441 #[doc = "Bit 28 - Low Energy UART 1 access control bit"]
442 #[inline(always)]
443 pub fn leuart1(&mut self) -> LEUART1_W {
444 LEUART1_W::new(self)
445 }
446 #[doc = "Writes raw bits to the register."]
447 #[inline(always)]
448 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
449 self.0.bits(bits);
450 self
451 }
452}
453#[doc = "PPU Privilege Access Type Descriptor 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd0](index.html) module"]
454pub struct PPUPATD0_SPEC;
455impl crate::RegisterSpec for PPUPATD0_SPEC {
456 type Ux = u32;
457}
458#[doc = "`read()` method returns [ppupatd0::R](R) reader structure"]
459impl crate::Readable for PPUPATD0_SPEC {
460 type Reader = R;
461}
462#[doc = "`write(|w| ..)` method takes [ppupatd0::W](W) writer structure"]
463impl crate::Writable for PPUPATD0_SPEC {
464 type Writer = W;
465}
466#[doc = "`reset()` method sets PPUPATD0 to value 0"]
467impl crate::Resettable for PPUPATD0_SPEC {
468 #[inline(always)]
469 fn reset_value() -> Self::Ux {
470 0
471 }
472}