1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IEN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IEN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IEN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IEN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CMDCOMSEN` reader - Command Complete Signal Enable"]
38pub type CMDCOMSEN_R = crate::BitReader<bool>;
39#[doc = "Field `CMDCOMSEN` writer - Command Complete Signal Enable"]
40pub type CMDCOMSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `TRANCOMSEN` reader - Transfer Complete Signal Enable"]
42pub type TRANCOMSEN_R = crate::BitReader<bool>;
43#[doc = "Field `TRANCOMSEN` writer - Transfer Complete Signal Enable"]
44pub type TRANCOMSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `BLKGAPEVTSEN` reader - Block Gap Event Signal Enable"]
46pub type BLKGAPEVTSEN_R = crate::BitReader<bool>;
47#[doc = "Field `BLKGAPEVTSEN` writer - Block Gap Event Signal Enable"]
48pub type BLKGAPEVTSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `DMAINTSEN` reader - DMA Interrupt Signal Enable"]
50pub type DMAINTSEN_R = crate::BitReader<bool>;
51#[doc = "Field `DMAINTSEN` writer - DMA Interrupt Signal Enable"]
52pub type DMAINTSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `BUFWRRDYSEN` reader - Buffer Write Ready Signal Enable"]
54pub type BUFWRRDYSEN_R = crate::BitReader<bool>;
55#[doc = "Field `BUFWRRDYSEN` writer - Buffer Write Ready Signal Enable"]
56pub type BUFWRRDYSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `BUFRDRDYSEN` reader - Buffer Read Ready Signal Enable"]
58pub type BUFRDRDYSEN_R = crate::BitReader<bool>;
59#[doc = "Field `BUFRDRDYSEN` writer - Buffer Read Ready Signal Enable"]
60pub type BUFRDRDYSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `CARDINSSEN` reader - Card Insertion Signal Enable"]
62pub type CARDINSSEN_R = crate::BitReader<bool>;
63#[doc = "Field `CARDINSSEN` writer - Card Insertion Signal Enable"]
64pub type CARDINSSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `CARDREMSEN` reader - Card Removal Signal Enable"]
66pub type CARDREMSEN_R = crate::BitReader<bool>;
67#[doc = "Field `CARDREMSEN` writer - Card Removal Signal Enable"]
68pub type CARDREMSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 7>;
69#[doc = "Field `CARDINTSEN` reader - Card Interrupt Signal Enable"]
70pub type CARDINTSEN_R = crate::BitReader<bool>;
71#[doc = "Field `CARDINTSEN` writer - Card Interrupt Signal Enable"]
72pub type CARDINTSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
73#[doc = "Field `RETUNINGEVTSEN` reader - Re-Tuning Event Signal Enable"]
74pub type RETUNINGEVTSEN_R = crate::BitReader<bool>;
75#[doc = "Field `RETUNINGEVTSEN` writer - Re-Tuning Event Signal Enable"]
76pub type RETUNINGEVTSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 12>;
77#[doc = "Field `BOOTACKRCVSEN` reader - Boot Ack Received Signal Enable"]
78pub type BOOTACKRCVSEN_R = crate::BitReader<bool>;
79#[doc = "Field `BOOTACKRCVSEN` writer - Boot Ack Received Signal Enable"]
80pub type BOOTACKRCVSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 13>;
81#[doc = "Field `BOOTTERMINATESEN` reader - Boot Terminate Interrupt Signal Enable"]
82pub type BOOTTERMINATESEN_R = crate::BitReader<bool>;
83#[doc = "Field `BOOTTERMINATESEN` writer - Boot Terminate Interrupt Signal Enable"]
84pub type BOOTTERMINATESEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 14>;
85#[doc = "Field `CMDTOUTERRSEN` reader - Command Timeout Error Signal Enable"]
86pub type CMDTOUTERRSEN_R = crate::BitReader<bool>;
87#[doc = "Field `CMDTOUTERRSEN` writer - Command Timeout Error Signal Enable"]
88pub type CMDTOUTERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 16>;
89#[doc = "Field `CMDCRCERRSEN` reader - Command CRC Error Signal Enable"]
90pub type CMDCRCERRSEN_R = crate::BitReader<bool>;
91#[doc = "Field `CMDCRCERRSEN` writer - Command CRC Error Signal Enable"]
92pub type CMDCRCERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 17>;
93#[doc = "Field `CMDENDBITERRSEN` reader - Command End Bit Error Signal Enable"]
94pub type CMDENDBITERRSEN_R = crate::BitReader<bool>;
95#[doc = "Field `CMDENDBITERRSEN` writer - Command End Bit Error Signal Enable"]
96pub type CMDENDBITERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 18>;
97#[doc = "Field `CMDINDEXERRSEN` reader - Command Index Error Signal Enable"]
98pub type CMDINDEXERRSEN_R = crate::BitReader<bool>;
99#[doc = "Field `CMDINDEXERRSEN` writer - Command Index Error Signal Enable"]
100pub type CMDINDEXERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 19>;
101#[doc = "Field `DATTOUTERRSEN` reader - Data Timeout Error Signal Enable"]
102pub type DATTOUTERRSEN_R = crate::BitReader<bool>;
103#[doc = "Field `DATTOUTERRSEN` writer - Data Timeout Error Signal Enable"]
104pub type DATTOUTERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 20>;
105#[doc = "Field `DATCRCERRSEN` reader - Data CRC Error Signal Enable"]
106pub type DATCRCERRSEN_R = crate::BitReader<bool>;
107#[doc = "Field `DATCRCERRSEN` writer - Data CRC Error Signal Enable"]
108pub type DATCRCERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 21>;
109#[doc = "Field `DATENDBITERRSEN` reader - Data End Bit Error Signal Enable"]
110pub type DATENDBITERRSEN_R = crate::BitReader<bool>;
111#[doc = "Field `DATENDBITERRSEN` writer - Data End Bit Error Signal Enable"]
112pub type DATENDBITERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 22>;
113#[doc = "Field `CURRENTLIMITERRSEN` reader - Current Limit Error Signal Enable"]
114pub type CURRENTLIMITERRSEN_R = crate::BitReader<bool>;
115#[doc = "Field `CURRENTLIMITERRSEN` writer - Current Limit Error Signal Enable"]
116pub type CURRENTLIMITERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 23>;
117#[doc = "Field `AUTOCMDERRSEN` reader - Auto CMD12 Error Signal Enable"]
118pub type AUTOCMDERRSEN_R = crate::BitReader<bool>;
119#[doc = "Field `AUTOCMDERRSEN` writer - Auto CMD12 Error Signal Enable"]
120pub type AUTOCMDERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 24>;
121#[doc = "Field `ADMAERRSEN` reader - ADMA Error Signal Enable"]
122pub type ADMAERRSEN_R = crate::BitReader<bool>;
123#[doc = "Field `ADMAERRSEN` writer - ADMA Error Signal Enable"]
124pub type ADMAERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 25>;
125#[doc = "Field `TUNINGERRSIGNALENABLE` reader - Tuning Error Signal Enable"]
126pub type TUNINGERRSIGNALENABLE_R = crate::BitReader<bool>;
127#[doc = "Field `TUNINGERRSIGNALENABLE` writer - Tuning Error Signal Enable"]
128pub type TUNINGERRSIGNALENABLE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 26>;
129#[doc = "Field `TARGETRESPERRSEN` reader - Target Response Error Signal Enable"]
130pub type TARGETRESPERRSEN_R = crate::BitReader<bool>;
131#[doc = "Field `TARGETRESPERRSEN` writer - Target Response Error Signal Enable"]
132pub type TARGETRESPERRSEN_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 28>;
133impl R {
134 #[doc = "Bit 0 - Command Complete Signal Enable"]
135 #[inline(always)]
136 pub fn cmdcomsen(&self) -> CMDCOMSEN_R {
137 CMDCOMSEN_R::new((self.bits & 1) != 0)
138 }
139 #[doc = "Bit 1 - Transfer Complete Signal Enable"]
140 #[inline(always)]
141 pub fn trancomsen(&self) -> TRANCOMSEN_R {
142 TRANCOMSEN_R::new(((self.bits >> 1) & 1) != 0)
143 }
144 #[doc = "Bit 2 - Block Gap Event Signal Enable"]
145 #[inline(always)]
146 pub fn blkgapevtsen(&self) -> BLKGAPEVTSEN_R {
147 BLKGAPEVTSEN_R::new(((self.bits >> 2) & 1) != 0)
148 }
149 #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
150 #[inline(always)]
151 pub fn dmaintsen(&self) -> DMAINTSEN_R {
152 DMAINTSEN_R::new(((self.bits >> 3) & 1) != 0)
153 }
154 #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
155 #[inline(always)]
156 pub fn bufwrrdysen(&self) -> BUFWRRDYSEN_R {
157 BUFWRRDYSEN_R::new(((self.bits >> 4) & 1) != 0)
158 }
159 #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
160 #[inline(always)]
161 pub fn bufrdrdysen(&self) -> BUFRDRDYSEN_R {
162 BUFRDRDYSEN_R::new(((self.bits >> 5) & 1) != 0)
163 }
164 #[doc = "Bit 6 - Card Insertion Signal Enable"]
165 #[inline(always)]
166 pub fn cardinssen(&self) -> CARDINSSEN_R {
167 CARDINSSEN_R::new(((self.bits >> 6) & 1) != 0)
168 }
169 #[doc = "Bit 7 - Card Removal Signal Enable"]
170 #[inline(always)]
171 pub fn cardremsen(&self) -> CARDREMSEN_R {
172 CARDREMSEN_R::new(((self.bits >> 7) & 1) != 0)
173 }
174 #[doc = "Bit 8 - Card Interrupt Signal Enable"]
175 #[inline(always)]
176 pub fn cardintsen(&self) -> CARDINTSEN_R {
177 CARDINTSEN_R::new(((self.bits >> 8) & 1) != 0)
178 }
179 #[doc = "Bit 12 - Re-Tuning Event Signal Enable"]
180 #[inline(always)]
181 pub fn retuningevtsen(&self) -> RETUNINGEVTSEN_R {
182 RETUNINGEVTSEN_R::new(((self.bits >> 12) & 1) != 0)
183 }
184 #[doc = "Bit 13 - Boot Ack Received Signal Enable"]
185 #[inline(always)]
186 pub fn bootackrcvsen(&self) -> BOOTACKRCVSEN_R {
187 BOOTACKRCVSEN_R::new(((self.bits >> 13) & 1) != 0)
188 }
189 #[doc = "Bit 14 - Boot Terminate Interrupt Signal Enable"]
190 #[inline(always)]
191 pub fn bootterminatesen(&self) -> BOOTTERMINATESEN_R {
192 BOOTTERMINATESEN_R::new(((self.bits >> 14) & 1) != 0)
193 }
194 #[doc = "Bit 16 - Command Timeout Error Signal Enable"]
195 #[inline(always)]
196 pub fn cmdtouterrsen(&self) -> CMDTOUTERRSEN_R {
197 CMDTOUTERRSEN_R::new(((self.bits >> 16) & 1) != 0)
198 }
199 #[doc = "Bit 17 - Command CRC Error Signal Enable"]
200 #[inline(always)]
201 pub fn cmdcrcerrsen(&self) -> CMDCRCERRSEN_R {
202 CMDCRCERRSEN_R::new(((self.bits >> 17) & 1) != 0)
203 }
204 #[doc = "Bit 18 - Command End Bit Error Signal Enable"]
205 #[inline(always)]
206 pub fn cmdendbiterrsen(&self) -> CMDENDBITERRSEN_R {
207 CMDENDBITERRSEN_R::new(((self.bits >> 18) & 1) != 0)
208 }
209 #[doc = "Bit 19 - Command Index Error Signal Enable"]
210 #[inline(always)]
211 pub fn cmdindexerrsen(&self) -> CMDINDEXERRSEN_R {
212 CMDINDEXERRSEN_R::new(((self.bits >> 19) & 1) != 0)
213 }
214 #[doc = "Bit 20 - Data Timeout Error Signal Enable"]
215 #[inline(always)]
216 pub fn dattouterrsen(&self) -> DATTOUTERRSEN_R {
217 DATTOUTERRSEN_R::new(((self.bits >> 20) & 1) != 0)
218 }
219 #[doc = "Bit 21 - Data CRC Error Signal Enable"]
220 #[inline(always)]
221 pub fn datcrcerrsen(&self) -> DATCRCERRSEN_R {
222 DATCRCERRSEN_R::new(((self.bits >> 21) & 1) != 0)
223 }
224 #[doc = "Bit 22 - Data End Bit Error Signal Enable"]
225 #[inline(always)]
226 pub fn datendbiterrsen(&self) -> DATENDBITERRSEN_R {
227 DATENDBITERRSEN_R::new(((self.bits >> 22) & 1) != 0)
228 }
229 #[doc = "Bit 23 - Current Limit Error Signal Enable"]
230 #[inline(always)]
231 pub fn currentlimiterrsen(&self) -> CURRENTLIMITERRSEN_R {
232 CURRENTLIMITERRSEN_R::new(((self.bits >> 23) & 1) != 0)
233 }
234 #[doc = "Bit 24 - Auto CMD12 Error Signal Enable"]
235 #[inline(always)]
236 pub fn autocmderrsen(&self) -> AUTOCMDERRSEN_R {
237 AUTOCMDERRSEN_R::new(((self.bits >> 24) & 1) != 0)
238 }
239 #[doc = "Bit 25 - ADMA Error Signal Enable"]
240 #[inline(always)]
241 pub fn admaerrsen(&self) -> ADMAERRSEN_R {
242 ADMAERRSEN_R::new(((self.bits >> 25) & 1) != 0)
243 }
244 #[doc = "Bit 26 - Tuning Error Signal Enable"]
245 #[inline(always)]
246 pub fn tuningerrsignalenable(&self) -> TUNINGERRSIGNALENABLE_R {
247 TUNINGERRSIGNALENABLE_R::new(((self.bits >> 26) & 1) != 0)
248 }
249 #[doc = "Bit 28 - Target Response Error Signal Enable"]
250 #[inline(always)]
251 pub fn targetresperrsen(&self) -> TARGETRESPERRSEN_R {
252 TARGETRESPERRSEN_R::new(((self.bits >> 28) & 1) != 0)
253 }
254}
255impl W {
256 #[doc = "Bit 0 - Command Complete Signal Enable"]
257 #[inline(always)]
258 pub fn cmdcomsen(&mut self) -> CMDCOMSEN_W {
259 CMDCOMSEN_W::new(self)
260 }
261 #[doc = "Bit 1 - Transfer Complete Signal Enable"]
262 #[inline(always)]
263 pub fn trancomsen(&mut self) -> TRANCOMSEN_W {
264 TRANCOMSEN_W::new(self)
265 }
266 #[doc = "Bit 2 - Block Gap Event Signal Enable"]
267 #[inline(always)]
268 pub fn blkgapevtsen(&mut self) -> BLKGAPEVTSEN_W {
269 BLKGAPEVTSEN_W::new(self)
270 }
271 #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
272 #[inline(always)]
273 pub fn dmaintsen(&mut self) -> DMAINTSEN_W {
274 DMAINTSEN_W::new(self)
275 }
276 #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
277 #[inline(always)]
278 pub fn bufwrrdysen(&mut self) -> BUFWRRDYSEN_W {
279 BUFWRRDYSEN_W::new(self)
280 }
281 #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
282 #[inline(always)]
283 pub fn bufrdrdysen(&mut self) -> BUFRDRDYSEN_W {
284 BUFRDRDYSEN_W::new(self)
285 }
286 #[doc = "Bit 6 - Card Insertion Signal Enable"]
287 #[inline(always)]
288 pub fn cardinssen(&mut self) -> CARDINSSEN_W {
289 CARDINSSEN_W::new(self)
290 }
291 #[doc = "Bit 7 - Card Removal Signal Enable"]
292 #[inline(always)]
293 pub fn cardremsen(&mut self) -> CARDREMSEN_W {
294 CARDREMSEN_W::new(self)
295 }
296 #[doc = "Bit 8 - Card Interrupt Signal Enable"]
297 #[inline(always)]
298 pub fn cardintsen(&mut self) -> CARDINTSEN_W {
299 CARDINTSEN_W::new(self)
300 }
301 #[doc = "Bit 12 - Re-Tuning Event Signal Enable"]
302 #[inline(always)]
303 pub fn retuningevtsen(&mut self) -> RETUNINGEVTSEN_W {
304 RETUNINGEVTSEN_W::new(self)
305 }
306 #[doc = "Bit 13 - Boot Ack Received Signal Enable"]
307 #[inline(always)]
308 pub fn bootackrcvsen(&mut self) -> BOOTACKRCVSEN_W {
309 BOOTACKRCVSEN_W::new(self)
310 }
311 #[doc = "Bit 14 - Boot Terminate Interrupt Signal Enable"]
312 #[inline(always)]
313 pub fn bootterminatesen(&mut self) -> BOOTTERMINATESEN_W {
314 BOOTTERMINATESEN_W::new(self)
315 }
316 #[doc = "Bit 16 - Command Timeout Error Signal Enable"]
317 #[inline(always)]
318 pub fn cmdtouterrsen(&mut self) -> CMDTOUTERRSEN_W {
319 CMDTOUTERRSEN_W::new(self)
320 }
321 #[doc = "Bit 17 - Command CRC Error Signal Enable"]
322 #[inline(always)]
323 pub fn cmdcrcerrsen(&mut self) -> CMDCRCERRSEN_W {
324 CMDCRCERRSEN_W::new(self)
325 }
326 #[doc = "Bit 18 - Command End Bit Error Signal Enable"]
327 #[inline(always)]
328 pub fn cmdendbiterrsen(&mut self) -> CMDENDBITERRSEN_W {
329 CMDENDBITERRSEN_W::new(self)
330 }
331 #[doc = "Bit 19 - Command Index Error Signal Enable"]
332 #[inline(always)]
333 pub fn cmdindexerrsen(&mut self) -> CMDINDEXERRSEN_W {
334 CMDINDEXERRSEN_W::new(self)
335 }
336 #[doc = "Bit 20 - Data Timeout Error Signal Enable"]
337 #[inline(always)]
338 pub fn dattouterrsen(&mut self) -> DATTOUTERRSEN_W {
339 DATTOUTERRSEN_W::new(self)
340 }
341 #[doc = "Bit 21 - Data CRC Error Signal Enable"]
342 #[inline(always)]
343 pub fn datcrcerrsen(&mut self) -> DATCRCERRSEN_W {
344 DATCRCERRSEN_W::new(self)
345 }
346 #[doc = "Bit 22 - Data End Bit Error Signal Enable"]
347 #[inline(always)]
348 pub fn datendbiterrsen(&mut self) -> DATENDBITERRSEN_W {
349 DATENDBITERRSEN_W::new(self)
350 }
351 #[doc = "Bit 23 - Current Limit Error Signal Enable"]
352 #[inline(always)]
353 pub fn currentlimiterrsen(&mut self) -> CURRENTLIMITERRSEN_W {
354 CURRENTLIMITERRSEN_W::new(self)
355 }
356 #[doc = "Bit 24 - Auto CMD12 Error Signal Enable"]
357 #[inline(always)]
358 pub fn autocmderrsen(&mut self) -> AUTOCMDERRSEN_W {
359 AUTOCMDERRSEN_W::new(self)
360 }
361 #[doc = "Bit 25 - ADMA Error Signal Enable"]
362 #[inline(always)]
363 pub fn admaerrsen(&mut self) -> ADMAERRSEN_W {
364 ADMAERRSEN_W::new(self)
365 }
366 #[doc = "Bit 26 - Tuning Error Signal Enable"]
367 #[inline(always)]
368 pub fn tuningerrsignalenable(&mut self) -> TUNINGERRSIGNALENABLE_W {
369 TUNINGERRSIGNALENABLE_W::new(self)
370 }
371 #[doc = "Bit 28 - Target Response Error Signal Enable"]
372 #[inline(always)]
373 pub fn targetresperrsen(&mut self) -> TARGETRESPERRSEN_W {
374 TARGETRESPERRSEN_W::new(self)
375 }
376 #[doc = "Writes raw bits to the register."]
377 #[inline(always)]
378 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
379 self.0.bits(bits);
380 self
381 }
382}
383#[doc = "Normal and Error Interrupt Signal Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
384pub struct IEN_SPEC;
385impl crate::RegisterSpec for IEN_SPEC {
386 type Ux = u32;
387}
388#[doc = "`read()` method returns [ien::R](R) reader structure"]
389impl crate::Readable for IEN_SPEC {
390 type Reader = R;
391}
392#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
393impl crate::Writable for IEN_SPEC {
394 type Writer = W;
395}
396#[doc = "`reset()` method sets IEN to value 0"]
397impl crate::Resettable for IEN_SPEC {
398 #[inline(always)]
399 fn reset_value() -> Self::Ux {
400 0
401 }
402}