efm32gg12b830_pac/qspi0/
phyconfiguration.rs

1#[doc = "Register `PHYCONFIGURATION` reader"]
2pub struct R(crate::R<PHYCONFIGURATION_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PHYCONFIGURATION_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PHYCONFIGURATION_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PHYCONFIGURATION_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PHYCONFIGURATION` writer"]
17pub struct W(crate::W<PHYCONFIGURATION_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PHYCONFIGURATION_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PHYCONFIGURATION_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PHYCONFIGURATION_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PHYCONFIGRXDLLDELAY` reader - RX DLL Delay"]
38pub type PHYCONFIGRXDLLDELAY_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `PHYCONFIGRXDLLDELAY` writer - RX DLL Delay"]
40pub type PHYCONFIGRXDLLDELAY_W<'a> =
41    crate::FieldWriter<'a, u32, PHYCONFIGURATION_SPEC, u8, u8, 7, 0>;
42#[doc = "Field `PHYCONFIGTXDLLDELAY` reader - TX DLL Delay"]
43pub type PHYCONFIGTXDLLDELAY_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `PHYCONFIGTXDLLDELAY` writer - TX DLL Delay"]
45pub type PHYCONFIGTXDLLDELAY_W<'a> =
46    crate::FieldWriter<'a, u32, PHYCONFIGURATION_SPEC, u8, u8, 7, 16>;
47#[doc = "Field `PHYCONFIGRESYNC` writer - PHY Config Resync"]
48pub type PHYCONFIGRESYNC_W<'a> = crate::BitWriter<'a, u32, PHYCONFIGURATION_SPEC, bool, 31>;
49impl R {
50    #[doc = "Bits 0:6 - RX DLL Delay"]
51    #[inline(always)]
52    pub fn phyconfigrxdlldelay(&self) -> PHYCONFIGRXDLLDELAY_R {
53        PHYCONFIGRXDLLDELAY_R::new((self.bits & 0x7f) as u8)
54    }
55    #[doc = "Bits 16:22 - TX DLL Delay"]
56    #[inline(always)]
57    pub fn phyconfigtxdlldelay(&self) -> PHYCONFIGTXDLLDELAY_R {
58        PHYCONFIGTXDLLDELAY_R::new(((self.bits >> 16) & 0x7f) as u8)
59    }
60}
61impl W {
62    #[doc = "Bits 0:6 - RX DLL Delay"]
63    #[inline(always)]
64    pub fn phyconfigrxdlldelay(&mut self) -> PHYCONFIGRXDLLDELAY_W {
65        PHYCONFIGRXDLLDELAY_W::new(self)
66    }
67    #[doc = "Bits 16:22 - TX DLL Delay"]
68    #[inline(always)]
69    pub fn phyconfigtxdlldelay(&mut self) -> PHYCONFIGTXDLLDELAY_W {
70        PHYCONFIGTXDLLDELAY_W::new(self)
71    }
72    #[doc = "Bit 31 - PHY Config Resync"]
73    #[inline(always)]
74    pub fn phyconfigresync(&mut self) -> PHYCONFIGRESYNC_W {
75        PHYCONFIGRESYNC_W::new(self)
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "PHY Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [phyconfiguration](index.html) module"]
85pub struct PHYCONFIGURATION_SPEC;
86impl crate::RegisterSpec for PHYCONFIGURATION_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [phyconfiguration::R](R) reader structure"]
90impl crate::Readable for PHYCONFIGURATION_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [phyconfiguration::W](W) writer structure"]
94impl crate::Writable for PHYCONFIGURATION_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets PHYCONFIGURATION to value 0"]
98impl crate::Resettable for PHYCONFIGURATION_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
efm32gg12b830_pac/qspi0/phyconfiguration.rs

efm32gg12b830_pac/qspi0/
phyconfiguration.rs
