efm32gg12b830_pac/qspi0/
irqmask.rs

1#[doc = "Register `IRQMASK` reader"]
2pub struct R(crate::R<IRQMASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IRQMASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IRQMASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IRQMASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IRQMASK` writer"]
17pub struct W(crate::W<IRQMASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IRQMASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IRQMASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IRQMASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODEMFAILMASK` reader - Mode M Failure Mask"]
38pub type MODEMFAILMASK_R = crate::BitReader<bool>;
39#[doc = "Field `MODEMFAILMASK` writer - Mode M Failure Mask"]
40pub type MODEMFAILMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 0>;
41#[doc = "Field `UNDERFLOWDETMASK` reader - Underflow Detected Mask"]
42pub type UNDERFLOWDETMASK_R = crate::BitReader<bool>;
43#[doc = "Field `UNDERFLOWDETMASK` writer - Underflow Detected Mask"]
44pub type UNDERFLOWDETMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 1>;
45#[doc = "Field `INDIRECTOPDONEMASK` reader - Indirect Complete Mask"]
46pub type INDIRECTOPDONEMASK_R = crate::BitReader<bool>;
47#[doc = "Field `INDIRECTOPDONEMASK` writer - Indirect Complete Mask"]
48pub type INDIRECTOPDONEMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 2>;
49#[doc = "Field `INDIRECTREADREJECTMASK` reader - Indirect Read Reject Mask"]
50pub type INDIRECTREADREJECTMASK_R = crate::BitReader<bool>;
51#[doc = "Field `INDIRECTREADREJECTMASK` writer - Indirect Read Reject Mask"]
52pub type INDIRECTREADREJECTMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 3>;
53#[doc = "Field `PROTWRATTEMPTMASK` reader - Protected Area Write Attempt Mask"]
54pub type PROTWRATTEMPTMASK_R = crate::BitReader<bool>;
55#[doc = "Field `PROTWRATTEMPTMASK` writer - Protected Area Write Attempt Mask"]
56pub type PROTWRATTEMPTMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 4>;
57#[doc = "Field `ILLEGALACCESSDETMASK` reader - Illegal Access Detected Mask"]
58pub type ILLEGALACCESSDETMASK_R = crate::BitReader<bool>;
59#[doc = "Field `ILLEGALACCESSDETMASK` writer - Illegal Access Detected Mask"]
60pub type ILLEGALACCESSDETMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 5>;
61#[doc = "Field `INDIRECTXFERLEVELBREACHMASK` reader - Transfer Watermark Breach Mask"]
62pub type INDIRECTXFERLEVELBREACHMASK_R = crate::BitReader<bool>;
63#[doc = "Field `INDIRECTXFERLEVELBREACHMASK` writer - Transfer Watermark Breach Mask"]
64pub type INDIRECTXFERLEVELBREACHMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 6>;
65#[doc = "Field `RECVOVERFLOWMASK` reader - Receive Overflow Mask"]
66pub type RECVOVERFLOWMASK_R = crate::BitReader<bool>;
67#[doc = "Field `RECVOVERFLOWMASK` writer - Receive Overflow Mask"]
68pub type RECVOVERFLOWMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 7>;
69#[doc = "Field `TXFIFONOTFULLMASK` reader - Small TX FIFO Not Full Mask"]
70pub type TXFIFONOTFULLMASK_R = crate::BitReader<bool>;
71#[doc = "Field `TXFIFONOTFULLMASK` writer - Small TX FIFO Not Full Mask"]
72pub type TXFIFONOTFULLMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 8>;
73#[doc = "Field `TXFIFOFULLMASK` reader - Small TX FIFO Full Mask"]
74pub type TXFIFOFULLMASK_R = crate::BitReader<bool>;
75#[doc = "Field `TXFIFOFULLMASK` writer - Small TX FIFO Full Mask"]
76pub type TXFIFOFULLMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 9>;
77#[doc = "Field `RXFIFONOTEMPTYMASK` reader - Small RX FIFO Not Empty Mask"]
78pub type RXFIFONOTEMPTYMASK_R = crate::BitReader<bool>;
79#[doc = "Field `RXFIFONOTEMPTYMASK` writer - Small RX FIFO Not Empty Mask"]
80pub type RXFIFONOTEMPTYMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 10>;
81#[doc = "Field `RXFIFOFULLMASK` reader - Small RX FIFO Full Mask"]
82pub type RXFIFOFULLMASK_R = crate::BitReader<bool>;
83#[doc = "Field `RXFIFOFULLMASK` writer - Small RX FIFO Full Mask"]
84pub type RXFIFOFULLMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 11>;
85#[doc = "Field `INDRDSRAMFULLMASK` reader - Indirect Read Partition Overflow Mask"]
86pub type INDRDSRAMFULLMASK_R = crate::BitReader<bool>;
87#[doc = "Field `INDRDSRAMFULLMASK` writer - Indirect Read Partition Overflow Mask"]
88pub type INDRDSRAMFULLMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 12>;
89#[doc = "Field `POLLEXPINTMASK` reader - Polling Expiration Detected Mask"]
90pub type POLLEXPINTMASK_R = crate::BitReader<bool>;
91#[doc = "Field `POLLEXPINTMASK` writer - Polling Expiration Detected Mask"]
92pub type POLLEXPINTMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 13>;
93#[doc = "Field `STIGREQMASK` reader - STIG Request Completion Mask"]
94pub type STIGREQMASK_R = crate::BitReader<bool>;
95#[doc = "Field `STIGREQMASK` writer - STIG Request Completion Mask"]
96pub type STIGREQMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 14>;
97#[doc = "Field `RXCRCDATAERRMASK` reader - RX CRC Data Error Mask"]
98pub type RXCRCDATAERRMASK_R = crate::BitReader<bool>;
99#[doc = "Field `RXCRCDATAERRMASK` writer - RX CRC Data Error Mask"]
100pub type RXCRCDATAERRMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 16>;
101#[doc = "Field `RXCRCDATAVALMASK` reader - RX CRC Data Valid Mask"]
102pub type RXCRCDATAVALMASK_R = crate::BitReader<bool>;
103#[doc = "Field `RXCRCDATAVALMASK` writer - RX CRC Data Valid Mask"]
104pub type RXCRCDATAVALMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 17>;
105#[doc = "Field `TXCRCCHUNKBRKMASK` reader - TX CRC Chunk Was Broken Mask"]
106pub type TXCRCCHUNKBRKMASK_R = crate::BitReader<bool>;
107#[doc = "Field `TXCRCCHUNKBRKMASK` writer - TX CRC Chunk Was Broken Mask"]
108pub type TXCRCCHUNKBRKMASK_W<'a> = crate::BitWriter<'a, u32, IRQMASK_SPEC, bool, 18>;
109impl R {
110    #[doc = "Bit 0 - Mode M Failure Mask"]
111    #[inline(always)]
112    pub fn modemfailmask(&self) -> MODEMFAILMASK_R {
113        MODEMFAILMASK_R::new((self.bits & 1) != 0)
114    }
115    #[doc = "Bit 1 - Underflow Detected Mask"]
116    #[inline(always)]
117    pub fn underflowdetmask(&self) -> UNDERFLOWDETMASK_R {
118        UNDERFLOWDETMASK_R::new(((self.bits >> 1) & 1) != 0)
119    }
120    #[doc = "Bit 2 - Indirect Complete Mask"]
121    #[inline(always)]
122    pub fn indirectopdonemask(&self) -> INDIRECTOPDONEMASK_R {
123        INDIRECTOPDONEMASK_R::new(((self.bits >> 2) & 1) != 0)
124    }
125    #[doc = "Bit 3 - Indirect Read Reject Mask"]
126    #[inline(always)]
127    pub fn indirectreadrejectmask(&self) -> INDIRECTREADREJECTMASK_R {
128        INDIRECTREADREJECTMASK_R::new(((self.bits >> 3) & 1) != 0)
129    }
130    #[doc = "Bit 4 - Protected Area Write Attempt Mask"]
131    #[inline(always)]
132    pub fn protwrattemptmask(&self) -> PROTWRATTEMPTMASK_R {
133        PROTWRATTEMPTMASK_R::new(((self.bits >> 4) & 1) != 0)
134    }
135    #[doc = "Bit 5 - Illegal Access Detected Mask"]
136    #[inline(always)]
137    pub fn illegalaccessdetmask(&self) -> ILLEGALACCESSDETMASK_R {
138        ILLEGALACCESSDETMASK_R::new(((self.bits >> 5) & 1) != 0)
139    }
140    #[doc = "Bit 6 - Transfer Watermark Breach Mask"]
141    #[inline(always)]
142    pub fn indirectxferlevelbreachmask(&self) -> INDIRECTXFERLEVELBREACHMASK_R {
143        INDIRECTXFERLEVELBREACHMASK_R::new(((self.bits >> 6) & 1) != 0)
144    }
145    #[doc = "Bit 7 - Receive Overflow Mask"]
146    #[inline(always)]
147    pub fn recvoverflowmask(&self) -> RECVOVERFLOWMASK_R {
148        RECVOVERFLOWMASK_R::new(((self.bits >> 7) & 1) != 0)
149    }
150    #[doc = "Bit 8 - Small TX FIFO Not Full Mask"]
151    #[inline(always)]
152    pub fn txfifonotfullmask(&self) -> TXFIFONOTFULLMASK_R {
153        TXFIFONOTFULLMASK_R::new(((self.bits >> 8) & 1) != 0)
154    }
155    #[doc = "Bit 9 - Small TX FIFO Full Mask"]
156    #[inline(always)]
157    pub fn txfifofullmask(&self) -> TXFIFOFULLMASK_R {
158        TXFIFOFULLMASK_R::new(((self.bits >> 9) & 1) != 0)
159    }
160    #[doc = "Bit 10 - Small RX FIFO Not Empty Mask"]
161    #[inline(always)]
162    pub fn rxfifonotemptymask(&self) -> RXFIFONOTEMPTYMASK_R {
163        RXFIFONOTEMPTYMASK_R::new(((self.bits >> 10) & 1) != 0)
164    }
165    #[doc = "Bit 11 - Small RX FIFO Full Mask"]
166    #[inline(always)]
167    pub fn rxfifofullmask(&self) -> RXFIFOFULLMASK_R {
168        RXFIFOFULLMASK_R::new(((self.bits >> 11) & 1) != 0)
169    }
170    #[doc = "Bit 12 - Indirect Read Partition Overflow Mask"]
171    #[inline(always)]
172    pub fn indrdsramfullmask(&self) -> INDRDSRAMFULLMASK_R {
173        INDRDSRAMFULLMASK_R::new(((self.bits >> 12) & 1) != 0)
174    }
175    #[doc = "Bit 13 - Polling Expiration Detected Mask"]
176    #[inline(always)]
177    pub fn pollexpintmask(&self) -> POLLEXPINTMASK_R {
178        POLLEXPINTMASK_R::new(((self.bits >> 13) & 1) != 0)
179    }
180    #[doc = "Bit 14 - STIG Request Completion Mask"]
181    #[inline(always)]
182    pub fn stigreqmask(&self) -> STIGREQMASK_R {
183        STIGREQMASK_R::new(((self.bits >> 14) & 1) != 0)
184    }
185    #[doc = "Bit 16 - RX CRC Data Error Mask"]
186    #[inline(always)]
187    pub fn rxcrcdataerrmask(&self) -> RXCRCDATAERRMASK_R {
188        RXCRCDATAERRMASK_R::new(((self.bits >> 16) & 1) != 0)
189    }
190    #[doc = "Bit 17 - RX CRC Data Valid Mask"]
191    #[inline(always)]
192    pub fn rxcrcdatavalmask(&self) -> RXCRCDATAVALMASK_R {
193        RXCRCDATAVALMASK_R::new(((self.bits >> 17) & 1) != 0)
194    }
195    #[doc = "Bit 18 - TX CRC Chunk Was Broken Mask"]
196    #[inline(always)]
197    pub fn txcrcchunkbrkmask(&self) -> TXCRCCHUNKBRKMASK_R {
198        TXCRCCHUNKBRKMASK_R::new(((self.bits >> 18) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bit 0 - Mode M Failure Mask"]
203    #[inline(always)]
204    pub fn modemfailmask(&mut self) -> MODEMFAILMASK_W {
205        MODEMFAILMASK_W::new(self)
206    }
207    #[doc = "Bit 1 - Underflow Detected Mask"]
208    #[inline(always)]
209    pub fn underflowdetmask(&mut self) -> UNDERFLOWDETMASK_W {
210        UNDERFLOWDETMASK_W::new(self)
211    }
212    #[doc = "Bit 2 - Indirect Complete Mask"]
213    #[inline(always)]
214    pub fn indirectopdonemask(&mut self) -> INDIRECTOPDONEMASK_W {
215        INDIRECTOPDONEMASK_W::new(self)
216    }
217    #[doc = "Bit 3 - Indirect Read Reject Mask"]
218    #[inline(always)]
219    pub fn indirectreadrejectmask(&mut self) -> INDIRECTREADREJECTMASK_W {
220        INDIRECTREADREJECTMASK_W::new(self)
221    }
222    #[doc = "Bit 4 - Protected Area Write Attempt Mask"]
223    #[inline(always)]
224    pub fn protwrattemptmask(&mut self) -> PROTWRATTEMPTMASK_W {
225        PROTWRATTEMPTMASK_W::new(self)
226    }
227    #[doc = "Bit 5 - Illegal Access Detected Mask"]
228    #[inline(always)]
229    pub fn illegalaccessdetmask(&mut self) -> ILLEGALACCESSDETMASK_W {
230        ILLEGALACCESSDETMASK_W::new(self)
231    }
232    #[doc = "Bit 6 - Transfer Watermark Breach Mask"]
233    #[inline(always)]
234    pub fn indirectxferlevelbreachmask(&mut self) -> INDIRECTXFERLEVELBREACHMASK_W {
235        INDIRECTXFERLEVELBREACHMASK_W::new(self)
236    }
237    #[doc = "Bit 7 - Receive Overflow Mask"]
238    #[inline(always)]
239    pub fn recvoverflowmask(&mut self) -> RECVOVERFLOWMASK_W {
240        RECVOVERFLOWMASK_W::new(self)
241    }
242    #[doc = "Bit 8 - Small TX FIFO Not Full Mask"]
243    #[inline(always)]
244    pub fn txfifonotfullmask(&mut self) -> TXFIFONOTFULLMASK_W {
245        TXFIFONOTFULLMASK_W::new(self)
246    }
247    #[doc = "Bit 9 - Small TX FIFO Full Mask"]
248    #[inline(always)]
249    pub fn txfifofullmask(&mut self) -> TXFIFOFULLMASK_W {
250        TXFIFOFULLMASK_W::new(self)
251    }
252    #[doc = "Bit 10 - Small RX FIFO Not Empty Mask"]
253    #[inline(always)]
254    pub fn rxfifonotemptymask(&mut self) -> RXFIFONOTEMPTYMASK_W {
255        RXFIFONOTEMPTYMASK_W::new(self)
256    }
257    #[doc = "Bit 11 - Small RX FIFO Full Mask"]
258    #[inline(always)]
259    pub fn rxfifofullmask(&mut self) -> RXFIFOFULLMASK_W {
260        RXFIFOFULLMASK_W::new(self)
261    }
262    #[doc = "Bit 12 - Indirect Read Partition Overflow Mask"]
263    #[inline(always)]
264    pub fn indrdsramfullmask(&mut self) -> INDRDSRAMFULLMASK_W {
265        INDRDSRAMFULLMASK_W::new(self)
266    }
267    #[doc = "Bit 13 - Polling Expiration Detected Mask"]
268    #[inline(always)]
269    pub fn pollexpintmask(&mut self) -> POLLEXPINTMASK_W {
270        POLLEXPINTMASK_W::new(self)
271    }
272    #[doc = "Bit 14 - STIG Request Completion Mask"]
273    #[inline(always)]
274    pub fn stigreqmask(&mut self) -> STIGREQMASK_W {
275        STIGREQMASK_W::new(self)
276    }
277    #[doc = "Bit 16 - RX CRC Data Error Mask"]
278    #[inline(always)]
279    pub fn rxcrcdataerrmask(&mut self) -> RXCRCDATAERRMASK_W {
280        RXCRCDATAERRMASK_W::new(self)
281    }
282    #[doc = "Bit 17 - RX CRC Data Valid Mask"]
283    #[inline(always)]
284    pub fn rxcrcdatavalmask(&mut self) -> RXCRCDATAVALMASK_W {
285        RXCRCDATAVALMASK_W::new(self)
286    }
287    #[doc = "Bit 18 - TX CRC Chunk Was Broken Mask"]
288    #[inline(always)]
289    pub fn txcrcchunkbrkmask(&mut self) -> TXCRCCHUNKBRKMASK_W {
290        TXCRCCHUNKBRKMASK_W::new(self)
291    }
292    #[doc = "Writes raw bits to the register."]
293    #[inline(always)]
294    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
295        self.0.bits(bits);
296        self
297    }
298}
299#[doc = "Interrupt Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqmask](index.html) module"]
300pub struct IRQMASK_SPEC;
301impl crate::RegisterSpec for IRQMASK_SPEC {
302    type Ux = u32;
303}
304#[doc = "`read()` method returns [irqmask::R](R) reader structure"]
305impl crate::Readable for IRQMASK_SPEC {
306    type Reader = R;
307}
308#[doc = "`write(|w| ..)` method takes [irqmask::W](W) writer structure"]
309impl crate::Writable for IRQMASK_SPEC {
310    type Writer = W;
311}
312#[doc = "`reset()` method sets IRQMASK to value 0"]
313impl crate::Resettable for IRQMASK_SPEC {
314    #[inline(always)]
315    fn reset_value() -> Self::Ux {
316        0
317    }
318}
efm32gg12b830_pac/qspi0/irqmask.rs

efm32gg12b830_pac/qspi0/
irqmask.rs
