efm32gg12b830_pac/cmu/
pdmctrl.rs

1#[doc = "Register `PDMCTRL` reader"]
2pub struct R(crate::R<PDMCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDMCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDMCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDMCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDMCTRL` writer"]
17pub struct W(crate::W<PDMCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDMCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDMCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDMCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "PDM Core Clock Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum PDMCLKSEL_A {
41    #[doc = "0: HFRCO clock is used to clock PDM"]
42    HFRCO = 0,
43    #[doc = "1: HFXO clock is used to clock PDM"]
44    HFXO = 1,
45    #[doc = "2: USHFRCO is used to clock PDM"]
46    USHFRCO = 2,
47    #[doc = "3: CLKIN0 is selected as HFCLK clock source"]
48    CLKIN0 = 3,
49}
50impl From<PDMCLKSEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: PDMCLKSEL_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `PDMCLKSEL` reader - PDM Core Clock Select"]
57pub type PDMCLKSEL_R = crate::FieldReader<u8, PDMCLKSEL_A>;
58impl PDMCLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> PDMCLKSEL_A {
62        match self.bits {
63            0 => PDMCLKSEL_A::HFRCO,
64            1 => PDMCLKSEL_A::HFXO,
65            2 => PDMCLKSEL_A::USHFRCO,
66            3 => PDMCLKSEL_A::CLKIN0,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `HFRCO`"]
71    #[inline(always)]
72    pub fn is_hfrco(&self) -> bool {
73        *self == PDMCLKSEL_A::HFRCO
74    }
75    #[doc = "Checks if the value of the field is `HFXO`"]
76    #[inline(always)]
77    pub fn is_hfxo(&self) -> bool {
78        *self == PDMCLKSEL_A::HFXO
79    }
80    #[doc = "Checks if the value of the field is `USHFRCO`"]
81    #[inline(always)]
82    pub fn is_ushfrco(&self) -> bool {
83        *self == PDMCLKSEL_A::USHFRCO
84    }
85    #[doc = "Checks if the value of the field is `CLKIN0`"]
86    #[inline(always)]
87    pub fn is_clkin0(&self) -> bool {
88        *self == PDMCLKSEL_A::CLKIN0
89    }
90}
91#[doc = "Field `PDMCLKSEL` writer - PDM Core Clock Select"]
92pub type PDMCLKSEL_W<'a> = crate::FieldWriterSafe<'a, u32, PDMCTRL_SPEC, u8, PDMCLKSEL_A, 2, 0>;
93impl<'a> PDMCLKSEL_W<'a> {
94    #[doc = "HFRCO clock is used to clock PDM"]
95    #[inline(always)]
96    pub fn hfrco(self) -> &'a mut W {
97        self.variant(PDMCLKSEL_A::HFRCO)
98    }
99    #[doc = "HFXO clock is used to clock PDM"]
100    #[inline(always)]
101    pub fn hfxo(self) -> &'a mut W {
102        self.variant(PDMCLKSEL_A::HFXO)
103    }
104    #[doc = "USHFRCO is used to clock PDM"]
105    #[inline(always)]
106    pub fn ushfrco(self) -> &'a mut W {
107        self.variant(PDMCLKSEL_A::USHFRCO)
108    }
109    #[doc = "CLKIN0 is selected as HFCLK clock source"]
110    #[inline(always)]
111    pub fn clkin0(self) -> &'a mut W {
112        self.variant(PDMCLKSEL_A::CLKIN0)
113    }
114}
115#[doc = "Field `PDMCLKEN` reader - PDM Core Clock Enable"]
116pub type PDMCLKEN_R = crate::BitReader<bool>;
117#[doc = "Field `PDMCLKEN` writer - PDM Core Clock Enable"]
118pub type PDMCLKEN_W<'a> = crate::BitWriter<'a, u32, PDMCTRL_SPEC, bool, 7>;
119impl R {
120    #[doc = "Bits 0:1 - PDM Core Clock Select"]
121    #[inline(always)]
122    pub fn pdmclksel(&self) -> PDMCLKSEL_R {
123        PDMCLKSEL_R::new((self.bits & 3) as u8)
124    }
125    #[doc = "Bit 7 - PDM Core Clock Enable"]
126    #[inline(always)]
127    pub fn pdmclken(&self) -> PDMCLKEN_R {
128        PDMCLKEN_R::new(((self.bits >> 7) & 1) != 0)
129    }
130}
131impl W {
132    #[doc = "Bits 0:1 - PDM Core Clock Select"]
133    #[inline(always)]
134    pub fn pdmclksel(&mut self) -> PDMCLKSEL_W {
135        PDMCLKSEL_W::new(self)
136    }
137    #[doc = "Bit 7 - PDM Core Clock Enable"]
138    #[inline(always)]
139    pub fn pdmclken(&mut self) -> PDMCLKEN_W {
140        PDMCLKEN_W::new(self)
141    }
142    #[doc = "Writes raw bits to the register."]
143    #[inline(always)]
144    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
145        self.0.bits(bits);
146        self
147    }
148}
149#[doc = "PDM Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdmctrl](index.html) module"]
150pub struct PDMCTRL_SPEC;
151impl crate::RegisterSpec for PDMCTRL_SPEC {
152    type Ux = u32;
153}
154#[doc = "`read()` method returns [pdmctrl::R](R) reader structure"]
155impl crate::Readable for PDMCTRL_SPEC {
156    type Reader = R;
157}
158#[doc = "`write(|w| ..)` method takes [pdmctrl::W](W) writer structure"]
159impl crate::Writable for PDMCTRL_SPEC {
160    type Writer = W;
161}
162#[doc = "`reset()` method sets PDMCTRL to value 0"]
163impl crate::Resettable for PDMCTRL_SPEC {
164    #[inline(always)]
165    fn reset_value() -> Self::Ux {
166        0
167    }
168}
efm32gg12b830_pac/cmu/pdmctrl.rs

efm32gg12b830_pac/cmu/
pdmctrl.rs
