efm32gg12b830_pac/cmu/
hfbusclken0.rs1#[doc = "Register `HFBUSCLKEN0` reader"]
2pub struct R(crate::R<HFBUSCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFBUSCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFBUSCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFBUSCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFBUSCLKEN0` writer"]
17pub struct W(crate::W<HFBUSCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFBUSCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFBUSCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFBUSCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `LE` reader - Low Energy Peripheral Interface Clock Enable"]
38pub type LE_R = crate::BitReader<bool>;
39#[doc = "Field `LE` writer - Low Energy Peripheral Interface Clock Enable"]
40pub type LE_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator Clock Enable"]
42pub type CRYPTO0_R = crate::BitReader<bool>;
43#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator Clock Enable"]
44pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `EBI` reader - External Bus Interface Clock Enable"]
46pub type EBI_R = crate::BitReader<bool>;
47#[doc = "Field `EBI` writer - External Bus Interface Clock Enable"]
48pub type EBI_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `SDIO` reader - SDIO Controller Clock Enable"]
50pub type SDIO_R = crate::BitReader<bool>;
51#[doc = "Field `SDIO` writer - SDIO Controller Clock Enable"]
52pub type SDIO_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
54pub type GPIO_R = crate::BitReader<bool>;
55#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
56pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
58pub type PRS_R = crate::BitReader<bool>;
59#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
60pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller Clock Enable"]
62pub type LDMA_R = crate::BitReader<bool>;
63#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller Clock Enable"]
64pub type LDMA_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `GPCRC` reader - General Purpose CRC Clock Enable"]
66pub type GPCRC_R = crate::BitReader<bool>;
67#[doc = "Field `GPCRC` writer - General Purpose CRC Clock Enable"]
68pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `QSPI0` reader - Quad-SPI Clock Enable"]
70pub type QSPI0_R = crate::BitReader<bool>;
71#[doc = "Field `QSPI0` writer - Quad-SPI Clock Enable"]
72pub type QSPI0_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `USB` reader - Universal Serial Bus Interface Clock Enable"]
74pub type USB_R = crate::BitReader<bool>;
75#[doc = "Field `USB` writer - Universal Serial Bus Interface Clock Enable"]
76pub type USB_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 9>;
77impl R {
78 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
79 #[inline(always)]
80 pub fn le(&self) -> LE_R {
81 LE_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
84 #[inline(always)]
85 pub fn crypto0(&self) -> CRYPTO0_R {
86 CRYPTO0_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - External Bus Interface Clock Enable"]
89 #[inline(always)]
90 pub fn ebi(&self) -> EBI_R {
91 EBI_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - SDIO Controller Clock Enable"]
94 #[inline(always)]
95 pub fn sdio(&self) -> SDIO_R {
96 SDIO_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - General purpose Input/Output Clock Enable"]
99 #[inline(always)]
100 pub fn gpio(&self) -> GPIO_R {
101 GPIO_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - Peripheral Reflex System Clock Enable"]
104 #[inline(always)]
105 pub fn prs(&self) -> PRS_R {
106 PRS_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 6 - Linked Direct Memory Access Controller Clock Enable"]
109 #[inline(always)]
110 pub fn ldma(&self) -> LDMA_R {
111 LDMA_R::new(((self.bits >> 6) & 1) != 0)
112 }
113 #[doc = "Bit 7 - General Purpose CRC Clock Enable"]
114 #[inline(always)]
115 pub fn gpcrc(&self) -> GPCRC_R {
116 GPCRC_R::new(((self.bits >> 7) & 1) != 0)
117 }
118 #[doc = "Bit 8 - Quad-SPI Clock Enable"]
119 #[inline(always)]
120 pub fn qspi0(&self) -> QSPI0_R {
121 QSPI0_R::new(((self.bits >> 8) & 1) != 0)
122 }
123 #[doc = "Bit 9 - Universal Serial Bus Interface Clock Enable"]
124 #[inline(always)]
125 pub fn usb(&self) -> USB_R {
126 USB_R::new(((self.bits >> 9) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
131 #[inline(always)]
132 pub fn le(&mut self) -> LE_W {
133 LE_W::new(self)
134 }
135 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
136 #[inline(always)]
137 pub fn crypto0(&mut self) -> CRYPTO0_W {
138 CRYPTO0_W::new(self)
139 }
140 #[doc = "Bit 2 - External Bus Interface Clock Enable"]
141 #[inline(always)]
142 pub fn ebi(&mut self) -> EBI_W {
143 EBI_W::new(self)
144 }
145 #[doc = "Bit 3 - SDIO Controller Clock Enable"]
146 #[inline(always)]
147 pub fn sdio(&mut self) -> SDIO_W {
148 SDIO_W::new(self)
149 }
150 #[doc = "Bit 4 - General purpose Input/Output Clock Enable"]
151 #[inline(always)]
152 pub fn gpio(&mut self) -> GPIO_W {
153 GPIO_W::new(self)
154 }
155 #[doc = "Bit 5 - Peripheral Reflex System Clock Enable"]
156 #[inline(always)]
157 pub fn prs(&mut self) -> PRS_W {
158 PRS_W::new(self)
159 }
160 #[doc = "Bit 6 - Linked Direct Memory Access Controller Clock Enable"]
161 #[inline(always)]
162 pub fn ldma(&mut self) -> LDMA_W {
163 LDMA_W::new(self)
164 }
165 #[doc = "Bit 7 - General Purpose CRC Clock Enable"]
166 #[inline(always)]
167 pub fn gpcrc(&mut self) -> GPCRC_W {
168 GPCRC_W::new(self)
169 }
170 #[doc = "Bit 8 - Quad-SPI Clock Enable"]
171 #[inline(always)]
172 pub fn qspi0(&mut self) -> QSPI0_W {
173 QSPI0_W::new(self)
174 }
175 #[doc = "Bit 9 - Universal Serial Bus Interface Clock Enable"]
176 #[inline(always)]
177 pub fn usb(&mut self) -> USB_W {
178 USB_W::new(self)
179 }
180 #[doc = "Writes raw bits to the register."]
181 #[inline(always)]
182 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183 self.0.bits(bits);
184 self
185 }
186}
187#[doc = "High Frequency Bus Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfbusclken0](index.html) module"]
188pub struct HFBUSCLKEN0_SPEC;
189impl crate::RegisterSpec for HFBUSCLKEN0_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [hfbusclken0::R](R) reader structure"]
193impl crate::Readable for HFBUSCLKEN0_SPEC {
194 type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [hfbusclken0::W](W) writer structure"]
197impl crate::Writable for HFBUSCLKEN0_SPEC {
198 type Writer = W;
199}
200#[doc = "`reset()` method sets HFBUSCLKEN0 to value 0"]
201impl crate::Resettable for HFBUSCLKEN0_SPEC {
202 #[inline(always)]
203 fn reset_value() -> Self::Ux {
204 0
205 }
206}