efm32gg12b810_pac/uart0/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TXC` reader - TXC Interrupt Enable"]
38pub type TXC_R = crate::BitReader<bool>;
39#[doc = "Field `TXC` writer - TXC Interrupt Enable"]
40pub type TXC_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `TXBL` reader - TXBL Interrupt Enable"]
42pub type TXBL_R = crate::BitReader<bool>;
43#[doc = "Field `TXBL` writer - TXBL Interrupt Enable"]
44pub type TXBL_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `RXDATAV` reader - RXDATAV Interrupt Enable"]
46pub type RXDATAV_R = crate::BitReader<bool>;
47#[doc = "Field `RXDATAV` writer - RXDATAV Interrupt Enable"]
48pub type RXDATAV_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `RXFULL` reader - RXFULL Interrupt Enable"]
50pub type RXFULL_R = crate::BitReader<bool>;
51#[doc = "Field `RXFULL` writer - RXFULL Interrupt Enable"]
52pub type RXFULL_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `RXOF` reader - RXOF Interrupt Enable"]
54pub type RXOF_R = crate::BitReader<bool>;
55#[doc = "Field `RXOF` writer - RXOF Interrupt Enable"]
56pub type RXOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `RXUF` reader - RXUF Interrupt Enable"]
58pub type RXUF_R = crate::BitReader<bool>;
59#[doc = "Field `RXUF` writer - RXUF Interrupt Enable"]
60pub type RXUF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `TXOF` reader - TXOF Interrupt Enable"]
62pub type TXOF_R = crate::BitReader<bool>;
63#[doc = "Field `TXOF` writer - TXOF Interrupt Enable"]
64pub type TXOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `TXUF` reader - TXUF Interrupt Enable"]
66pub type TXUF_R = crate::BitReader<bool>;
67#[doc = "Field `TXUF` writer - TXUF Interrupt Enable"]
68pub type TXUF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 7>;
69#[doc = "Field `PERR` reader - PERR Interrupt Enable"]
70pub type PERR_R = crate::BitReader<bool>;
71#[doc = "Field `PERR` writer - PERR Interrupt Enable"]
72pub type PERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
73#[doc = "Field `FERR` reader - FERR Interrupt Enable"]
74pub type FERR_R = crate::BitReader<bool>;
75#[doc = "Field `FERR` writer - FERR Interrupt Enable"]
76pub type FERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 9>;
77#[doc = "Field `MPAF` reader - MPAF Interrupt Enable"]
78pub type MPAF_R = crate::BitReader<bool>;
79#[doc = "Field `MPAF` writer - MPAF Interrupt Enable"]
80pub type MPAF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 10>;
81#[doc = "Field `SSM` reader - SSM Interrupt Enable"]
82pub type SSM_R = crate::BitReader<bool>;
83#[doc = "Field `SSM` writer - SSM Interrupt Enable"]
84pub type SSM_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 11>;
85#[doc = "Field `CCF` reader - CCF Interrupt Enable"]
86pub type CCF_R = crate::BitReader<bool>;
87#[doc = "Field `CCF` writer - CCF Interrupt Enable"]
88pub type CCF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 12>;
89#[doc = "Field `TXIDLE` reader - TXIDLE Interrupt Enable"]
90pub type TXIDLE_R = crate::BitReader<bool>;
91#[doc = "Field `TXIDLE` writer - TXIDLE Interrupt Enable"]
92pub type TXIDLE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 13>;
93#[doc = "Field `TCMP0` reader - TCMP0 Interrupt Enable"]
94pub type TCMP0_R = crate::BitReader<bool>;
95#[doc = "Field `TCMP0` writer - TCMP0 Interrupt Enable"]
96pub type TCMP0_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 14>;
97#[doc = "Field `TCMP1` reader - TCMP1 Interrupt Enable"]
98pub type TCMP1_R = crate::BitReader<bool>;
99#[doc = "Field `TCMP1` writer - TCMP1 Interrupt Enable"]
100pub type TCMP1_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 15>;
101#[doc = "Field `TCMP2` reader - TCMP2 Interrupt Enable"]
102pub type TCMP2_R = crate::BitReader<bool>;
103#[doc = "Field `TCMP2` writer - TCMP2 Interrupt Enable"]
104pub type TCMP2_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 16>;
105impl R {
106    #[doc = "Bit 0 - TXC Interrupt Enable"]
107    #[inline(always)]
108    pub fn txc(&self) -> TXC_R {
109        TXC_R::new((self.bits & 1) != 0)
110    }
111    #[doc = "Bit 1 - TXBL Interrupt Enable"]
112    #[inline(always)]
113    pub fn txbl(&self) -> TXBL_R {
114        TXBL_R::new(((self.bits >> 1) & 1) != 0)
115    }
116    #[doc = "Bit 2 - RXDATAV Interrupt Enable"]
117    #[inline(always)]
118    pub fn rxdatav(&self) -> RXDATAV_R {
119        RXDATAV_R::new(((self.bits >> 2) & 1) != 0)
120    }
121    #[doc = "Bit 3 - RXFULL Interrupt Enable"]
122    #[inline(always)]
123    pub fn rxfull(&self) -> RXFULL_R {
124        RXFULL_R::new(((self.bits >> 3) & 1) != 0)
125    }
126    #[doc = "Bit 4 - RXOF Interrupt Enable"]
127    #[inline(always)]
128    pub fn rxof(&self) -> RXOF_R {
129        RXOF_R::new(((self.bits >> 4) & 1) != 0)
130    }
131    #[doc = "Bit 5 - RXUF Interrupt Enable"]
132    #[inline(always)]
133    pub fn rxuf(&self) -> RXUF_R {
134        RXUF_R::new(((self.bits >> 5) & 1) != 0)
135    }
136    #[doc = "Bit 6 - TXOF Interrupt Enable"]
137    #[inline(always)]
138    pub fn txof(&self) -> TXOF_R {
139        TXOF_R::new(((self.bits >> 6) & 1) != 0)
140    }
141    #[doc = "Bit 7 - TXUF Interrupt Enable"]
142    #[inline(always)]
143    pub fn txuf(&self) -> TXUF_R {
144        TXUF_R::new(((self.bits >> 7) & 1) != 0)
145    }
146    #[doc = "Bit 8 - PERR Interrupt Enable"]
147    #[inline(always)]
148    pub fn perr(&self) -> PERR_R {
149        PERR_R::new(((self.bits >> 8) & 1) != 0)
150    }
151    #[doc = "Bit 9 - FERR Interrupt Enable"]
152    #[inline(always)]
153    pub fn ferr(&self) -> FERR_R {
154        FERR_R::new(((self.bits >> 9) & 1) != 0)
155    }
156    #[doc = "Bit 10 - MPAF Interrupt Enable"]
157    #[inline(always)]
158    pub fn mpaf(&self) -> MPAF_R {
159        MPAF_R::new(((self.bits >> 10) & 1) != 0)
160    }
161    #[doc = "Bit 11 - SSM Interrupt Enable"]
162    #[inline(always)]
163    pub fn ssm(&self) -> SSM_R {
164        SSM_R::new(((self.bits >> 11) & 1) != 0)
165    }
166    #[doc = "Bit 12 - CCF Interrupt Enable"]
167    #[inline(always)]
168    pub fn ccf(&self) -> CCF_R {
169        CCF_R::new(((self.bits >> 12) & 1) != 0)
170    }
171    #[doc = "Bit 13 - TXIDLE Interrupt Enable"]
172    #[inline(always)]
173    pub fn txidle(&self) -> TXIDLE_R {
174        TXIDLE_R::new(((self.bits >> 13) & 1) != 0)
175    }
176    #[doc = "Bit 14 - TCMP0 Interrupt Enable"]
177    #[inline(always)]
178    pub fn tcmp0(&self) -> TCMP0_R {
179        TCMP0_R::new(((self.bits >> 14) & 1) != 0)
180    }
181    #[doc = "Bit 15 - TCMP1 Interrupt Enable"]
182    #[inline(always)]
183    pub fn tcmp1(&self) -> TCMP1_R {
184        TCMP1_R::new(((self.bits >> 15) & 1) != 0)
185    }
186    #[doc = "Bit 16 - TCMP2 Interrupt Enable"]
187    #[inline(always)]
188    pub fn tcmp2(&self) -> TCMP2_R {
189        TCMP2_R::new(((self.bits >> 16) & 1) != 0)
190    }
191}
192impl W {
193    #[doc = "Bit 0 - TXC Interrupt Enable"]
194    #[inline(always)]
195    pub fn txc(&mut self) -> TXC_W {
196        TXC_W::new(self)
197    }
198    #[doc = "Bit 1 - TXBL Interrupt Enable"]
199    #[inline(always)]
200    pub fn txbl(&mut self) -> TXBL_W {
201        TXBL_W::new(self)
202    }
203    #[doc = "Bit 2 - RXDATAV Interrupt Enable"]
204    #[inline(always)]
205    pub fn rxdatav(&mut self) -> RXDATAV_W {
206        RXDATAV_W::new(self)
207    }
208    #[doc = "Bit 3 - RXFULL Interrupt Enable"]
209    #[inline(always)]
210    pub fn rxfull(&mut self) -> RXFULL_W {
211        RXFULL_W::new(self)
212    }
213    #[doc = "Bit 4 - RXOF Interrupt Enable"]
214    #[inline(always)]
215    pub fn rxof(&mut self) -> RXOF_W {
216        RXOF_W::new(self)
217    }
218    #[doc = "Bit 5 - RXUF Interrupt Enable"]
219    #[inline(always)]
220    pub fn rxuf(&mut self) -> RXUF_W {
221        RXUF_W::new(self)
222    }
223    #[doc = "Bit 6 - TXOF Interrupt Enable"]
224    #[inline(always)]
225    pub fn txof(&mut self) -> TXOF_W {
226        TXOF_W::new(self)
227    }
228    #[doc = "Bit 7 - TXUF Interrupt Enable"]
229    #[inline(always)]
230    pub fn txuf(&mut self) -> TXUF_W {
231        TXUF_W::new(self)
232    }
233    #[doc = "Bit 8 - PERR Interrupt Enable"]
234    #[inline(always)]
235    pub fn perr(&mut self) -> PERR_W {
236        PERR_W::new(self)
237    }
238    #[doc = "Bit 9 - FERR Interrupt Enable"]
239    #[inline(always)]
240    pub fn ferr(&mut self) -> FERR_W {
241        FERR_W::new(self)
242    }
243    #[doc = "Bit 10 - MPAF Interrupt Enable"]
244    #[inline(always)]
245    pub fn mpaf(&mut self) -> MPAF_W {
246        MPAF_W::new(self)
247    }
248    #[doc = "Bit 11 - SSM Interrupt Enable"]
249    #[inline(always)]
250    pub fn ssm(&mut self) -> SSM_W {
251        SSM_W::new(self)
252    }
253    #[doc = "Bit 12 - CCF Interrupt Enable"]
254    #[inline(always)]
255    pub fn ccf(&mut self) -> CCF_W {
256        CCF_W::new(self)
257    }
258    #[doc = "Bit 13 - TXIDLE Interrupt Enable"]
259    #[inline(always)]
260    pub fn txidle(&mut self) -> TXIDLE_W {
261        TXIDLE_W::new(self)
262    }
263    #[doc = "Bit 14 - TCMP0 Interrupt Enable"]
264    #[inline(always)]
265    pub fn tcmp0(&mut self) -> TCMP0_W {
266        TCMP0_W::new(self)
267    }
268    #[doc = "Bit 15 - TCMP1 Interrupt Enable"]
269    #[inline(always)]
270    pub fn tcmp1(&mut self) -> TCMP1_W {
271        TCMP1_W::new(self)
272    }
273    #[doc = "Bit 16 - TCMP2 Interrupt Enable"]
274    #[inline(always)]
275    pub fn tcmp2(&mut self) -> TCMP2_W {
276        TCMP2_W::new(self)
277    }
278    #[doc = "Writes raw bits to the register."]
279    #[inline(always)]
280    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
281        self.0.bits(bits);
282        self
283    }
284}
285#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
286pub struct IEN_SPEC;
287impl crate::RegisterSpec for IEN_SPEC {
288    type Ux = u32;
289}
290#[doc = "`read()` method returns [ien::R](R) reader structure"]
291impl crate::Readable for IEN_SPEC {
292    type Reader = R;
293}
294#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
295impl crate::Writable for IEN_SPEC {
296    type Writer = W;
297}
298#[doc = "`reset()` method sets IEN to value 0"]
299impl crate::Resettable for IEN_SPEC {
300    #[inline(always)]
301    fn reset_value() -> Self::Ux {
302        0
303    }
304}
efm32gg12b810_pac/uart0/ien.rs

efm32gg12b810_pac/uart0/
ien.rs
