efm32gg12b810_pac/qspi0/
config.rs

1#[doc = "Register `CONFIG` reader"]
2pub struct R(crate::R<CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CONFIG` writer"]
17pub struct W(crate::W<CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENBSPI` reader - QSPI Enable"]
38pub type ENBSPI_R = crate::BitReader<bool>;
39#[doc = "Field `ENBSPI` writer - QSPI Enable"]
40pub type ENBSPI_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 0>;
41#[doc = "Field `SELCLKPOL` reader - Clock Polarity, CPOL"]
42pub type SELCLKPOL_R = crate::BitReader<bool>;
43#[doc = "Field `SELCLKPOL` writer - Clock Polarity, CPOL"]
44pub type SELCLKPOL_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 1>;
45#[doc = "Field `SELCLKPHASE` reader - Clock Phase, CPHA"]
46pub type SELCLKPHASE_R = crate::BitReader<bool>;
47#[doc = "Field `SELCLKPHASE` writer - Clock Phase, CPHA"]
48pub type SELCLKPHASE_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 2>;
49#[doc = "Field `PHYMODEENABLE` reader - PHY Mode Enable"]
50pub type PHYMODEENABLE_R = crate::BitReader<bool>;
51#[doc = "Field `PHYMODEENABLE` writer - PHY Mode Enable"]
52pub type PHYMODEENABLE_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 3>;
53#[doc = "Field `ENBDEVHOLD` reader - Enable Device Hold"]
54pub type ENBDEVHOLD_R = crate::BitReader<bool>;
55#[doc = "Field `ENBDEVHOLD` writer - Enable Device Hold"]
56pub type ENBDEVHOLD_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 4>;
57#[doc = "Field `ENBDEVRST` reader - Enable Device Reset"]
58pub type ENBDEVRST_R = crate::BitReader<bool>;
59#[doc = "Field `ENBDEVRST` writer - Enable Device Reset"]
60pub type ENBDEVRST_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 5>;
61#[doc = "Field `DEVRSTCONFIG` reader - Device Reset Configuration"]
62pub type DEVRSTCONFIG_R = crate::BitReader<bool>;
63#[doc = "Field `DEVRSTCONFIG` writer - Device Reset Configuration"]
64pub type DEVRSTCONFIG_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 6>;
65#[doc = "Field `ENBDIRACCCTLR` reader - Enable Direct Access Controller"]
66pub type ENBDIRACCCTLR_R = crate::BitReader<bool>;
67#[doc = "Field `ENBDIRACCCTLR` writer - Enable Direct Access Controller"]
68pub type ENBDIRACCCTLR_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 7>;
69#[doc = "Field `ENBLEGACYIPMODE` reader - Legacy IP Mode Enable"]
70pub type ENBLEGACYIPMODE_R = crate::BitReader<bool>;
71#[doc = "Field `ENBLEGACYIPMODE` writer - Legacy IP Mode Enable"]
72pub type ENBLEGACYIPMODE_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 8>;
73#[doc = "Field `PERIPHSELDEC` reader - Peripheral Select Decode"]
74pub type PERIPHSELDEC_R = crate::BitReader<bool>;
75#[doc = "Field `PERIPHSELDEC` writer - Peripheral Select Decode"]
76pub type PERIPHSELDEC_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 9>;
77#[doc = "Field `PERIPHCSLINES` reader - Peripheral Chip Select Lines"]
78pub type PERIPHCSLINES_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `PERIPHCSLINES` writer - Peripheral Chip Select Lines"]
80pub type PERIPHCSLINES_W<'a> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 2, 10>;
81#[doc = "Field `WRPROTFLASH` reader - Write Protect Flash Pin"]
82pub type WRPROTFLASH_R = crate::BitReader<bool>;
83#[doc = "Field `WRPROTFLASH` writer - Write Protect Flash Pin"]
84pub type WRPROTFLASH_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 14>;
85#[doc = "Field `ENBAHBADDRREMAP` reader - Enable Address Remapping"]
86pub type ENBAHBADDRREMAP_R = crate::BitReader<bool>;
87#[doc = "Field `ENBAHBADDRREMAP` writer - Enable Address Remapping"]
88pub type ENBAHBADDRREMAP_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 16>;
89#[doc = "Field `ENTERXIPMODE` reader - Enter XIP Mode on Next READ"]
90pub type ENTERXIPMODE_R = crate::BitReader<bool>;
91#[doc = "Field `ENTERXIPMODE` writer - Enter XIP Mode on Next READ"]
92pub type ENTERXIPMODE_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 17>;
93#[doc = "Field `ENTERXIPMODEIMM` reader - Enter XIP Mode Immediately"]
94pub type ENTERXIPMODEIMM_R = crate::BitReader<bool>;
95#[doc = "Field `ENTERXIPMODEIMM` writer - Enter XIP Mode Immediately"]
96pub type ENTERXIPMODEIMM_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 18>;
97#[doc = "Field `MSTRBAUDDIV` reader - Master Mode Baud Rate Divisor"]
98pub type MSTRBAUDDIV_R = crate::FieldReader<u8, u8>;
99#[doc = "Field `MSTRBAUDDIV` writer - Master Mode Baud Rate Divisor"]
100pub type MSTRBAUDDIV_W<'a> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 4, 19>;
101#[doc = "Field `ENABLEAHBDECODER` reader - Enable Address Decoder"]
102pub type ENABLEAHBDECODER_R = crate::BitReader<bool>;
103#[doc = "Field `ENABLEAHBDECODER` writer - Enable Address Decoder"]
104pub type ENABLEAHBDECODER_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 23>;
105#[doc = "Field `ENABLEDTRPROTOCOL` reader - Enable DTR Protocol"]
106pub type ENABLEDTRPROTOCOL_R = crate::BitReader<bool>;
107#[doc = "Field `ENABLEDTRPROTOCOL` writer - Enable DTR Protocol"]
108pub type ENABLEDTRPROTOCOL_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 24>;
109#[doc = "Field `PIPELINEPHY` reader - Pipeline PHY Mode Enable"]
110pub type PIPELINEPHY_R = crate::BitReader<bool>;
111#[doc = "Field `PIPELINEPHY` writer - Pipeline PHY Mode Enable"]
112pub type PIPELINEPHY_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 25>;
113#[doc = "Field `CRCENABLE` reader - CRC Enable Bit"]
114pub type CRCENABLE_R = crate::BitReader<bool>;
115#[doc = "Field `CRCENABLE` writer - CRC Enable Bit"]
116pub type CRCENABLE_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 29>;
117#[doc = "Field `DUALBYTEOPCODEEN` reader - Dual-byte Opcode Mode Enable Bit"]
118pub type DUALBYTEOPCODEEN_R = crate::BitReader<bool>;
119#[doc = "Field `DUALBYTEOPCODEEN` writer - Dual-byte Opcode Mode Enable Bit"]
120pub type DUALBYTEOPCODEEN_W<'a> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, 30>;
121#[doc = "Field `IDLE` reader - Serial Interface and Low Level SPI Pipeline is IDLE"]
122pub type IDLE_R = crate::BitReader<bool>;
123impl R {
124    #[doc = "Bit 0 - QSPI Enable"]
125    #[inline(always)]
126    pub fn enbspi(&self) -> ENBSPI_R {
127        ENBSPI_R::new((self.bits & 1) != 0)
128    }
129    #[doc = "Bit 1 - Clock Polarity, CPOL"]
130    #[inline(always)]
131    pub fn selclkpol(&self) -> SELCLKPOL_R {
132        SELCLKPOL_R::new(((self.bits >> 1) & 1) != 0)
133    }
134    #[doc = "Bit 2 - Clock Phase, CPHA"]
135    #[inline(always)]
136    pub fn selclkphase(&self) -> SELCLKPHASE_R {
137        SELCLKPHASE_R::new(((self.bits >> 2) & 1) != 0)
138    }
139    #[doc = "Bit 3 - PHY Mode Enable"]
140    #[inline(always)]
141    pub fn phymodeenable(&self) -> PHYMODEENABLE_R {
142        PHYMODEENABLE_R::new(((self.bits >> 3) & 1) != 0)
143    }
144    #[doc = "Bit 4 - Enable Device Hold"]
145    #[inline(always)]
146    pub fn enbdevhold(&self) -> ENBDEVHOLD_R {
147        ENBDEVHOLD_R::new(((self.bits >> 4) & 1) != 0)
148    }
149    #[doc = "Bit 5 - Enable Device Reset"]
150    #[inline(always)]
151    pub fn enbdevrst(&self) -> ENBDEVRST_R {
152        ENBDEVRST_R::new(((self.bits >> 5) & 1) != 0)
153    }
154    #[doc = "Bit 6 - Device Reset Configuration"]
155    #[inline(always)]
156    pub fn devrstconfig(&self) -> DEVRSTCONFIG_R {
157        DEVRSTCONFIG_R::new(((self.bits >> 6) & 1) != 0)
158    }
159    #[doc = "Bit 7 - Enable Direct Access Controller"]
160    #[inline(always)]
161    pub fn enbdiraccctlr(&self) -> ENBDIRACCCTLR_R {
162        ENBDIRACCCTLR_R::new(((self.bits >> 7) & 1) != 0)
163    }
164    #[doc = "Bit 8 - Legacy IP Mode Enable"]
165    #[inline(always)]
166    pub fn enblegacyipmode(&self) -> ENBLEGACYIPMODE_R {
167        ENBLEGACYIPMODE_R::new(((self.bits >> 8) & 1) != 0)
168    }
169    #[doc = "Bit 9 - Peripheral Select Decode"]
170    #[inline(always)]
171    pub fn periphseldec(&self) -> PERIPHSELDEC_R {
172        PERIPHSELDEC_R::new(((self.bits >> 9) & 1) != 0)
173    }
174    #[doc = "Bits 10:11 - Peripheral Chip Select Lines"]
175    #[inline(always)]
176    pub fn periphcslines(&self) -> PERIPHCSLINES_R {
177        PERIPHCSLINES_R::new(((self.bits >> 10) & 3) as u8)
178    }
179    #[doc = "Bit 14 - Write Protect Flash Pin"]
180    #[inline(always)]
181    pub fn wrprotflash(&self) -> WRPROTFLASH_R {
182        WRPROTFLASH_R::new(((self.bits >> 14) & 1) != 0)
183    }
184    #[doc = "Bit 16 - Enable Address Remapping"]
185    #[inline(always)]
186    pub fn enbahbaddrremap(&self) -> ENBAHBADDRREMAP_R {
187        ENBAHBADDRREMAP_R::new(((self.bits >> 16) & 1) != 0)
188    }
189    #[doc = "Bit 17 - Enter XIP Mode on Next READ"]
190    #[inline(always)]
191    pub fn enterxipmode(&self) -> ENTERXIPMODE_R {
192        ENTERXIPMODE_R::new(((self.bits >> 17) & 1) != 0)
193    }
194    #[doc = "Bit 18 - Enter XIP Mode Immediately"]
195    #[inline(always)]
196    pub fn enterxipmodeimm(&self) -> ENTERXIPMODEIMM_R {
197        ENTERXIPMODEIMM_R::new(((self.bits >> 18) & 1) != 0)
198    }
199    #[doc = "Bits 19:22 - Master Mode Baud Rate Divisor"]
200    #[inline(always)]
201    pub fn mstrbauddiv(&self) -> MSTRBAUDDIV_R {
202        MSTRBAUDDIV_R::new(((self.bits >> 19) & 0x0f) as u8)
203    }
204    #[doc = "Bit 23 - Enable Address Decoder"]
205    #[inline(always)]
206    pub fn enableahbdecoder(&self) -> ENABLEAHBDECODER_R {
207        ENABLEAHBDECODER_R::new(((self.bits >> 23) & 1) != 0)
208    }
209    #[doc = "Bit 24 - Enable DTR Protocol"]
210    #[inline(always)]
211    pub fn enabledtrprotocol(&self) -> ENABLEDTRPROTOCOL_R {
212        ENABLEDTRPROTOCOL_R::new(((self.bits >> 24) & 1) != 0)
213    }
214    #[doc = "Bit 25 - Pipeline PHY Mode Enable"]
215    #[inline(always)]
216    pub fn pipelinephy(&self) -> PIPELINEPHY_R {
217        PIPELINEPHY_R::new(((self.bits >> 25) & 1) != 0)
218    }
219    #[doc = "Bit 29 - CRC Enable Bit"]
220    #[inline(always)]
221    pub fn crcenable(&self) -> CRCENABLE_R {
222        CRCENABLE_R::new(((self.bits >> 29) & 1) != 0)
223    }
224    #[doc = "Bit 30 - Dual-byte Opcode Mode Enable Bit"]
225    #[inline(always)]
226    pub fn dualbyteopcodeen(&self) -> DUALBYTEOPCODEEN_R {
227        DUALBYTEOPCODEEN_R::new(((self.bits >> 30) & 1) != 0)
228    }
229    #[doc = "Bit 31 - Serial Interface and Low Level SPI Pipeline is IDLE"]
230    #[inline(always)]
231    pub fn idle(&self) -> IDLE_R {
232        IDLE_R::new(((self.bits >> 31) & 1) != 0)
233    }
234}
235impl W {
236    #[doc = "Bit 0 - QSPI Enable"]
237    #[inline(always)]
238    pub fn enbspi(&mut self) -> ENBSPI_W {
239        ENBSPI_W::new(self)
240    }
241    #[doc = "Bit 1 - Clock Polarity, CPOL"]
242    #[inline(always)]
243    pub fn selclkpol(&mut self) -> SELCLKPOL_W {
244        SELCLKPOL_W::new(self)
245    }
246    #[doc = "Bit 2 - Clock Phase, CPHA"]
247    #[inline(always)]
248    pub fn selclkphase(&mut self) -> SELCLKPHASE_W {
249        SELCLKPHASE_W::new(self)
250    }
251    #[doc = "Bit 3 - PHY Mode Enable"]
252    #[inline(always)]
253    pub fn phymodeenable(&mut self) -> PHYMODEENABLE_W {
254        PHYMODEENABLE_W::new(self)
255    }
256    #[doc = "Bit 4 - Enable Device Hold"]
257    #[inline(always)]
258    pub fn enbdevhold(&mut self) -> ENBDEVHOLD_W {
259        ENBDEVHOLD_W::new(self)
260    }
261    #[doc = "Bit 5 - Enable Device Reset"]
262    #[inline(always)]
263    pub fn enbdevrst(&mut self) -> ENBDEVRST_W {
264        ENBDEVRST_W::new(self)
265    }
266    #[doc = "Bit 6 - Device Reset Configuration"]
267    #[inline(always)]
268    pub fn devrstconfig(&mut self) -> DEVRSTCONFIG_W {
269        DEVRSTCONFIG_W::new(self)
270    }
271    #[doc = "Bit 7 - Enable Direct Access Controller"]
272    #[inline(always)]
273    pub fn enbdiraccctlr(&mut self) -> ENBDIRACCCTLR_W {
274        ENBDIRACCCTLR_W::new(self)
275    }
276    #[doc = "Bit 8 - Legacy IP Mode Enable"]
277    #[inline(always)]
278    pub fn enblegacyipmode(&mut self) -> ENBLEGACYIPMODE_W {
279        ENBLEGACYIPMODE_W::new(self)
280    }
281    #[doc = "Bit 9 - Peripheral Select Decode"]
282    #[inline(always)]
283    pub fn periphseldec(&mut self) -> PERIPHSELDEC_W {
284        PERIPHSELDEC_W::new(self)
285    }
286    #[doc = "Bits 10:11 - Peripheral Chip Select Lines"]
287    #[inline(always)]
288    pub fn periphcslines(&mut self) -> PERIPHCSLINES_W {
289        PERIPHCSLINES_W::new(self)
290    }
291    #[doc = "Bit 14 - Write Protect Flash Pin"]
292    #[inline(always)]
293    pub fn wrprotflash(&mut self) -> WRPROTFLASH_W {
294        WRPROTFLASH_W::new(self)
295    }
296    #[doc = "Bit 16 - Enable Address Remapping"]
297    #[inline(always)]
298    pub fn enbahbaddrremap(&mut self) -> ENBAHBADDRREMAP_W {
299        ENBAHBADDRREMAP_W::new(self)
300    }
301    #[doc = "Bit 17 - Enter XIP Mode on Next READ"]
302    #[inline(always)]
303    pub fn enterxipmode(&mut self) -> ENTERXIPMODE_W {
304        ENTERXIPMODE_W::new(self)
305    }
306    #[doc = "Bit 18 - Enter XIP Mode Immediately"]
307    #[inline(always)]
308    pub fn enterxipmodeimm(&mut self) -> ENTERXIPMODEIMM_W {
309        ENTERXIPMODEIMM_W::new(self)
310    }
311    #[doc = "Bits 19:22 - Master Mode Baud Rate Divisor"]
312    #[inline(always)]
313    pub fn mstrbauddiv(&mut self) -> MSTRBAUDDIV_W {
314        MSTRBAUDDIV_W::new(self)
315    }
316    #[doc = "Bit 23 - Enable Address Decoder"]
317    #[inline(always)]
318    pub fn enableahbdecoder(&mut self) -> ENABLEAHBDECODER_W {
319        ENABLEAHBDECODER_W::new(self)
320    }
321    #[doc = "Bit 24 - Enable DTR Protocol"]
322    #[inline(always)]
323    pub fn enabledtrprotocol(&mut self) -> ENABLEDTRPROTOCOL_W {
324        ENABLEDTRPROTOCOL_W::new(self)
325    }
326    #[doc = "Bit 25 - Pipeline PHY Mode Enable"]
327    #[inline(always)]
328    pub fn pipelinephy(&mut self) -> PIPELINEPHY_W {
329        PIPELINEPHY_W::new(self)
330    }
331    #[doc = "Bit 29 - CRC Enable Bit"]
332    #[inline(always)]
333    pub fn crcenable(&mut self) -> CRCENABLE_W {
334        CRCENABLE_W::new(self)
335    }
336    #[doc = "Bit 30 - Dual-byte Opcode Mode Enable Bit"]
337    #[inline(always)]
338    pub fn dualbyteopcodeen(&mut self) -> DUALBYTEOPCODEEN_W {
339        DUALBYTEOPCODEEN_W::new(self)
340    }
341    #[doc = "Writes raw bits to the register."]
342    #[inline(always)]
343    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
344        self.0.bits(bits);
345        self
346    }
347}
348#[doc = "Octal-SPI Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
349pub struct CONFIG_SPEC;
350impl crate::RegisterSpec for CONFIG_SPEC {
351    type Ux = u32;
352}
353#[doc = "`read()` method returns [config::R](R) reader structure"]
354impl crate::Readable for CONFIG_SPEC {
355    type Reader = R;
356}
357#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
358impl crate::Writable for CONFIG_SPEC {
359    type Writer = W;
360}
361#[doc = "`reset()` method sets CONFIG to value 0x8078_0081"]
362impl crate::Resettable for CONFIG_SPEC {
363    #[inline(always)]
364    fn reset_value() -> Self::Ux {
365        0x8078_0081
366    }
367}
efm32gg12b810_pac/qspi0/config.rs

efm32gg12b810_pac/qspi0/
config.rs
