efm32gg12b810_pac/prs/
ch4_ctrl.rs

1#[doc = "Register `CH4_CTRL` reader"]
2pub struct R(crate::R<CH4_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH4_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH4_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH4_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH4_CTRL` writer"]
17pub struct W(crate::W<CH4_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH4_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH4_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH4_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRS = 2,
51    #[doc = "4: Analog Comparator 0"]
52    ACMP0 = 4,
53    #[doc = "5: Analog Comparator 1"]
54    ACMP1 = 5,
55    #[doc = "6: Analog to Digital Converter 0"]
56    ADC0 = 6,
57    #[doc = "7: Real-Time Counter"]
58    RTC = 7,
59    #[doc = "8: Real-Time Counter and Calendar"]
60    RTCC = 8,
61    #[doc = "9: General purpose Input/Output"]
62    GPIOL = 9,
63    #[doc = "10: General purpose Input/Output"]
64    GPIOH = 10,
65    #[doc = "11: Low Energy Timer 0"]
66    LETIMER0 = 11,
67    #[doc = "12: Low Energy Timer 1"]
68    LETIMER1 = 12,
69    #[doc = "13: Pulse Counter 0"]
70    PCNT0 = 13,
71    #[doc = "14: Pulse Counter 1"]
72    PCNT1 = 14,
73    #[doc = "15: Pulse Counter 2"]
74    PCNT2 = 15,
75    #[doc = "16: CRYOTIMER"]
76    CRYOTIMER = 16,
77    #[doc = "17: Clock Management Unit"]
78    CMU = 17,
79    #[doc = "23: Digital to Analog Converter 0"]
80    VDAC0 = 23,
81    #[doc = "24: Low Energy Sensor Interface"]
82    LESENSEL = 24,
83    #[doc = "25: Low Energy Sensor Interface"]
84    LESENSEH = 25,
85    #[doc = "26: Low Energy Sensor Interface"]
86    LESENSED = 26,
87    #[doc = "27: Low Energy Sensor Interface"]
88    LESENSE = 27,
89    #[doc = "28: Analog Comparator 2"]
90    ACMP2 = 28,
91    #[doc = "29: Analog to Digital Converter 0"]
92    ADC1 = 29,
93    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
94    USART0 = 48,
95    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
96    USART1 = 49,
97    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
98    USART2 = 50,
99    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
100    USART3 = 51,
101    #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
102    USART4 = 52,
103    #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
104    UART0 = 54,
105    #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
106    UART1 = 55,
107    #[doc = "60: Timer 0"]
108    TIMER0 = 60,
109    #[doc = "61: Timer 1"]
110    TIMER1 = 61,
111    #[doc = "62: Timer 2"]
112    TIMER2 = 62,
113    #[doc = "64: Universal Serial Bus Interface"]
114    USB = 64,
115    #[doc = "67: `1000011`"]
116    CM4 = 67,
117    #[doc = "80: Timer 3"]
118    TIMER3 = 80,
119    #[doc = "82: Wide Timer 0"]
120    WTIMER0 = 82,
121    #[doc = "83: Wide Timer 0"]
122    WTIMER1 = 83,
123    #[doc = "121: PDM Interface"]
124    PDM = 121,
125}
126impl From<SOURCESEL_A> for u8 {
127    #[inline(always)]
128    fn from(variant: SOURCESEL_A) -> Self {
129        variant as _
130    }
131}
132#[doc = "Field `SOURCESEL` reader - Source Select"]
133pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
134impl SOURCESEL_R {
135    #[doc = "Get enumerated values variant"]
136    #[inline(always)]
137    pub fn variant(&self) -> Option<SOURCESEL_A> {
138        match self.bits {
139            0 => Some(SOURCESEL_A::NONE),
140            1 => Some(SOURCESEL_A::PRSL),
141            2 => Some(SOURCESEL_A::PRS),
142            4 => Some(SOURCESEL_A::ACMP0),
143            5 => Some(SOURCESEL_A::ACMP1),
144            6 => Some(SOURCESEL_A::ADC0),
145            7 => Some(SOURCESEL_A::RTC),
146            8 => Some(SOURCESEL_A::RTCC),
147            9 => Some(SOURCESEL_A::GPIOL),
148            10 => Some(SOURCESEL_A::GPIOH),
149            11 => Some(SOURCESEL_A::LETIMER0),
150            12 => Some(SOURCESEL_A::LETIMER1),
151            13 => Some(SOURCESEL_A::PCNT0),
152            14 => Some(SOURCESEL_A::PCNT1),
153            15 => Some(SOURCESEL_A::PCNT2),
154            16 => Some(SOURCESEL_A::CRYOTIMER),
155            17 => Some(SOURCESEL_A::CMU),
156            23 => Some(SOURCESEL_A::VDAC0),
157            24 => Some(SOURCESEL_A::LESENSEL),
158            25 => Some(SOURCESEL_A::LESENSEH),
159            26 => Some(SOURCESEL_A::LESENSED),
160            27 => Some(SOURCESEL_A::LESENSE),
161            28 => Some(SOURCESEL_A::ACMP2),
162            29 => Some(SOURCESEL_A::ADC1),
163            48 => Some(SOURCESEL_A::USART0),
164            49 => Some(SOURCESEL_A::USART1),
165            50 => Some(SOURCESEL_A::USART2),
166            51 => Some(SOURCESEL_A::USART3),
167            52 => Some(SOURCESEL_A::USART4),
168            54 => Some(SOURCESEL_A::UART0),
169            55 => Some(SOURCESEL_A::UART1),
170            60 => Some(SOURCESEL_A::TIMER0),
171            61 => Some(SOURCESEL_A::TIMER1),
172            62 => Some(SOURCESEL_A::TIMER2),
173            64 => Some(SOURCESEL_A::USB),
174            67 => Some(SOURCESEL_A::CM4),
175            80 => Some(SOURCESEL_A::TIMER3),
176            82 => Some(SOURCESEL_A::WTIMER0),
177            83 => Some(SOURCESEL_A::WTIMER1),
178            121 => Some(SOURCESEL_A::PDM),
179            _ => None,
180        }
181    }
182    #[doc = "Checks if the value of the field is `NONE`"]
183    #[inline(always)]
184    pub fn is_none(&self) -> bool {
185        *self == SOURCESEL_A::NONE
186    }
187    #[doc = "Checks if the value of the field is `PRSL`"]
188    #[inline(always)]
189    pub fn is_prsl(&self) -> bool {
190        *self == SOURCESEL_A::PRSL
191    }
192    #[doc = "Checks if the value of the field is `PRS`"]
193    #[inline(always)]
194    pub fn is_prs(&self) -> bool {
195        *self == SOURCESEL_A::PRS
196    }
197    #[doc = "Checks if the value of the field is `ACMP0`"]
198    #[inline(always)]
199    pub fn is_acmp0(&self) -> bool {
200        *self == SOURCESEL_A::ACMP0
201    }
202    #[doc = "Checks if the value of the field is `ACMP1`"]
203    #[inline(always)]
204    pub fn is_acmp1(&self) -> bool {
205        *self == SOURCESEL_A::ACMP1
206    }
207    #[doc = "Checks if the value of the field is `ADC0`"]
208    #[inline(always)]
209    pub fn is_adc0(&self) -> bool {
210        *self == SOURCESEL_A::ADC0
211    }
212    #[doc = "Checks if the value of the field is `RTC`"]
213    #[inline(always)]
214    pub fn is_rtc(&self) -> bool {
215        *self == SOURCESEL_A::RTC
216    }
217    #[doc = "Checks if the value of the field is `RTCC`"]
218    #[inline(always)]
219    pub fn is_rtcc(&self) -> bool {
220        *self == SOURCESEL_A::RTCC
221    }
222    #[doc = "Checks if the value of the field is `GPIOL`"]
223    #[inline(always)]
224    pub fn is_gpiol(&self) -> bool {
225        *self == SOURCESEL_A::GPIOL
226    }
227    #[doc = "Checks if the value of the field is `GPIOH`"]
228    #[inline(always)]
229    pub fn is_gpioh(&self) -> bool {
230        *self == SOURCESEL_A::GPIOH
231    }
232    #[doc = "Checks if the value of the field is `LETIMER0`"]
233    #[inline(always)]
234    pub fn is_letimer0(&self) -> bool {
235        *self == SOURCESEL_A::LETIMER0
236    }
237    #[doc = "Checks if the value of the field is `LETIMER1`"]
238    #[inline(always)]
239    pub fn is_letimer1(&self) -> bool {
240        *self == SOURCESEL_A::LETIMER1
241    }
242    #[doc = "Checks if the value of the field is `PCNT0`"]
243    #[inline(always)]
244    pub fn is_pcnt0(&self) -> bool {
245        *self == SOURCESEL_A::PCNT0
246    }
247    #[doc = "Checks if the value of the field is `PCNT1`"]
248    #[inline(always)]
249    pub fn is_pcnt1(&self) -> bool {
250        *self == SOURCESEL_A::PCNT1
251    }
252    #[doc = "Checks if the value of the field is `PCNT2`"]
253    #[inline(always)]
254    pub fn is_pcnt2(&self) -> bool {
255        *self == SOURCESEL_A::PCNT2
256    }
257    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
258    #[inline(always)]
259    pub fn is_cryotimer(&self) -> bool {
260        *self == SOURCESEL_A::CRYOTIMER
261    }
262    #[doc = "Checks if the value of the field is `CMU`"]
263    #[inline(always)]
264    pub fn is_cmu(&self) -> bool {
265        *self == SOURCESEL_A::CMU
266    }
267    #[doc = "Checks if the value of the field is `VDAC0`"]
268    #[inline(always)]
269    pub fn is_vdac0(&self) -> bool {
270        *self == SOURCESEL_A::VDAC0
271    }
272    #[doc = "Checks if the value of the field is `LESENSEL`"]
273    #[inline(always)]
274    pub fn is_lesensel(&self) -> bool {
275        *self == SOURCESEL_A::LESENSEL
276    }
277    #[doc = "Checks if the value of the field is `LESENSEH`"]
278    #[inline(always)]
279    pub fn is_lesenseh(&self) -> bool {
280        *self == SOURCESEL_A::LESENSEH
281    }
282    #[doc = "Checks if the value of the field is `LESENSED`"]
283    #[inline(always)]
284    pub fn is_lesensed(&self) -> bool {
285        *self == SOURCESEL_A::LESENSED
286    }
287    #[doc = "Checks if the value of the field is `LESENSE`"]
288    #[inline(always)]
289    pub fn is_lesense(&self) -> bool {
290        *self == SOURCESEL_A::LESENSE
291    }
292    #[doc = "Checks if the value of the field is `ACMP2`"]
293    #[inline(always)]
294    pub fn is_acmp2(&self) -> bool {
295        *self == SOURCESEL_A::ACMP2
296    }
297    #[doc = "Checks if the value of the field is `ADC1`"]
298    #[inline(always)]
299    pub fn is_adc1(&self) -> bool {
300        *self == SOURCESEL_A::ADC1
301    }
302    #[doc = "Checks if the value of the field is `USART0`"]
303    #[inline(always)]
304    pub fn is_usart0(&self) -> bool {
305        *self == SOURCESEL_A::USART0
306    }
307    #[doc = "Checks if the value of the field is `USART1`"]
308    #[inline(always)]
309    pub fn is_usart1(&self) -> bool {
310        *self == SOURCESEL_A::USART1
311    }
312    #[doc = "Checks if the value of the field is `USART2`"]
313    #[inline(always)]
314    pub fn is_usart2(&self) -> bool {
315        *self == SOURCESEL_A::USART2
316    }
317    #[doc = "Checks if the value of the field is `USART3`"]
318    #[inline(always)]
319    pub fn is_usart3(&self) -> bool {
320        *self == SOURCESEL_A::USART3
321    }
322    #[doc = "Checks if the value of the field is `USART4`"]
323    #[inline(always)]
324    pub fn is_usart4(&self) -> bool {
325        *self == SOURCESEL_A::USART4
326    }
327    #[doc = "Checks if the value of the field is `UART0`"]
328    #[inline(always)]
329    pub fn is_uart0(&self) -> bool {
330        *self == SOURCESEL_A::UART0
331    }
332    #[doc = "Checks if the value of the field is `UART1`"]
333    #[inline(always)]
334    pub fn is_uart1(&self) -> bool {
335        *self == SOURCESEL_A::UART1
336    }
337    #[doc = "Checks if the value of the field is `TIMER0`"]
338    #[inline(always)]
339    pub fn is_timer0(&self) -> bool {
340        *self == SOURCESEL_A::TIMER0
341    }
342    #[doc = "Checks if the value of the field is `TIMER1`"]
343    #[inline(always)]
344    pub fn is_timer1(&self) -> bool {
345        *self == SOURCESEL_A::TIMER1
346    }
347    #[doc = "Checks if the value of the field is `TIMER2`"]
348    #[inline(always)]
349    pub fn is_timer2(&self) -> bool {
350        *self == SOURCESEL_A::TIMER2
351    }
352    #[doc = "Checks if the value of the field is `USB`"]
353    #[inline(always)]
354    pub fn is_usb(&self) -> bool {
355        *self == SOURCESEL_A::USB
356    }
357    #[doc = "Checks if the value of the field is `CM4`"]
358    #[inline(always)]
359    pub fn is_cm4(&self) -> bool {
360        *self == SOURCESEL_A::CM4
361    }
362    #[doc = "Checks if the value of the field is `TIMER3`"]
363    #[inline(always)]
364    pub fn is_timer3(&self) -> bool {
365        *self == SOURCESEL_A::TIMER3
366    }
367    #[doc = "Checks if the value of the field is `WTIMER0`"]
368    #[inline(always)]
369    pub fn is_wtimer0(&self) -> bool {
370        *self == SOURCESEL_A::WTIMER0
371    }
372    #[doc = "Checks if the value of the field is `WTIMER1`"]
373    #[inline(always)]
374    pub fn is_wtimer1(&self) -> bool {
375        *self == SOURCESEL_A::WTIMER1
376    }
377    #[doc = "Checks if the value of the field is `PDM`"]
378    #[inline(always)]
379    pub fn is_pdm(&self) -> bool {
380        *self == SOURCESEL_A::PDM
381    }
382}
383#[doc = "Field `SOURCESEL` writer - Source Select"]
384pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
385impl<'a> SOURCESEL_W<'a> {
386    #[doc = "No source selected"]
387    #[inline(always)]
388    pub fn none(self) -> &'a mut W {
389        self.variant(SOURCESEL_A::NONE)
390    }
391    #[doc = "Peripheral Reflex System"]
392    #[inline(always)]
393    pub fn prsl(self) -> &'a mut W {
394        self.variant(SOURCESEL_A::PRSL)
395    }
396    #[doc = "Peripheral Reflex System"]
397    #[inline(always)]
398    pub fn prs(self) -> &'a mut W {
399        self.variant(SOURCESEL_A::PRS)
400    }
401    #[doc = "Analog Comparator 0"]
402    #[inline(always)]
403    pub fn acmp0(self) -> &'a mut W {
404        self.variant(SOURCESEL_A::ACMP0)
405    }
406    #[doc = "Analog Comparator 1"]
407    #[inline(always)]
408    pub fn acmp1(self) -> &'a mut W {
409        self.variant(SOURCESEL_A::ACMP1)
410    }
411    #[doc = "Analog to Digital Converter 0"]
412    #[inline(always)]
413    pub fn adc0(self) -> &'a mut W {
414        self.variant(SOURCESEL_A::ADC0)
415    }
416    #[doc = "Real-Time Counter"]
417    #[inline(always)]
418    pub fn rtc(self) -> &'a mut W {
419        self.variant(SOURCESEL_A::RTC)
420    }
421    #[doc = "Real-Time Counter and Calendar"]
422    #[inline(always)]
423    pub fn rtcc(self) -> &'a mut W {
424        self.variant(SOURCESEL_A::RTCC)
425    }
426    #[doc = "General purpose Input/Output"]
427    #[inline(always)]
428    pub fn gpiol(self) -> &'a mut W {
429        self.variant(SOURCESEL_A::GPIOL)
430    }
431    #[doc = "General purpose Input/Output"]
432    #[inline(always)]
433    pub fn gpioh(self) -> &'a mut W {
434        self.variant(SOURCESEL_A::GPIOH)
435    }
436    #[doc = "Low Energy Timer 0"]
437    #[inline(always)]
438    pub fn letimer0(self) -> &'a mut W {
439        self.variant(SOURCESEL_A::LETIMER0)
440    }
441    #[doc = "Low Energy Timer 1"]
442    #[inline(always)]
443    pub fn letimer1(self) -> &'a mut W {
444        self.variant(SOURCESEL_A::LETIMER1)
445    }
446    #[doc = "Pulse Counter 0"]
447    #[inline(always)]
448    pub fn pcnt0(self) -> &'a mut W {
449        self.variant(SOURCESEL_A::PCNT0)
450    }
451    #[doc = "Pulse Counter 1"]
452    #[inline(always)]
453    pub fn pcnt1(self) -> &'a mut W {
454        self.variant(SOURCESEL_A::PCNT1)
455    }
456    #[doc = "Pulse Counter 2"]
457    #[inline(always)]
458    pub fn pcnt2(self) -> &'a mut W {
459        self.variant(SOURCESEL_A::PCNT2)
460    }
461    #[doc = "CRYOTIMER"]
462    #[inline(always)]
463    pub fn cryotimer(self) -> &'a mut W {
464        self.variant(SOURCESEL_A::CRYOTIMER)
465    }
466    #[doc = "Clock Management Unit"]
467    #[inline(always)]
468    pub fn cmu(self) -> &'a mut W {
469        self.variant(SOURCESEL_A::CMU)
470    }
471    #[doc = "Digital to Analog Converter 0"]
472    #[inline(always)]
473    pub fn vdac0(self) -> &'a mut W {
474        self.variant(SOURCESEL_A::VDAC0)
475    }
476    #[doc = "Low Energy Sensor Interface"]
477    #[inline(always)]
478    pub fn lesensel(self) -> &'a mut W {
479        self.variant(SOURCESEL_A::LESENSEL)
480    }
481    #[doc = "Low Energy Sensor Interface"]
482    #[inline(always)]
483    pub fn lesenseh(self) -> &'a mut W {
484        self.variant(SOURCESEL_A::LESENSEH)
485    }
486    #[doc = "Low Energy Sensor Interface"]
487    #[inline(always)]
488    pub fn lesensed(self) -> &'a mut W {
489        self.variant(SOURCESEL_A::LESENSED)
490    }
491    #[doc = "Low Energy Sensor Interface"]
492    #[inline(always)]
493    pub fn lesense(self) -> &'a mut W {
494        self.variant(SOURCESEL_A::LESENSE)
495    }
496    #[doc = "Analog Comparator 2"]
497    #[inline(always)]
498    pub fn acmp2(self) -> &'a mut W {
499        self.variant(SOURCESEL_A::ACMP2)
500    }
501    #[doc = "Analog to Digital Converter 0"]
502    #[inline(always)]
503    pub fn adc1(self) -> &'a mut W {
504        self.variant(SOURCESEL_A::ADC1)
505    }
506    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
507    #[inline(always)]
508    pub fn usart0(self) -> &'a mut W {
509        self.variant(SOURCESEL_A::USART0)
510    }
511    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
512    #[inline(always)]
513    pub fn usart1(self) -> &'a mut W {
514        self.variant(SOURCESEL_A::USART1)
515    }
516    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
517    #[inline(always)]
518    pub fn usart2(self) -> &'a mut W {
519        self.variant(SOURCESEL_A::USART2)
520    }
521    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
522    #[inline(always)]
523    pub fn usart3(self) -> &'a mut W {
524        self.variant(SOURCESEL_A::USART3)
525    }
526    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
527    #[inline(always)]
528    pub fn usart4(self) -> &'a mut W {
529        self.variant(SOURCESEL_A::USART4)
530    }
531    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
532    #[inline(always)]
533    pub fn uart0(self) -> &'a mut W {
534        self.variant(SOURCESEL_A::UART0)
535    }
536    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
537    #[inline(always)]
538    pub fn uart1(self) -> &'a mut W {
539        self.variant(SOURCESEL_A::UART1)
540    }
541    #[doc = "Timer 0"]
542    #[inline(always)]
543    pub fn timer0(self) -> &'a mut W {
544        self.variant(SOURCESEL_A::TIMER0)
545    }
546    #[doc = "Timer 1"]
547    #[inline(always)]
548    pub fn timer1(self) -> &'a mut W {
549        self.variant(SOURCESEL_A::TIMER1)
550    }
551    #[doc = "Timer 2"]
552    #[inline(always)]
553    pub fn timer2(self) -> &'a mut W {
554        self.variant(SOURCESEL_A::TIMER2)
555    }
556    #[doc = "Universal Serial Bus Interface"]
557    #[inline(always)]
558    pub fn usb(self) -> &'a mut W {
559        self.variant(SOURCESEL_A::USB)
560    }
561    #[doc = "`1000011`"]
562    #[inline(always)]
563    pub fn cm4(self) -> &'a mut W {
564        self.variant(SOURCESEL_A::CM4)
565    }
566    #[doc = "Timer 3"]
567    #[inline(always)]
568    pub fn timer3(self) -> &'a mut W {
569        self.variant(SOURCESEL_A::TIMER3)
570    }
571    #[doc = "Wide Timer 0"]
572    #[inline(always)]
573    pub fn wtimer0(self) -> &'a mut W {
574        self.variant(SOURCESEL_A::WTIMER0)
575    }
576    #[doc = "Wide Timer 0"]
577    #[inline(always)]
578    pub fn wtimer1(self) -> &'a mut W {
579        self.variant(SOURCESEL_A::WTIMER1)
580    }
581    #[doc = "PDM Interface"]
582    #[inline(always)]
583    pub fn pdm(self) -> &'a mut W {
584        self.variant(SOURCESEL_A::PDM)
585    }
586}
587#[doc = "Edge Detect Select\n\nValue on reset: 0"]
588#[derive(Clone, Copy, Debug, PartialEq)]
589#[repr(u8)]
590pub enum EDSEL_A {
591    #[doc = "0: Signal is left as it is"]
592    OFF = 0,
593    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
594    POSEDGE = 1,
595    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
596    NEGEDGE = 2,
597    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
598    BOTHEDGES = 3,
599}
600impl From<EDSEL_A> for u8 {
601    #[inline(always)]
602    fn from(variant: EDSEL_A) -> Self {
603        variant as _
604    }
605}
606#[doc = "Field `EDSEL` reader - Edge Detect Select"]
607pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
608impl EDSEL_R {
609    #[doc = "Get enumerated values variant"]
610    #[inline(always)]
611    pub fn variant(&self) -> EDSEL_A {
612        match self.bits {
613            0 => EDSEL_A::OFF,
614            1 => EDSEL_A::POSEDGE,
615            2 => EDSEL_A::NEGEDGE,
616            3 => EDSEL_A::BOTHEDGES,
617            _ => unreachable!(),
618        }
619    }
620    #[doc = "Checks if the value of the field is `OFF`"]
621    #[inline(always)]
622    pub fn is_off(&self) -> bool {
623        *self == EDSEL_A::OFF
624    }
625    #[doc = "Checks if the value of the field is `POSEDGE`"]
626    #[inline(always)]
627    pub fn is_posedge(&self) -> bool {
628        *self == EDSEL_A::POSEDGE
629    }
630    #[doc = "Checks if the value of the field is `NEGEDGE`"]
631    #[inline(always)]
632    pub fn is_negedge(&self) -> bool {
633        *self == EDSEL_A::NEGEDGE
634    }
635    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
636    #[inline(always)]
637    pub fn is_bothedges(&self) -> bool {
638        *self == EDSEL_A::BOTHEDGES
639    }
640}
641#[doc = "Field `EDSEL` writer - Edge Detect Select"]
642pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH4_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
643impl<'a> EDSEL_W<'a> {
644    #[doc = "Signal is left as it is"]
645    #[inline(always)]
646    pub fn off(self) -> &'a mut W {
647        self.variant(EDSEL_A::OFF)
648    }
649    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
650    #[inline(always)]
651    pub fn posedge(self) -> &'a mut W {
652        self.variant(EDSEL_A::POSEDGE)
653    }
654    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
655    #[inline(always)]
656    pub fn negedge(self) -> &'a mut W {
657        self.variant(EDSEL_A::NEGEDGE)
658    }
659    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
660    #[inline(always)]
661    pub fn bothedges(self) -> &'a mut W {
662        self.variant(EDSEL_A::BOTHEDGES)
663    }
664}
665#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
666pub type STRETCH_R = crate::BitReader<bool>;
667#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
668pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 25>;
669#[doc = "Field `INV` reader - Invert Channel"]
670pub type INV_R = crate::BitReader<bool>;
671#[doc = "Field `INV` writer - Invert Channel"]
672pub type INV_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 26>;
673#[doc = "Field `ORPREV` reader - Or Previous"]
674pub type ORPREV_R = crate::BitReader<bool>;
675#[doc = "Field `ORPREV` writer - Or Previous"]
676pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 27>;
677#[doc = "Field `ANDNEXT` reader - And Next"]
678pub type ANDNEXT_R = crate::BitReader<bool>;
679#[doc = "Field `ANDNEXT` writer - And Next"]
680pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 28>;
681#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
682pub type ASYNC_R = crate::BitReader<bool>;
683#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
684pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH4_CTRL_SPEC, bool, 30>;
685impl R {
686    #[doc = "Bits 0:2 - Signal Select"]
687    #[inline(always)]
688    pub fn sigsel(&self) -> SIGSEL_R {
689        SIGSEL_R::new((self.bits & 7) as u8)
690    }
691    #[doc = "Bits 8:14 - Source Select"]
692    #[inline(always)]
693    pub fn sourcesel(&self) -> SOURCESEL_R {
694        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
695    }
696    #[doc = "Bits 20:21 - Edge Detect Select"]
697    #[inline(always)]
698    pub fn edsel(&self) -> EDSEL_R {
699        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
700    }
701    #[doc = "Bit 25 - Stretch Channel Output"]
702    #[inline(always)]
703    pub fn stretch(&self) -> STRETCH_R {
704        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
705    }
706    #[doc = "Bit 26 - Invert Channel"]
707    #[inline(always)]
708    pub fn inv(&self) -> INV_R {
709        INV_R::new(((self.bits >> 26) & 1) != 0)
710    }
711    #[doc = "Bit 27 - Or Previous"]
712    #[inline(always)]
713    pub fn orprev(&self) -> ORPREV_R {
714        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
715    }
716    #[doc = "Bit 28 - And Next"]
717    #[inline(always)]
718    pub fn andnext(&self) -> ANDNEXT_R {
719        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
720    }
721    #[doc = "Bit 30 - Asynchronous Reflex"]
722    #[inline(always)]
723    pub fn async_(&self) -> ASYNC_R {
724        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
725    }
726}
727impl W {
728    #[doc = "Bits 0:2 - Signal Select"]
729    #[inline(always)]
730    pub fn sigsel(&mut self) -> SIGSEL_W {
731        SIGSEL_W::new(self)
732    }
733    #[doc = "Bits 8:14 - Source Select"]
734    #[inline(always)]
735    pub fn sourcesel(&mut self) -> SOURCESEL_W {
736        SOURCESEL_W::new(self)
737    }
738    #[doc = "Bits 20:21 - Edge Detect Select"]
739    #[inline(always)]
740    pub fn edsel(&mut self) -> EDSEL_W {
741        EDSEL_W::new(self)
742    }
743    #[doc = "Bit 25 - Stretch Channel Output"]
744    #[inline(always)]
745    pub fn stretch(&mut self) -> STRETCH_W {
746        STRETCH_W::new(self)
747    }
748    #[doc = "Bit 26 - Invert Channel"]
749    #[inline(always)]
750    pub fn inv(&mut self) -> INV_W {
751        INV_W::new(self)
752    }
753    #[doc = "Bit 27 - Or Previous"]
754    #[inline(always)]
755    pub fn orprev(&mut self) -> ORPREV_W {
756        ORPREV_W::new(self)
757    }
758    #[doc = "Bit 28 - And Next"]
759    #[inline(always)]
760    pub fn andnext(&mut self) -> ANDNEXT_W {
761        ANDNEXT_W::new(self)
762    }
763    #[doc = "Bit 30 - Asynchronous Reflex"]
764    #[inline(always)]
765    pub fn async_(&mut self) -> ASYNC_W {
766        ASYNC_W::new(self)
767    }
768    #[doc = "Writes raw bits to the register."]
769    #[inline(always)]
770    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
771        self.0.bits(bits);
772        self
773    }
774}
775#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch4_ctrl](index.html) module"]
776pub struct CH4_CTRL_SPEC;
777impl crate::RegisterSpec for CH4_CTRL_SPEC {
778    type Ux = u32;
779}
780#[doc = "`read()` method returns [ch4_ctrl::R](R) reader structure"]
781impl crate::Readable for CH4_CTRL_SPEC {
782    type Reader = R;
783}
784#[doc = "`write(|w| ..)` method takes [ch4_ctrl::W](W) writer structure"]
785impl crate::Writable for CH4_CTRL_SPEC {
786    type Writer = W;
787}
788#[doc = "`reset()` method sets CH4_CTRL to value 0"]
789impl crate::Resettable for CH4_CTRL_SPEC {
790    #[inline(always)]
791    fn reset_value() -> Self::Ux {
792        0
793    }
794}
efm32gg12b810_pac/prs/ch4_ctrl.rs

efm32gg12b810_pac/prs/
ch4_ctrl.rs
