efm32gg12b810_pac/cmu/
status.rs

1#[doc = "Register `STATUS` reader"]
2pub struct R(crate::R<STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `HFRCOENS` reader - HFRCO Enable Status"]
17pub type HFRCOENS_R = crate::BitReader<bool>;
18#[doc = "Field `HFRCORDY` reader - HFRCO Ready"]
19pub type HFRCORDY_R = crate::BitReader<bool>;
20#[doc = "Field `HFXOENS` reader - HFXO Enable Status"]
21pub type HFXOENS_R = crate::BitReader<bool>;
22#[doc = "Field `HFXORDY` reader - HFXO Ready"]
23pub type HFXORDY_R = crate::BitReader<bool>;
24#[doc = "Field `AUXHFRCOENS` reader - AUXHFRCO Enable Status"]
25pub type AUXHFRCOENS_R = crate::BitReader<bool>;
26#[doc = "Field `AUXHFRCORDY` reader - AUXHFRCO Ready"]
27pub type AUXHFRCORDY_R = crate::BitReader<bool>;
28#[doc = "Field `LFRCOENS` reader - LFRCO Enable Status"]
29pub type LFRCOENS_R = crate::BitReader<bool>;
30#[doc = "Field `LFRCORDY` reader - LFRCO Ready"]
31pub type LFRCORDY_R = crate::BitReader<bool>;
32#[doc = "Field `LFXOENS` reader - LFXO Enable Status"]
33pub type LFXOENS_R = crate::BitReader<bool>;
34#[doc = "Field `LFXORDY` reader - LFXO Ready"]
35pub type LFXORDY_R = crate::BitReader<bool>;
36#[doc = "Field `USHFRCOENS` reader - USHFRCO Enable Status"]
37pub type USHFRCOENS_R = crate::BitReader<bool>;
38#[doc = "Field `USHFRCORDY` reader - USHFRCO Ready"]
39pub type USHFRCORDY_R = crate::BitReader<bool>;
40#[doc = "Field `DPLLENS` reader - DPLL Enable Status"]
41pub type DPLLENS_R = crate::BitReader<bool>;
42#[doc = "Field `DPLLRDY` reader - DPLL Ready"]
43pub type DPLLRDY_R = crate::BitReader<bool>;
44#[doc = "Field `CALRDY` reader - Calibration Ready"]
45pub type CALRDY_R = crate::BitReader<bool>;
46#[doc = "Field `SDIOCLKENS` reader - SDIO Clock Enabled Status"]
47pub type SDIOCLKENS_R = crate::BitReader<bool>;
48#[doc = "Field `QSPI0CLKENS` reader - QSPI0 Clock Enabled Status"]
49pub type QSPI0CLKENS_R = crate::BitReader<bool>;
50#[doc = "Field `PDMCLKENS` reader - PDM Clock Enabled Status"]
51pub type PDMCLKENS_R = crate::BitReader<bool>;
52#[doc = "Field `HFXOPEAKDETRDY` reader - HFXO Peak Detection Ready"]
53pub type HFXOPEAKDETRDY_R = crate::BitReader<bool>;
54#[doc = "Field `HFXOAMPLOW` reader - HFXO Amplitude Tuning Value Too Low"]
55pub type HFXOAMPLOW_R = crate::BitReader<bool>;
56#[doc = "Field `LFXOPHASE` reader - LFXO Clock Phase"]
57pub type LFXOPHASE_R = crate::BitReader<bool>;
58#[doc = "Field `LFRCOPHASE` reader - LFRCO Clock Phase"]
59pub type LFRCOPHASE_R = crate::BitReader<bool>;
60#[doc = "Field `ULFRCOPHASE` reader - ULFRCO Clock Phase"]
61pub type ULFRCOPHASE_R = crate::BitReader<bool>;
62impl R {
63    #[doc = "Bit 0 - HFRCO Enable Status"]
64    #[inline(always)]
65    pub fn hfrcoens(&self) -> HFRCOENS_R {
66        HFRCOENS_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bit 1 - HFRCO Ready"]
69    #[inline(always)]
70    pub fn hfrcordy(&self) -> HFRCORDY_R {
71        HFRCORDY_R::new(((self.bits >> 1) & 1) != 0)
72    }
73    #[doc = "Bit 2 - HFXO Enable Status"]
74    #[inline(always)]
75    pub fn hfxoens(&self) -> HFXOENS_R {
76        HFXOENS_R::new(((self.bits >> 2) & 1) != 0)
77    }
78    #[doc = "Bit 3 - HFXO Ready"]
79    #[inline(always)]
80    pub fn hfxordy(&self) -> HFXORDY_R {
81        HFXORDY_R::new(((self.bits >> 3) & 1) != 0)
82    }
83    #[doc = "Bit 4 - AUXHFRCO Enable Status"]
84    #[inline(always)]
85    pub fn auxhfrcoens(&self) -> AUXHFRCOENS_R {
86        AUXHFRCOENS_R::new(((self.bits >> 4) & 1) != 0)
87    }
88    #[doc = "Bit 5 - AUXHFRCO Ready"]
89    #[inline(always)]
90    pub fn auxhfrcordy(&self) -> AUXHFRCORDY_R {
91        AUXHFRCORDY_R::new(((self.bits >> 5) & 1) != 0)
92    }
93    #[doc = "Bit 6 - LFRCO Enable Status"]
94    #[inline(always)]
95    pub fn lfrcoens(&self) -> LFRCOENS_R {
96        LFRCOENS_R::new(((self.bits >> 6) & 1) != 0)
97    }
98    #[doc = "Bit 7 - LFRCO Ready"]
99    #[inline(always)]
100    pub fn lfrcordy(&self) -> LFRCORDY_R {
101        LFRCORDY_R::new(((self.bits >> 7) & 1) != 0)
102    }
103    #[doc = "Bit 8 - LFXO Enable Status"]
104    #[inline(always)]
105    pub fn lfxoens(&self) -> LFXOENS_R {
106        LFXOENS_R::new(((self.bits >> 8) & 1) != 0)
107    }
108    #[doc = "Bit 9 - LFXO Ready"]
109    #[inline(always)]
110    pub fn lfxordy(&self) -> LFXORDY_R {
111        LFXORDY_R::new(((self.bits >> 9) & 1) != 0)
112    }
113    #[doc = "Bit 10 - USHFRCO Enable Status"]
114    #[inline(always)]
115    pub fn ushfrcoens(&self) -> USHFRCOENS_R {
116        USHFRCOENS_R::new(((self.bits >> 10) & 1) != 0)
117    }
118    #[doc = "Bit 11 - USHFRCO Ready"]
119    #[inline(always)]
120    pub fn ushfrcordy(&self) -> USHFRCORDY_R {
121        USHFRCORDY_R::new(((self.bits >> 11) & 1) != 0)
122    }
123    #[doc = "Bit 12 - DPLL Enable Status"]
124    #[inline(always)]
125    pub fn dpllens(&self) -> DPLLENS_R {
126        DPLLENS_R::new(((self.bits >> 12) & 1) != 0)
127    }
128    #[doc = "Bit 13 - DPLL Ready"]
129    #[inline(always)]
130    pub fn dpllrdy(&self) -> DPLLRDY_R {
131        DPLLRDY_R::new(((self.bits >> 13) & 1) != 0)
132    }
133    #[doc = "Bit 16 - Calibration Ready"]
134    #[inline(always)]
135    pub fn calrdy(&self) -> CALRDY_R {
136        CALRDY_R::new(((self.bits >> 16) & 1) != 0)
137    }
138    #[doc = "Bit 17 - SDIO Clock Enabled Status"]
139    #[inline(always)]
140    pub fn sdioclkens(&self) -> SDIOCLKENS_R {
141        SDIOCLKENS_R::new(((self.bits >> 17) & 1) != 0)
142    }
143    #[doc = "Bit 18 - QSPI0 Clock Enabled Status"]
144    #[inline(always)]
145    pub fn qspi0clkens(&self) -> QSPI0CLKENS_R {
146        QSPI0CLKENS_R::new(((self.bits >> 18) & 1) != 0)
147    }
148    #[doc = "Bit 19 - PDM Clock Enabled Status"]
149    #[inline(always)]
150    pub fn pdmclkens(&self) -> PDMCLKENS_R {
151        PDMCLKENS_R::new(((self.bits >> 19) & 1) != 0)
152    }
153    #[doc = "Bit 22 - HFXO Peak Detection Ready"]
154    #[inline(always)]
155    pub fn hfxopeakdetrdy(&self) -> HFXOPEAKDETRDY_R {
156        HFXOPEAKDETRDY_R::new(((self.bits >> 22) & 1) != 0)
157    }
158    #[doc = "Bit 25 - HFXO Amplitude Tuning Value Too Low"]
159    #[inline(always)]
160    pub fn hfxoamplow(&self) -> HFXOAMPLOW_R {
161        HFXOAMPLOW_R::new(((self.bits >> 25) & 1) != 0)
162    }
163    #[doc = "Bit 27 - LFXO Clock Phase"]
164    #[inline(always)]
165    pub fn lfxophase(&self) -> LFXOPHASE_R {
166        LFXOPHASE_R::new(((self.bits >> 27) & 1) != 0)
167    }
168    #[doc = "Bit 28 - LFRCO Clock Phase"]
169    #[inline(always)]
170    pub fn lfrcophase(&self) -> LFRCOPHASE_R {
171        LFRCOPHASE_R::new(((self.bits >> 28) & 1) != 0)
172    }
173    #[doc = "Bit 29 - ULFRCO Clock Phase"]
174    #[inline(always)]
175    pub fn ulfrcophase(&self) -> ULFRCOPHASE_R {
176        ULFRCOPHASE_R::new(((self.bits >> 29) & 1) != 0)
177    }
178}
179#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
180pub struct STATUS_SPEC;
181impl crate::RegisterSpec for STATUS_SPEC {
182    type Ux = u32;
183}
184#[doc = "`read()` method returns [status::R](R) reader structure"]
185impl crate::Readable for STATUS_SPEC {
186    type Reader = R;
187}
188#[doc = "`reset()` method sets STATUS to value 0x0001_0003"]
189impl crate::Resettable for STATUS_SPEC {
190    #[inline(always)]
191    fn reset_value() -> Self::Ux {
192        0x0001_0003
193    }
194}
efm32gg12b810_pac/cmu/status.rs

efm32gg12b810_pac/cmu/
status.rs
