efm32gg12b810_pac/adc0/
singlectrl.rs

1#[doc = "Register `SINGLECTRL` reader"]
2pub struct R(crate::R<SINGLECTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SINGLECTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SINGLECTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SINGLECTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SINGLECTRL` writer"]
17pub struct W(crate::W<SINGLECTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SINGLECTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SINGLECTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SINGLECTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `REP` reader - Single Channel Repetitive Mode"]
38pub type REP_R = crate::BitReader<bool>;
39#[doc = "Field `REP` writer - Single Channel Repetitive Mode"]
40pub type REP_W<'a> = crate::BitWriter<'a, u32, SINGLECTRL_SPEC, bool, 0>;
41#[doc = "Field `DIFF` reader - Single Channel Differential Mode"]
42pub type DIFF_R = crate::BitReader<bool>;
43#[doc = "Field `DIFF` writer - Single Channel Differential Mode"]
44pub type DIFF_W<'a> = crate::BitWriter<'a, u32, SINGLECTRL_SPEC, bool, 1>;
45#[doc = "Field `ADJ` reader - Single Channel Result Adjustment"]
46pub type ADJ_R = crate::BitReader<bool>;
47#[doc = "Field `ADJ` writer - Single Channel Result Adjustment"]
48pub type ADJ_W<'a> = crate::BitWriter<'a, u32, SINGLECTRL_SPEC, bool, 2>;
49#[doc = "Single Channel Resolution Select\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum RES_A {
53    #[doc = "0: 12-bit resolution."]
54    _12BIT = 0,
55    #[doc = "1: 8-bit resolution."]
56    _8BIT = 1,
57    #[doc = "2: 6-bit resolution."]
58    _6BIT = 2,
59    #[doc = "3: Oversampling enabled. Oversampling rate is set in OVSRSEL."]
60    OVS = 3,
61}
62impl From<RES_A> for u8 {
63    #[inline(always)]
64    fn from(variant: RES_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `RES` reader - Single Channel Resolution Select"]
69pub type RES_R = crate::FieldReader<u8, RES_A>;
70impl RES_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> RES_A {
74        match self.bits {
75            0 => RES_A::_12BIT,
76            1 => RES_A::_8BIT,
77            2 => RES_A::_6BIT,
78            3 => RES_A::OVS,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `_12BIT`"]
83    #[inline(always)]
84    pub fn is_12bit(&self) -> bool {
85        *self == RES_A::_12BIT
86    }
87    #[doc = "Checks if the value of the field is `_8BIT`"]
88    #[inline(always)]
89    pub fn is_8bit(&self) -> bool {
90        *self == RES_A::_8BIT
91    }
92    #[doc = "Checks if the value of the field is `_6BIT`"]
93    #[inline(always)]
94    pub fn is_6bit(&self) -> bool {
95        *self == RES_A::_6BIT
96    }
97    #[doc = "Checks if the value of the field is `OVS`"]
98    #[inline(always)]
99    pub fn is_ovs(&self) -> bool {
100        *self == RES_A::OVS
101    }
102}
103#[doc = "Field `RES` writer - Single Channel Resolution Select"]
104pub type RES_W<'a> = crate::FieldWriterSafe<'a, u32, SINGLECTRL_SPEC, u8, RES_A, 2, 3>;
105impl<'a> RES_W<'a> {
106    #[doc = "12-bit resolution."]
107    #[inline(always)]
108    pub fn _12bit(self) -> &'a mut W {
109        self.variant(RES_A::_12BIT)
110    }
111    #[doc = "8-bit resolution."]
112    #[inline(always)]
113    pub fn _8bit(self) -> &'a mut W {
114        self.variant(RES_A::_8BIT)
115    }
116    #[doc = "6-bit resolution."]
117    #[inline(always)]
118    pub fn _6bit(self) -> &'a mut W {
119        self.variant(RES_A::_6BIT)
120    }
121    #[doc = "Oversampling enabled. Oversampling rate is set in OVSRSEL."]
122    #[inline(always)]
123    pub fn ovs(self) -> &'a mut W {
124        self.variant(RES_A::OVS)
125    }
126}
127#[doc = "Single Channel Reference Selection\n\nValue on reset: 0"]
128#[derive(Clone, Copy, Debug, PartialEq)]
129#[repr(u8)]
130pub enum REF_A {
131    #[doc = "0: VFS = 1.25V with internal VBGR reference"]
132    _1V25 = 0,
133    #[doc = "1: VFS = 2.5V with internal VBGR reference"]
134    _2V5 = 1,
135    #[doc = "2: VFS = AVDD with AVDD as reference source"]
136    VDD = 2,
137    #[doc = "3: VFS = 5V with internal VBGR reference"]
138    _5V = 3,
139    #[doc = "4: Single ended external reference"]
140    EXTSINGLE = 4,
141    #[doc = "5: Differential external reference, 2x"]
142    _2XEXTDIFF = 5,
143    #[doc = "6: VFS = 2xAVDD with AVDD as the reference source"]
144    _2XVDD = 6,
145    #[doc = "7: Use SINGLECTRLX to configure reference"]
146    CONF = 7,
147}
148impl From<REF_A> for u8 {
149    #[inline(always)]
150    fn from(variant: REF_A) -> Self {
151        variant as _
152    }
153}
154#[doc = "Field `REF` reader - Single Channel Reference Selection"]
155pub type REF_R = crate::FieldReader<u8, REF_A>;
156impl REF_R {
157    #[doc = "Get enumerated values variant"]
158    #[inline(always)]
159    pub fn variant(&self) -> REF_A {
160        match self.bits {
161            0 => REF_A::_1V25,
162            1 => REF_A::_2V5,
163            2 => REF_A::VDD,
164            3 => REF_A::_5V,
165            4 => REF_A::EXTSINGLE,
166            5 => REF_A::_2XEXTDIFF,
167            6 => REF_A::_2XVDD,
168            7 => REF_A::CONF,
169            _ => unreachable!(),
170        }
171    }
172    #[doc = "Checks if the value of the field is `_1V25`"]
173    #[inline(always)]
174    pub fn is_1v25(&self) -> bool {
175        *self == REF_A::_1V25
176    }
177    #[doc = "Checks if the value of the field is `_2V5`"]
178    #[inline(always)]
179    pub fn is_2v5(&self) -> bool {
180        *self == REF_A::_2V5
181    }
182    #[doc = "Checks if the value of the field is `VDD`"]
183    #[inline(always)]
184    pub fn is_vdd(&self) -> bool {
185        *self == REF_A::VDD
186    }
187    #[doc = "Checks if the value of the field is `_5V`"]
188    #[inline(always)]
189    pub fn is_5v(&self) -> bool {
190        *self == REF_A::_5V
191    }
192    #[doc = "Checks if the value of the field is `EXTSINGLE`"]
193    #[inline(always)]
194    pub fn is_extsingle(&self) -> bool {
195        *self == REF_A::EXTSINGLE
196    }
197    #[doc = "Checks if the value of the field is `_2XEXTDIFF`"]
198    #[inline(always)]
199    pub fn is_2xextdiff(&self) -> bool {
200        *self == REF_A::_2XEXTDIFF
201    }
202    #[doc = "Checks if the value of the field is `_2XVDD`"]
203    #[inline(always)]
204    pub fn is_2xvdd(&self) -> bool {
205        *self == REF_A::_2XVDD
206    }
207    #[doc = "Checks if the value of the field is `CONF`"]
208    #[inline(always)]
209    pub fn is_conf(&self) -> bool {
210        *self == REF_A::CONF
211    }
212}
213#[doc = "Field `REF` writer - Single Channel Reference Selection"]
214pub type REF_W<'a> = crate::FieldWriterSafe<'a, u32, SINGLECTRL_SPEC, u8, REF_A, 3, 5>;
215impl<'a> REF_W<'a> {
216    #[doc = "VFS = 1.25V with internal VBGR reference"]
217    #[inline(always)]
218    pub fn _1v25(self) -> &'a mut W {
219        self.variant(REF_A::_1V25)
220    }
221    #[doc = "VFS = 2.5V with internal VBGR reference"]
222    #[inline(always)]
223    pub fn _2v5(self) -> &'a mut W {
224        self.variant(REF_A::_2V5)
225    }
226    #[doc = "VFS = AVDD with AVDD as reference source"]
227    #[inline(always)]
228    pub fn vdd(self) -> &'a mut W {
229        self.variant(REF_A::VDD)
230    }
231    #[doc = "VFS = 5V with internal VBGR reference"]
232    #[inline(always)]
233    pub fn _5v(self) -> &'a mut W {
234        self.variant(REF_A::_5V)
235    }
236    #[doc = "Single ended external reference"]
237    #[inline(always)]
238    pub fn extsingle(self) -> &'a mut W {
239        self.variant(REF_A::EXTSINGLE)
240    }
241    #[doc = "Differential external reference, 2x"]
242    #[inline(always)]
243    pub fn _2xextdiff(self) -> &'a mut W {
244        self.variant(REF_A::_2XEXTDIFF)
245    }
246    #[doc = "VFS = 2xAVDD with AVDD as the reference source"]
247    #[inline(always)]
248    pub fn _2xvdd(self) -> &'a mut W {
249        self.variant(REF_A::_2XVDD)
250    }
251    #[doc = "Use SINGLECTRLX to configure reference"]
252    #[inline(always)]
253    pub fn conf(self) -> &'a mut W {
254        self.variant(REF_A::CONF)
255    }
256}
257#[doc = "Field `POSSEL` reader - Single Channel Positive Input Selection"]
258pub type POSSEL_R = crate::FieldReader<u8, u8>;
259#[doc = "Field `POSSEL` writer - Single Channel Positive Input Selection"]
260pub type POSSEL_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRL_SPEC, u8, u8, 8, 8>;
261#[doc = "Field `NEGSEL` reader - Single Channel Negative Input Selection"]
262pub type NEGSEL_R = crate::FieldReader<u8, u8>;
263#[doc = "Field `NEGSEL` writer - Single Channel Negative Input Selection"]
264pub type NEGSEL_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRL_SPEC, u8, u8, 8, 16>;
265#[doc = "Single Channel Acquisition Time\n\nValue on reset: 0"]
266#[derive(Clone, Copy, Debug, PartialEq)]
267#[repr(u8)]
268pub enum AT_A {
269    #[doc = "0: 1 conversion clock cycle acquisition time for single channel"]
270    _1CYCLE = 0,
271    #[doc = "1: 2 conversion clock cycles acquisition time for single channel"]
272    _2CYCLES = 1,
273    #[doc = "2: 3 conversion clock cycles acquisition time for single channel"]
274    _3CYCLES = 2,
275    #[doc = "3: 4 conversion clock cycles acquisition time for single channel"]
276    _4CYCLES = 3,
277    #[doc = "4: 8 conversion clock cycles acquisition time for single channel"]
278    _8CYCLES = 4,
279    #[doc = "5: 16 conversion clock cycles acquisition time for single channel"]
280    _16CYCLES = 5,
281    #[doc = "6: 32 conversion clock cycles acquisition time for single channel"]
282    _32CYCLES = 6,
283    #[doc = "7: 64 conversion clock cycles acquisition time for single channel"]
284    _64CYCLES = 7,
285    #[doc = "8: 128 conversion clock cycles acquisition time for single channel"]
286    _128CYCLES = 8,
287    #[doc = "9: 256 conversion clock cycles acquisition time for single channel"]
288    _256CYCLES = 9,
289}
290impl From<AT_A> for u8 {
291    #[inline(always)]
292    fn from(variant: AT_A) -> Self {
293        variant as _
294    }
295}
296#[doc = "Field `AT` reader - Single Channel Acquisition Time"]
297pub type AT_R = crate::FieldReader<u8, AT_A>;
298impl AT_R {
299    #[doc = "Get enumerated values variant"]
300    #[inline(always)]
301    pub fn variant(&self) -> Option<AT_A> {
302        match self.bits {
303            0 => Some(AT_A::_1CYCLE),
304            1 => Some(AT_A::_2CYCLES),
305            2 => Some(AT_A::_3CYCLES),
306            3 => Some(AT_A::_4CYCLES),
307            4 => Some(AT_A::_8CYCLES),
308            5 => Some(AT_A::_16CYCLES),
309            6 => Some(AT_A::_32CYCLES),
310            7 => Some(AT_A::_64CYCLES),
311            8 => Some(AT_A::_128CYCLES),
312            9 => Some(AT_A::_256CYCLES),
313            _ => None,
314        }
315    }
316    #[doc = "Checks if the value of the field is `_1CYCLE`"]
317    #[inline(always)]
318    pub fn is_1cycle(&self) -> bool {
319        *self == AT_A::_1CYCLE
320    }
321    #[doc = "Checks if the value of the field is `_2CYCLES`"]
322    #[inline(always)]
323    pub fn is_2cycles(&self) -> bool {
324        *self == AT_A::_2CYCLES
325    }
326    #[doc = "Checks if the value of the field is `_3CYCLES`"]
327    #[inline(always)]
328    pub fn is_3cycles(&self) -> bool {
329        *self == AT_A::_3CYCLES
330    }
331    #[doc = "Checks if the value of the field is `_4CYCLES`"]
332    #[inline(always)]
333    pub fn is_4cycles(&self) -> bool {
334        *self == AT_A::_4CYCLES
335    }
336    #[doc = "Checks if the value of the field is `_8CYCLES`"]
337    #[inline(always)]
338    pub fn is_8cycles(&self) -> bool {
339        *self == AT_A::_8CYCLES
340    }
341    #[doc = "Checks if the value of the field is `_16CYCLES`"]
342    #[inline(always)]
343    pub fn is_16cycles(&self) -> bool {
344        *self == AT_A::_16CYCLES
345    }
346    #[doc = "Checks if the value of the field is `_32CYCLES`"]
347    #[inline(always)]
348    pub fn is_32cycles(&self) -> bool {
349        *self == AT_A::_32CYCLES
350    }
351    #[doc = "Checks if the value of the field is `_64CYCLES`"]
352    #[inline(always)]
353    pub fn is_64cycles(&self) -> bool {
354        *self == AT_A::_64CYCLES
355    }
356    #[doc = "Checks if the value of the field is `_128CYCLES`"]
357    #[inline(always)]
358    pub fn is_128cycles(&self) -> bool {
359        *self == AT_A::_128CYCLES
360    }
361    #[doc = "Checks if the value of the field is `_256CYCLES`"]
362    #[inline(always)]
363    pub fn is_256cycles(&self) -> bool {
364        *self == AT_A::_256CYCLES
365    }
366}
367#[doc = "Field `AT` writer - Single Channel Acquisition Time"]
368pub type AT_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRL_SPEC, u8, AT_A, 4, 24>;
369impl<'a> AT_W<'a> {
370    #[doc = "1 conversion clock cycle acquisition time for single channel"]
371    #[inline(always)]
372    pub fn _1cycle(self) -> &'a mut W {
373        self.variant(AT_A::_1CYCLE)
374    }
375    #[doc = "2 conversion clock cycles acquisition time for single channel"]
376    #[inline(always)]
377    pub fn _2cycles(self) -> &'a mut W {
378        self.variant(AT_A::_2CYCLES)
379    }
380    #[doc = "3 conversion clock cycles acquisition time for single channel"]
381    #[inline(always)]
382    pub fn _3cycles(self) -> &'a mut W {
383        self.variant(AT_A::_3CYCLES)
384    }
385    #[doc = "4 conversion clock cycles acquisition time for single channel"]
386    #[inline(always)]
387    pub fn _4cycles(self) -> &'a mut W {
388        self.variant(AT_A::_4CYCLES)
389    }
390    #[doc = "8 conversion clock cycles acquisition time for single channel"]
391    #[inline(always)]
392    pub fn _8cycles(self) -> &'a mut W {
393        self.variant(AT_A::_8CYCLES)
394    }
395    #[doc = "16 conversion clock cycles acquisition time for single channel"]
396    #[inline(always)]
397    pub fn _16cycles(self) -> &'a mut W {
398        self.variant(AT_A::_16CYCLES)
399    }
400    #[doc = "32 conversion clock cycles acquisition time for single channel"]
401    #[inline(always)]
402    pub fn _32cycles(self) -> &'a mut W {
403        self.variant(AT_A::_32CYCLES)
404    }
405    #[doc = "64 conversion clock cycles acquisition time for single channel"]
406    #[inline(always)]
407    pub fn _64cycles(self) -> &'a mut W {
408        self.variant(AT_A::_64CYCLES)
409    }
410    #[doc = "128 conversion clock cycles acquisition time for single channel"]
411    #[inline(always)]
412    pub fn _128cycles(self) -> &'a mut W {
413        self.variant(AT_A::_128CYCLES)
414    }
415    #[doc = "256 conversion clock cycles acquisition time for single channel"]
416    #[inline(always)]
417    pub fn _256cycles(self) -> &'a mut W {
418        self.variant(AT_A::_256CYCLES)
419    }
420}
421#[doc = "Field `PRSEN` reader - Single Channel PRS Trigger Enable"]
422pub type PRSEN_R = crate::BitReader<bool>;
423#[doc = "Field `PRSEN` writer - Single Channel PRS Trigger Enable"]
424pub type PRSEN_W<'a> = crate::BitWriter<'a, u32, SINGLECTRL_SPEC, bool, 29>;
425#[doc = "Field `CMPEN` reader - Compare Logic Enable for Single Channel"]
426pub type CMPEN_R = crate::BitReader<bool>;
427#[doc = "Field `CMPEN` writer - Compare Logic Enable for Single Channel"]
428pub type CMPEN_W<'a> = crate::BitWriter<'a, u32, SINGLECTRL_SPEC, bool, 31>;
429impl R {
430    #[doc = "Bit 0 - Single Channel Repetitive Mode"]
431    #[inline(always)]
432    pub fn rep(&self) -> REP_R {
433        REP_R::new((self.bits & 1) != 0)
434    }
435    #[doc = "Bit 1 - Single Channel Differential Mode"]
436    #[inline(always)]
437    pub fn diff(&self) -> DIFF_R {
438        DIFF_R::new(((self.bits >> 1) & 1) != 0)
439    }
440    #[doc = "Bit 2 - Single Channel Result Adjustment"]
441    #[inline(always)]
442    pub fn adj(&self) -> ADJ_R {
443        ADJ_R::new(((self.bits >> 2) & 1) != 0)
444    }
445    #[doc = "Bits 3:4 - Single Channel Resolution Select"]
446    #[inline(always)]
447    pub fn res(&self) -> RES_R {
448        RES_R::new(((self.bits >> 3) & 3) as u8)
449    }
450    #[doc = "Bits 5:7 - Single Channel Reference Selection"]
451    #[inline(always)]
452    pub fn ref_(&self) -> REF_R {
453        REF_R::new(((self.bits >> 5) & 7) as u8)
454    }
455    #[doc = "Bits 8:15 - Single Channel Positive Input Selection"]
456    #[inline(always)]
457    pub fn possel(&self) -> POSSEL_R {
458        POSSEL_R::new(((self.bits >> 8) & 0xff) as u8)
459    }
460    #[doc = "Bits 16:23 - Single Channel Negative Input Selection"]
461    #[inline(always)]
462    pub fn negsel(&self) -> NEGSEL_R {
463        NEGSEL_R::new(((self.bits >> 16) & 0xff) as u8)
464    }
465    #[doc = "Bits 24:27 - Single Channel Acquisition Time"]
466    #[inline(always)]
467    pub fn at(&self) -> AT_R {
468        AT_R::new(((self.bits >> 24) & 0x0f) as u8)
469    }
470    #[doc = "Bit 29 - Single Channel PRS Trigger Enable"]
471    #[inline(always)]
472    pub fn prsen(&self) -> PRSEN_R {
473        PRSEN_R::new(((self.bits >> 29) & 1) != 0)
474    }
475    #[doc = "Bit 31 - Compare Logic Enable for Single Channel"]
476    #[inline(always)]
477    pub fn cmpen(&self) -> CMPEN_R {
478        CMPEN_R::new(((self.bits >> 31) & 1) != 0)
479    }
480}
481impl W {
482    #[doc = "Bit 0 - Single Channel Repetitive Mode"]
483    #[inline(always)]
484    pub fn rep(&mut self) -> REP_W {
485        REP_W::new(self)
486    }
487    #[doc = "Bit 1 - Single Channel Differential Mode"]
488    #[inline(always)]
489    pub fn diff(&mut self) -> DIFF_W {
490        DIFF_W::new(self)
491    }
492    #[doc = "Bit 2 - Single Channel Result Adjustment"]
493    #[inline(always)]
494    pub fn adj(&mut self) -> ADJ_W {
495        ADJ_W::new(self)
496    }
497    #[doc = "Bits 3:4 - Single Channel Resolution Select"]
498    #[inline(always)]
499    pub fn res(&mut self) -> RES_W {
500        RES_W::new(self)
501    }
502    #[doc = "Bits 5:7 - Single Channel Reference Selection"]
503    #[inline(always)]
504    pub fn ref_(&mut self) -> REF_W {
505        REF_W::new(self)
506    }
507    #[doc = "Bits 8:15 - Single Channel Positive Input Selection"]
508    #[inline(always)]
509    pub fn possel(&mut self) -> POSSEL_W {
510        POSSEL_W::new(self)
511    }
512    #[doc = "Bits 16:23 - Single Channel Negative Input Selection"]
513    #[inline(always)]
514    pub fn negsel(&mut self) -> NEGSEL_W {
515        NEGSEL_W::new(self)
516    }
517    #[doc = "Bits 24:27 - Single Channel Acquisition Time"]
518    #[inline(always)]
519    pub fn at(&mut self) -> AT_W {
520        AT_W::new(self)
521    }
522    #[doc = "Bit 29 - Single Channel PRS Trigger Enable"]
523    #[inline(always)]
524    pub fn prsen(&mut self) -> PRSEN_W {
525        PRSEN_W::new(self)
526    }
527    #[doc = "Bit 31 - Compare Logic Enable for Single Channel"]
528    #[inline(always)]
529    pub fn cmpen(&mut self) -> CMPEN_W {
530        CMPEN_W::new(self)
531    }
532    #[doc = "Writes raw bits to the register."]
533    #[inline(always)]
534    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
535        self.0.bits(bits);
536        self
537    }
538}
539#[doc = "Single Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [singlectrl](index.html) module"]
540pub struct SINGLECTRL_SPEC;
541impl crate::RegisterSpec for SINGLECTRL_SPEC {
542    type Ux = u32;
543}
544#[doc = "`read()` method returns [singlectrl::R](R) reader structure"]
545impl crate::Readable for SINGLECTRL_SPEC {
546    type Reader = R;
547}
548#[doc = "`write(|w| ..)` method takes [singlectrl::W](W) writer structure"]
549impl crate::Writable for SINGLECTRL_SPEC {
550    type Writer = W;
551}
552#[doc = "`reset()` method sets SINGLECTRL to value 0x00ff_ff00"]
553impl crate::Resettable for SINGLECTRL_SPEC {
554    #[inline(always)]
555    fn reset_value() -> Self::Ux {
556        0x00ff_ff00
557    }
558}
efm32gg12b810_pac/adc0/singlectrl.rs

efm32gg12b810_pac/adc0/
singlectrl.rs
