efm32gg12b530_pac/msc/
ifs.rs

1#[doc = "Register `IFS` writer"]
2pub struct W(crate::W<IFS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ERASE` writer - Set ERASE Interrupt Flag"]
23pub type ERASE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 0>;
24#[doc = "Field `WRITE` writer - Set WRITE Interrupt Flag"]
25pub type WRITE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 1>;
26#[doc = "Field `CHOF` writer - Set CHOF Interrupt Flag"]
27pub type CHOF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 2>;
28#[doc = "Field `CMOF` writer - Set CMOF Interrupt Flag"]
29pub type CMOF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 3>;
30#[doc = "Field `PWRUPF` writer - Set PWRUPF Interrupt Flag"]
31pub type PWRUPF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 4>;
32#[doc = "Field `ICACHERR` writer - Set ICACHERR Interrupt Flag"]
33pub type ICACHERR_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 5>;
34#[doc = "Field `WDATAOV` writer - Set WDATAOV Interrupt Flag"]
35pub type WDATAOV_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 6>;
36#[doc = "Field `LVEWRITE` writer - Set LVEWRITE Interrupt Flag"]
37pub type LVEWRITE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 8>;
38#[doc = "Field `RAMERR1B` writer - Set RAMERR1B Interrupt Flag"]
39pub type RAMERR1B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 16>;
40#[doc = "Field `RAMERR2B` writer - Set RAMERR2B Interrupt Flag"]
41pub type RAMERR2B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 17>;
42#[doc = "Field `RAM1ERR1B` writer - Set RAM1ERR1B Interrupt Flag"]
43pub type RAM1ERR1B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 18>;
44#[doc = "Field `RAM1ERR2B` writer - Set RAM1ERR2B Interrupt Flag"]
45pub type RAM1ERR2B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 19>;
46#[doc = "Field `RAM2ERR1B` writer - Set RAM2ERR1B Interrupt Flag"]
47pub type RAM2ERR1B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 20>;
48#[doc = "Field `RAM2ERR2B` writer - Set RAM2ERR2B Interrupt Flag"]
49pub type RAM2ERR2B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 21>;
50impl W {
51    #[doc = "Bit 0 - Set ERASE Interrupt Flag"]
52    #[inline(always)]
53    pub fn erase(&mut self) -> ERASE_W {
54        ERASE_W::new(self)
55    }
56    #[doc = "Bit 1 - Set WRITE Interrupt Flag"]
57    #[inline(always)]
58    pub fn write(&mut self) -> WRITE_W {
59        WRITE_W::new(self)
60    }
61    #[doc = "Bit 2 - Set CHOF Interrupt Flag"]
62    #[inline(always)]
63    pub fn chof(&mut self) -> CHOF_W {
64        CHOF_W::new(self)
65    }
66    #[doc = "Bit 3 - Set CMOF Interrupt Flag"]
67    #[inline(always)]
68    pub fn cmof(&mut self) -> CMOF_W {
69        CMOF_W::new(self)
70    }
71    #[doc = "Bit 4 - Set PWRUPF Interrupt Flag"]
72    #[inline(always)]
73    pub fn pwrupf(&mut self) -> PWRUPF_W {
74        PWRUPF_W::new(self)
75    }
76    #[doc = "Bit 5 - Set ICACHERR Interrupt Flag"]
77    #[inline(always)]
78    pub fn icacherr(&mut self) -> ICACHERR_W {
79        ICACHERR_W::new(self)
80    }
81    #[doc = "Bit 6 - Set WDATAOV Interrupt Flag"]
82    #[inline(always)]
83    pub fn wdataov(&mut self) -> WDATAOV_W {
84        WDATAOV_W::new(self)
85    }
86    #[doc = "Bit 8 - Set LVEWRITE Interrupt Flag"]
87    #[inline(always)]
88    pub fn lvewrite(&mut self) -> LVEWRITE_W {
89        LVEWRITE_W::new(self)
90    }
91    #[doc = "Bit 16 - Set RAMERR1B Interrupt Flag"]
92    #[inline(always)]
93    pub fn ramerr1b(&mut self) -> RAMERR1B_W {
94        RAMERR1B_W::new(self)
95    }
96    #[doc = "Bit 17 - Set RAMERR2B Interrupt Flag"]
97    #[inline(always)]
98    pub fn ramerr2b(&mut self) -> RAMERR2B_W {
99        RAMERR2B_W::new(self)
100    }
101    #[doc = "Bit 18 - Set RAM1ERR1B Interrupt Flag"]
102    #[inline(always)]
103    pub fn ram1err1b(&mut self) -> RAM1ERR1B_W {
104        RAM1ERR1B_W::new(self)
105    }
106    #[doc = "Bit 19 - Set RAM1ERR2B Interrupt Flag"]
107    #[inline(always)]
108    pub fn ram1err2b(&mut self) -> RAM1ERR2B_W {
109        RAM1ERR2B_W::new(self)
110    }
111    #[doc = "Bit 20 - Set RAM2ERR1B Interrupt Flag"]
112    #[inline(always)]
113    pub fn ram2err1b(&mut self) -> RAM2ERR1B_W {
114        RAM2ERR1B_W::new(self)
115    }
116    #[doc = "Bit 21 - Set RAM2ERR2B Interrupt Flag"]
117    #[inline(always)]
118    pub fn ram2err2b(&mut self) -> RAM2ERR2B_W {
119        RAM2ERR2B_W::new(self)
120    }
121    #[doc = "Writes raw bits to the register."]
122    #[inline(always)]
123    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
124        self.0.bits(bits);
125        self
126    }
127}
128#[doc = "Interrupt Flag Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifs](index.html) module"]
129pub struct IFS_SPEC;
130impl crate::RegisterSpec for IFS_SPEC {
131    type Ux = u32;
132}
133#[doc = "`write(|w| ..)` method takes [ifs::W](W) writer structure"]
134impl crate::Writable for IFS_SPEC {
135    type Writer = W;
136}
137#[doc = "`reset()` method sets IFS to value 0"]
138impl crate::Resettable for IFS_SPEC {
139    #[inline(always)]
140    fn reset_value() -> Self::Ux {
141        0
142    }
143}
efm32gg12b530_pac/msc/ifs.rs

efm32gg12b530_pac/msc/
ifs.rs
