efm32gg12b530_pac/can1/
mir0_ctrl.rs

1#[doc = "Register `MIR0_CTRL` reader"]
2pub struct R(crate::R<MIR0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MIR0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MIR0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MIR0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MIR0_CTRL` writer"]
17pub struct W(crate::W<MIR0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MIR0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MIR0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MIR0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DLC` reader - Data Length Code"]
38pub type DLC_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DLC` writer - Data Length Code"]
40pub type DLC_W<'a> = crate::FieldWriter<'a, u32, MIR0_CTRL_SPEC, u8, u8, 4, 0>;
41#[doc = "Field `EOB` reader - End of Buffer"]
42pub type EOB_R = crate::BitReader<bool>;
43#[doc = "Field `EOB` writer - End of Buffer"]
44pub type EOB_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 7>;
45#[doc = "Field `TXRQST` reader - Transmit Request"]
46pub type TXRQST_R = crate::BitReader<bool>;
47#[doc = "Field `TXRQST` writer - Transmit Request"]
48pub type TXRQST_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 8>;
49#[doc = "Field `RMTEN` reader - Remote Enable"]
50pub type RMTEN_R = crate::BitReader<bool>;
51#[doc = "Field `RMTEN` writer - Remote Enable"]
52pub type RMTEN_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 9>;
53#[doc = "Field `RXIE` reader - Receive Interrupt Enable"]
54pub type RXIE_R = crate::BitReader<bool>;
55#[doc = "Field `RXIE` writer - Receive Interrupt Enable"]
56pub type RXIE_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 10>;
57#[doc = "Field `TXIE` reader - Transmit Interrupt Enable"]
58pub type TXIE_R = crate::BitReader<bool>;
59#[doc = "Field `TXIE` writer - Transmit Interrupt Enable"]
60pub type TXIE_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 11>;
61#[doc = "Field `UMASK` reader - Use Acceptance Mask"]
62pub type UMASK_R = crate::BitReader<bool>;
63#[doc = "Field `UMASK` writer - Use Acceptance Mask"]
64pub type UMASK_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 12>;
65#[doc = "Field `INTPND` reader - Interrupt Pending"]
66pub type INTPND_R = crate::BitReader<bool>;
67#[doc = "Field `INTPND` writer - Interrupt Pending"]
68pub type INTPND_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 13>;
69#[doc = "Field `MESSAGEOF` reader - Message Lost (only Valid for Message Objects With Direction = Receive)"]
70pub type MESSAGEOF_R = crate::BitReader<bool>;
71#[doc = "Field `MESSAGEOF` writer - Message Lost (only Valid for Message Objects With Direction = Receive)"]
72pub type MESSAGEOF_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 14>;
73#[doc = "Field `DATAVALID` reader - New Data"]
74pub type DATAVALID_R = crate::BitReader<bool>;
75#[doc = "Field `DATAVALID` writer - New Data"]
76pub type DATAVALID_W<'a> = crate::BitWriter<'a, u32, MIR0_CTRL_SPEC, bool, 15>;
77impl R {
78    #[doc = "Bits 0:3 - Data Length Code"]
79    #[inline(always)]
80    pub fn dlc(&self) -> DLC_R {
81        DLC_R::new((self.bits & 0x0f) as u8)
82    }
83    #[doc = "Bit 7 - End of Buffer"]
84    #[inline(always)]
85    pub fn eob(&self) -> EOB_R {
86        EOB_R::new(((self.bits >> 7) & 1) != 0)
87    }
88    #[doc = "Bit 8 - Transmit Request"]
89    #[inline(always)]
90    pub fn txrqst(&self) -> TXRQST_R {
91        TXRQST_R::new(((self.bits >> 8) & 1) != 0)
92    }
93    #[doc = "Bit 9 - Remote Enable"]
94    #[inline(always)]
95    pub fn rmten(&self) -> RMTEN_R {
96        RMTEN_R::new(((self.bits >> 9) & 1) != 0)
97    }
98    #[doc = "Bit 10 - Receive Interrupt Enable"]
99    #[inline(always)]
100    pub fn rxie(&self) -> RXIE_R {
101        RXIE_R::new(((self.bits >> 10) & 1) != 0)
102    }
103    #[doc = "Bit 11 - Transmit Interrupt Enable"]
104    #[inline(always)]
105    pub fn txie(&self) -> TXIE_R {
106        TXIE_R::new(((self.bits >> 11) & 1) != 0)
107    }
108    #[doc = "Bit 12 - Use Acceptance Mask"]
109    #[inline(always)]
110    pub fn umask(&self) -> UMASK_R {
111        UMASK_R::new(((self.bits >> 12) & 1) != 0)
112    }
113    #[doc = "Bit 13 - Interrupt Pending"]
114    #[inline(always)]
115    pub fn intpnd(&self) -> INTPND_R {
116        INTPND_R::new(((self.bits >> 13) & 1) != 0)
117    }
118    #[doc = "Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)"]
119    #[inline(always)]
120    pub fn messageof(&self) -> MESSAGEOF_R {
121        MESSAGEOF_R::new(((self.bits >> 14) & 1) != 0)
122    }
123    #[doc = "Bit 15 - New Data"]
124    #[inline(always)]
125    pub fn datavalid(&self) -> DATAVALID_R {
126        DATAVALID_R::new(((self.bits >> 15) & 1) != 0)
127    }
128}
129impl W {
130    #[doc = "Bits 0:3 - Data Length Code"]
131    #[inline(always)]
132    pub fn dlc(&mut self) -> DLC_W {
133        DLC_W::new(self)
134    }
135    #[doc = "Bit 7 - End of Buffer"]
136    #[inline(always)]
137    pub fn eob(&mut self) -> EOB_W {
138        EOB_W::new(self)
139    }
140    #[doc = "Bit 8 - Transmit Request"]
141    #[inline(always)]
142    pub fn txrqst(&mut self) -> TXRQST_W {
143        TXRQST_W::new(self)
144    }
145    #[doc = "Bit 9 - Remote Enable"]
146    #[inline(always)]
147    pub fn rmten(&mut self) -> RMTEN_W {
148        RMTEN_W::new(self)
149    }
150    #[doc = "Bit 10 - Receive Interrupt Enable"]
151    #[inline(always)]
152    pub fn rxie(&mut self) -> RXIE_W {
153        RXIE_W::new(self)
154    }
155    #[doc = "Bit 11 - Transmit Interrupt Enable"]
156    #[inline(always)]
157    pub fn txie(&mut self) -> TXIE_W {
158        TXIE_W::new(self)
159    }
160    #[doc = "Bit 12 - Use Acceptance Mask"]
161    #[inline(always)]
162    pub fn umask(&mut self) -> UMASK_W {
163        UMASK_W::new(self)
164    }
165    #[doc = "Bit 13 - Interrupt Pending"]
166    #[inline(always)]
167    pub fn intpnd(&mut self) -> INTPND_W {
168        INTPND_W::new(self)
169    }
170    #[doc = "Bit 14 - Message Lost (only Valid for Message Objects With Direction = Receive)"]
171    #[inline(always)]
172    pub fn messageof(&mut self) -> MESSAGEOF_W {
173        MESSAGEOF_W::new(self)
174    }
175    #[doc = "Bit 15 - New Data"]
176    #[inline(always)]
177    pub fn datavalid(&mut self) -> DATAVALID_W {
178        DATAVALID_W::new(self)
179    }
180    #[doc = "Writes raw bits to the register."]
181    #[inline(always)]
182    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183        self.0.bits(bits);
184        self
185    }
186}
187#[doc = "Interface Message Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mir0_ctrl](index.html) module"]
188pub struct MIR0_CTRL_SPEC;
189impl crate::RegisterSpec for MIR0_CTRL_SPEC {
190    type Ux = u32;
191}
192#[doc = "`read()` method returns [mir0_ctrl::R](R) reader structure"]
193impl crate::Readable for MIR0_CTRL_SPEC {
194    type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [mir0_ctrl::W](W) writer structure"]
197impl crate::Writable for MIR0_CTRL_SPEC {
198    type Writer = W;
199}
200#[doc = "`reset()` method sets MIR0_CTRL to value 0"]
201impl crate::Resettable for MIR0_CTRL_SPEC {
202    #[inline(always)]
203    fn reset_value() -> Self::Ux {
204        0
205    }
206}
efm32gg12b530_pac/can1/mir0_ctrl.rs

efm32gg12b530_pac/can1/
mir0_ctrl.rs
