efm32gg12b430_pac/msc/
ramctrl.rs

1#[doc = "Register `RAMCTRL` reader"]
2pub struct R(crate::R<RAMCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RAMCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RAMCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RAMCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RAMCTRL` writer"]
17pub struct W(crate::W<RAMCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RAMCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RAMCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RAMCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RAMWSEN` reader - RAM WAIT STATE Enable"]
38pub type RAMWSEN_R = crate::BitReader<bool>;
39#[doc = "Field `RAMWSEN` writer - RAM WAIT STATE Enable"]
40pub type RAMWSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 1>;
41#[doc = "Field `RAMPREFETCHEN` reader - RAM Prefetch Enable"]
42pub type RAMPREFETCHEN_R = crate::BitReader<bool>;
43#[doc = "Field `RAMPREFETCHEN` writer - RAM Prefetch Enable"]
44pub type RAMPREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 2>;
45#[doc = "Field `RAM1WSEN` reader - RAM1 WAIT STATE Enable"]
46pub type RAM1WSEN_R = crate::BitReader<bool>;
47#[doc = "Field `RAM1WSEN` writer - RAM1 WAIT STATE Enable"]
48pub type RAM1WSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 9>;
49#[doc = "Field `RAM1PREFETCHEN` reader - RAM1 Prefetch Enable"]
50pub type RAM1PREFETCHEN_R = crate::BitReader<bool>;
51#[doc = "Field `RAM1PREFETCHEN` writer - RAM1 Prefetch Enable"]
52pub type RAM1PREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 10>;
53#[doc = "Field `RAM2WSEN` reader - RAM2 WAIT STATE Enable"]
54pub type RAM2WSEN_R = crate::BitReader<bool>;
55#[doc = "Field `RAM2WSEN` writer - RAM2 WAIT STATE Enable"]
56pub type RAM2WSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 17>;
57#[doc = "Field `RAM2PREFETCHEN` reader - RAM2 Prefetch Enable"]
58pub type RAM2PREFETCHEN_R = crate::BitReader<bool>;
59#[doc = "Field `RAM2PREFETCHEN` writer - RAM2 Prefetch Enable"]
60pub type RAM2PREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 18>;
61impl R {
62    #[doc = "Bit 1 - RAM WAIT STATE Enable"]
63    #[inline(always)]
64    pub fn ramwsen(&self) -> RAMWSEN_R {
65        RAMWSEN_R::new(((self.bits >> 1) & 1) != 0)
66    }
67    #[doc = "Bit 2 - RAM Prefetch Enable"]
68    #[inline(always)]
69    pub fn ramprefetchen(&self) -> RAMPREFETCHEN_R {
70        RAMPREFETCHEN_R::new(((self.bits >> 2) & 1) != 0)
71    }
72    #[doc = "Bit 9 - RAM1 WAIT STATE Enable"]
73    #[inline(always)]
74    pub fn ram1wsen(&self) -> RAM1WSEN_R {
75        RAM1WSEN_R::new(((self.bits >> 9) & 1) != 0)
76    }
77    #[doc = "Bit 10 - RAM1 Prefetch Enable"]
78    #[inline(always)]
79    pub fn ram1prefetchen(&self) -> RAM1PREFETCHEN_R {
80        RAM1PREFETCHEN_R::new(((self.bits >> 10) & 1) != 0)
81    }
82    #[doc = "Bit 17 - RAM2 WAIT STATE Enable"]
83    #[inline(always)]
84    pub fn ram2wsen(&self) -> RAM2WSEN_R {
85        RAM2WSEN_R::new(((self.bits >> 17) & 1) != 0)
86    }
87    #[doc = "Bit 18 - RAM2 Prefetch Enable"]
88    #[inline(always)]
89    pub fn ram2prefetchen(&self) -> RAM2PREFETCHEN_R {
90        RAM2PREFETCHEN_R::new(((self.bits >> 18) & 1) != 0)
91    }
92}
93impl W {
94    #[doc = "Bit 1 - RAM WAIT STATE Enable"]
95    #[inline(always)]
96    pub fn ramwsen(&mut self) -> RAMWSEN_W {
97        RAMWSEN_W::new(self)
98    }
99    #[doc = "Bit 2 - RAM Prefetch Enable"]
100    #[inline(always)]
101    pub fn ramprefetchen(&mut self) -> RAMPREFETCHEN_W {
102        RAMPREFETCHEN_W::new(self)
103    }
104    #[doc = "Bit 9 - RAM1 WAIT STATE Enable"]
105    #[inline(always)]
106    pub fn ram1wsen(&mut self) -> RAM1WSEN_W {
107        RAM1WSEN_W::new(self)
108    }
109    #[doc = "Bit 10 - RAM1 Prefetch Enable"]
110    #[inline(always)]
111    pub fn ram1prefetchen(&mut self) -> RAM1PREFETCHEN_W {
112        RAM1PREFETCHEN_W::new(self)
113    }
114    #[doc = "Bit 17 - RAM2 WAIT STATE Enable"]
115    #[inline(always)]
116    pub fn ram2wsen(&mut self) -> RAM2WSEN_W {
117        RAM2WSEN_W::new(self)
118    }
119    #[doc = "Bit 18 - RAM2 Prefetch Enable"]
120    #[inline(always)]
121    pub fn ram2prefetchen(&mut self) -> RAM2PREFETCHEN_W {
122        RAM2PREFETCHEN_W::new(self)
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "RAM Control Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ramctrl](index.html) module"]
132pub struct RAMCTRL_SPEC;
133impl crate::RegisterSpec for RAMCTRL_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [ramctrl::R](R) reader structure"]
137impl crate::Readable for RAMCTRL_SPEC {
138    type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [ramctrl::W](W) writer structure"]
141impl crate::Writable for RAMCTRL_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets RAMCTRL to value 0"]
145impl crate::Resettable for RAMCTRL_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0
149    }
150}
efm32gg12b430_pac/msc/ramctrl.rs

efm32gg12b430_pac/msc/
ramctrl.rs
