efm32gg12b430_pac/cmu/
hfperclken1.rs

1#[doc = "Register `HFPERCLKEN1` reader"]
2pub struct R(crate::R<HFPERCLKEN1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFPERCLKEN1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFPERCLKEN1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFPERCLKEN1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFPERCLKEN1` writer"]
17pub struct W(crate::W<HFPERCLKEN1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFPERCLKEN1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFPERCLKEN1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFPERCLKEN1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
38pub type UART0_R = crate::BitReader<bool>;
39#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
40pub type UART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 0>;
41#[doc = "Field `UART1` reader - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
42pub type UART1_R = crate::BitReader<bool>;
43#[doc = "Field `UART1` writer - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
44pub type UART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 1>;
45#[doc = "Field `WTIMER0` reader - Wide Timer 0 Clock Enable"]
46pub type WTIMER0_R = crate::BitReader<bool>;
47#[doc = "Field `WTIMER0` writer - Wide Timer 0 Clock Enable"]
48pub type WTIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 2>;
49#[doc = "Field `WTIMER1` reader - Wide Timer 0 Clock Enable"]
50pub type WTIMER1_R = crate::BitReader<bool>;
51#[doc = "Field `WTIMER1` writer - Wide Timer 0 Clock Enable"]
52pub type WTIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 3>;
53#[doc = "Field `CAN0` reader - CAN 0 Clock Enable"]
54pub type CAN0_R = crate::BitReader<bool>;
55#[doc = "Field `CAN0` writer - CAN 0 Clock Enable"]
56pub type CAN0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 4>;
57#[doc = "Field `CAN1` reader - CAN 1 Clock Enable"]
58pub type CAN1_R = crate::BitReader<bool>;
59#[doc = "Field `CAN1` writer - CAN 1 Clock Enable"]
60pub type CAN1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 5>;
61#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 Clock Enable"]
62pub type VDAC0_R = crate::BitReader<bool>;
63#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 Clock Enable"]
64pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 6>;
65#[doc = "Field `CSEN` reader - Capacitive touch sense module Clock Enable"]
66pub type CSEN_R = crate::BitReader<bool>;
67#[doc = "Field `CSEN` writer - Capacitive touch sense module Clock Enable"]
68pub type CSEN_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 7>;
69impl R {
70    #[doc = "Bit 0 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
71    #[inline(always)]
72    pub fn uart0(&self) -> UART0_R {
73        UART0_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
76    #[inline(always)]
77    pub fn uart1(&self) -> UART1_R {
78        UART1_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Wide Timer 0 Clock Enable"]
81    #[inline(always)]
82    pub fn wtimer0(&self) -> WTIMER0_R {
83        WTIMER0_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - Wide Timer 0 Clock Enable"]
86    #[inline(always)]
87    pub fn wtimer1(&self) -> WTIMER1_R {
88        WTIMER1_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - CAN 0 Clock Enable"]
91    #[inline(always)]
92    pub fn can0(&self) -> CAN0_R {
93        CAN0_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - CAN 1 Clock Enable"]
96    #[inline(always)]
97    pub fn can1(&self) -> CAN1_R {
98        CAN1_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - Digital to Analog Converter 0 Clock Enable"]
101    #[inline(always)]
102    pub fn vdac0(&self) -> VDAC0_R {
103        VDAC0_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - Capacitive touch sense module Clock Enable"]
106    #[inline(always)]
107    pub fn csen(&self) -> CSEN_R {
108        CSEN_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
113    #[inline(always)]
114    pub fn uart0(&mut self) -> UART0_W {
115        UART0_W::new(self)
116    }
117    #[doc = "Bit 1 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
118    #[inline(always)]
119    pub fn uart1(&mut self) -> UART1_W {
120        UART1_W::new(self)
121    }
122    #[doc = "Bit 2 - Wide Timer 0 Clock Enable"]
123    #[inline(always)]
124    pub fn wtimer0(&mut self) -> WTIMER0_W {
125        WTIMER0_W::new(self)
126    }
127    #[doc = "Bit 3 - Wide Timer 0 Clock Enable"]
128    #[inline(always)]
129    pub fn wtimer1(&mut self) -> WTIMER1_W {
130        WTIMER1_W::new(self)
131    }
132    #[doc = "Bit 4 - CAN 0 Clock Enable"]
133    #[inline(always)]
134    pub fn can0(&mut self) -> CAN0_W {
135        CAN0_W::new(self)
136    }
137    #[doc = "Bit 5 - CAN 1 Clock Enable"]
138    #[inline(always)]
139    pub fn can1(&mut self) -> CAN1_W {
140        CAN1_W::new(self)
141    }
142    #[doc = "Bit 6 - Digital to Analog Converter 0 Clock Enable"]
143    #[inline(always)]
144    pub fn vdac0(&mut self) -> VDAC0_W {
145        VDAC0_W::new(self)
146    }
147    #[doc = "Bit 7 - Capacitive touch sense module Clock Enable"]
148    #[inline(always)]
149    pub fn csen(&mut self) -> CSEN_W {
150        CSEN_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "High Frequency Peripheral Clock Enable Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken1](index.html) module"]
160pub struct HFPERCLKEN1_SPEC;
161impl crate::RegisterSpec for HFPERCLKEN1_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [hfperclken1::R](R) reader structure"]
165impl crate::Readable for HFPERCLKEN1_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [hfperclken1::W](W) writer structure"]
169impl crate::Writable for HFPERCLKEN1_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets HFPERCLKEN1 to value 0"]
173impl crate::Resettable for HFPERCLKEN1_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0
177    }
178}
efm32gg12b430_pac/cmu/hfperclken1.rs

efm32gg12b430_pac/cmu/
hfperclken1.rs
