efm32gg12b430_pac/usb/
diep3_int.rs

1#[doc = "Register `DIEP3_INT` reader"]
2pub struct R(crate::R<DIEP3_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEP3_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEP3_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEP3_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEP3_INT` writer"]
17pub struct W(crate::W<DIEP3_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEP3_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEP3_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEP3_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed Interrupt"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed Interrupt"]
40pub type XFERCOMPL_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 0>;
41#[doc = "Field `EPDISBLD` reader - Endpoint Disabled Interrupt"]
42pub type EPDISBLD_R = crate::BitReader<bool>;
43#[doc = "Field `EPDISBLD` writer - Endpoint Disabled Interrupt"]
44pub type EPDISBLD_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 1>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 2>;
49#[doc = "Field `TIMEOUT` reader - Timeout Condition"]
50pub type TIMEOUT_R = crate::BitReader<bool>;
51#[doc = "Field `TIMEOUT` writer - Timeout Condition"]
52pub type TIMEOUT_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 3>;
53#[doc = "Field `INTKNTXFEMP` reader - IN Token Received When TxFIFO is Empty"]
54pub type INTKNTXFEMP_R = crate::BitReader<bool>;
55#[doc = "Field `INTKNTXFEMP` writer - IN Token Received When TxFIFO is Empty"]
56pub type INTKNTXFEMP_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 4>;
57#[doc = "Field `INTKNEPMIS` reader - IN Token Received with EP Mismatch"]
58pub type INTKNEPMIS_R = crate::BitReader<bool>;
59#[doc = "Field `INTKNEPMIS` writer - IN Token Received with EP Mismatch"]
60pub type INTKNEPMIS_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 5>;
61#[doc = "Field `INEPNAKEFF` reader - IN Endpoint NAK Effective"]
62pub type INEPNAKEFF_R = crate::BitReader<bool>;
63#[doc = "Field `INEPNAKEFF` writer - IN Endpoint NAK Effective"]
64pub type INEPNAKEFF_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 6>;
65#[doc = "Field `TXFEMP` reader - Transmit FIFO Empty"]
66pub type TXFEMP_R = crate::BitReader<bool>;
67#[doc = "Field `TXFIFOUNDRN` reader - Fifo Underrun"]
68pub type TXFIFOUNDRN_R = crate::BitReader<bool>;
69#[doc = "Field `TXFIFOUNDRN` writer - Fifo Underrun"]
70pub type TXFIFOUNDRN_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 8>;
71#[doc = "Field `PKTDRPSTS` reader - Packet Drop Status"]
72pub type PKTDRPSTS_R = crate::BitReader<bool>;
73#[doc = "Field `PKTDRPSTS` writer - Packet Drop Status"]
74pub type PKTDRPSTS_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 11>;
75#[doc = "Field `BBLEERR` reader - Babble Interrupt"]
76pub type BBLEERR_R = crate::BitReader<bool>;
77#[doc = "Field `BBLEERR` writer - Babble Interrupt"]
78pub type BBLEERR_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 12>;
79#[doc = "Field `NAKINTRPT` reader - NAK Interrupt"]
80pub type NAKINTRPT_R = crate::BitReader<bool>;
81#[doc = "Field `NAKINTRPT` writer - NAK Interrupt"]
82pub type NAKINTRPT_W<'a> = crate::BitWriter<'a, u32, DIEP3_INT_SPEC, bool, 13>;
83impl R {
84    #[doc = "Bit 0 - Transfer Completed Interrupt"]
85    #[inline(always)]
86    pub fn xfercompl(&self) -> XFERCOMPL_R {
87        XFERCOMPL_R::new((self.bits & 1) != 0)
88    }
89    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
90    #[inline(always)]
91    pub fn epdisbld(&self) -> EPDISBLD_R {
92        EPDISBLD_R::new(((self.bits >> 1) & 1) != 0)
93    }
94    #[doc = "Bit 2 - AHB Error"]
95    #[inline(always)]
96    pub fn ahberr(&self) -> AHBERR_R {
97        AHBERR_R::new(((self.bits >> 2) & 1) != 0)
98    }
99    #[doc = "Bit 3 - Timeout Condition"]
100    #[inline(always)]
101    pub fn timeout(&self) -> TIMEOUT_R {
102        TIMEOUT_R::new(((self.bits >> 3) & 1) != 0)
103    }
104    #[doc = "Bit 4 - IN Token Received When TxFIFO is Empty"]
105    #[inline(always)]
106    pub fn intkntxfemp(&self) -> INTKNTXFEMP_R {
107        INTKNTXFEMP_R::new(((self.bits >> 4) & 1) != 0)
108    }
109    #[doc = "Bit 5 - IN Token Received with EP Mismatch"]
110    #[inline(always)]
111    pub fn intknepmis(&self) -> INTKNEPMIS_R {
112        INTKNEPMIS_R::new(((self.bits >> 5) & 1) != 0)
113    }
114    #[doc = "Bit 6 - IN Endpoint NAK Effective"]
115    #[inline(always)]
116    pub fn inepnakeff(&self) -> INEPNAKEFF_R {
117        INEPNAKEFF_R::new(((self.bits >> 6) & 1) != 0)
118    }
119    #[doc = "Bit 7 - Transmit FIFO Empty"]
120    #[inline(always)]
121    pub fn txfemp(&self) -> TXFEMP_R {
122        TXFEMP_R::new(((self.bits >> 7) & 1) != 0)
123    }
124    #[doc = "Bit 8 - Fifo Underrun"]
125    #[inline(always)]
126    pub fn txfifoundrn(&self) -> TXFIFOUNDRN_R {
127        TXFIFOUNDRN_R::new(((self.bits >> 8) & 1) != 0)
128    }
129    #[doc = "Bit 11 - Packet Drop Status"]
130    #[inline(always)]
131    pub fn pktdrpsts(&self) -> PKTDRPSTS_R {
132        PKTDRPSTS_R::new(((self.bits >> 11) & 1) != 0)
133    }
134    #[doc = "Bit 12 - Babble Interrupt"]
135    #[inline(always)]
136    pub fn bbleerr(&self) -> BBLEERR_R {
137        BBLEERR_R::new(((self.bits >> 12) & 1) != 0)
138    }
139    #[doc = "Bit 13 - NAK Interrupt"]
140    #[inline(always)]
141    pub fn nakintrpt(&self) -> NAKINTRPT_R {
142        NAKINTRPT_R::new(((self.bits >> 13) & 1) != 0)
143    }
144}
145impl W {
146    #[doc = "Bit 0 - Transfer Completed Interrupt"]
147    #[inline(always)]
148    pub fn xfercompl(&mut self) -> XFERCOMPL_W {
149        XFERCOMPL_W::new(self)
150    }
151    #[doc = "Bit 1 - Endpoint Disabled Interrupt"]
152    #[inline(always)]
153    pub fn epdisbld(&mut self) -> EPDISBLD_W {
154        EPDISBLD_W::new(self)
155    }
156    #[doc = "Bit 2 - AHB Error"]
157    #[inline(always)]
158    pub fn ahberr(&mut self) -> AHBERR_W {
159        AHBERR_W::new(self)
160    }
161    #[doc = "Bit 3 - Timeout Condition"]
162    #[inline(always)]
163    pub fn timeout(&mut self) -> TIMEOUT_W {
164        TIMEOUT_W::new(self)
165    }
166    #[doc = "Bit 4 - IN Token Received When TxFIFO is Empty"]
167    #[inline(always)]
168    pub fn intkntxfemp(&mut self) -> INTKNTXFEMP_W {
169        INTKNTXFEMP_W::new(self)
170    }
171    #[doc = "Bit 5 - IN Token Received with EP Mismatch"]
172    #[inline(always)]
173    pub fn intknepmis(&mut self) -> INTKNEPMIS_W {
174        INTKNEPMIS_W::new(self)
175    }
176    #[doc = "Bit 6 - IN Endpoint NAK Effective"]
177    #[inline(always)]
178    pub fn inepnakeff(&mut self) -> INEPNAKEFF_W {
179        INEPNAKEFF_W::new(self)
180    }
181    #[doc = "Bit 8 - Fifo Underrun"]
182    #[inline(always)]
183    pub fn txfifoundrn(&mut self) -> TXFIFOUNDRN_W {
184        TXFIFOUNDRN_W::new(self)
185    }
186    #[doc = "Bit 11 - Packet Drop Status"]
187    #[inline(always)]
188    pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W {
189        PKTDRPSTS_W::new(self)
190    }
191    #[doc = "Bit 12 - Babble Interrupt"]
192    #[inline(always)]
193    pub fn bbleerr(&mut self) -> BBLEERR_W {
194        BBLEERR_W::new(self)
195    }
196    #[doc = "Bit 13 - NAK Interrupt"]
197    #[inline(always)]
198    pub fn nakintrpt(&mut self) -> NAKINTRPT_W {
199        NAKINTRPT_W::new(self)
200    }
201    #[doc = "Writes raw bits to the register."]
202    #[inline(always)]
203    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
204        self.0.bits(bits);
205        self
206    }
207}
208#[doc = "Device IN Endpoint x+1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_int](index.html) module"]
209pub struct DIEP3_INT_SPEC;
210impl crate::RegisterSpec for DIEP3_INT_SPEC {
211    type Ux = u32;
212}
213#[doc = "`read()` method returns [diep3_int::R](R) reader structure"]
214impl crate::Readable for DIEP3_INT_SPEC {
215    type Reader = R;
216}
217#[doc = "`write(|w| ..)` method takes [diep3_int::W](W) writer structure"]
218impl crate::Writable for DIEP3_INT_SPEC {
219    type Writer = W;
220}
221#[doc = "`reset()` method sets DIEP3_INT to value 0x80"]
222impl crate::Resettable for DIEP3_INT_SPEC {
223    #[inline(always)]
224    fn reset_value() -> Self::Ux {
225        0x80
226    }
227}
efm32gg12b430_pac/usb/diep3_int.rs

efm32gg12b430_pac/usb/
diep3_int.rs
