efm32gg12b430_pac/adc0/
singlectrlx.rs

1#[doc = "Register `SINGLECTRLX` reader"]
2pub struct R(crate::R<SINGLECTRLX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SINGLECTRLX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SINGLECTRLX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SINGLECTRLX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SINGLECTRLX` writer"]
17pub struct W(crate::W<SINGLECTRLX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SINGLECTRLX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SINGLECTRLX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SINGLECTRLX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Single Channel Reference Selection\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum VREFSEL_A {
41    #[doc = "0: Internal 0.83V Bandgap reference"]
42    VBGR = 0,
43    #[doc = "1: Scaled AVDD: AVDD*(the VREF attenuation factor)"]
44    VDDXWATT = 1,
45    #[doc = "2: Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
46    VREFPWATT = 2,
47    #[doc = "3: Raw single ended external Vref: ADCn_EXTP"]
48    VREFP = 3,
49    #[doc = "4: Special mode used to generate ENTROPY."]
50    VENTROPY = 4,
51    #[doc = "5: Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
52    VREFPNWATT = 5,
53    #[doc = "6: Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
54    VREFPN = 6,
55    #[doc = "7: Internal Bandgap reference at low setting 0.78V"]
56    VBGRLOW = 7,
57}
58impl From<VREFSEL_A> for u8 {
59    #[inline(always)]
60    fn from(variant: VREFSEL_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `VREFSEL` reader - Single Channel Reference Selection"]
65pub type VREFSEL_R = crate::FieldReader<u8, VREFSEL_A>;
66impl VREFSEL_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> VREFSEL_A {
70        match self.bits {
71            0 => VREFSEL_A::VBGR,
72            1 => VREFSEL_A::VDDXWATT,
73            2 => VREFSEL_A::VREFPWATT,
74            3 => VREFSEL_A::VREFP,
75            4 => VREFSEL_A::VENTROPY,
76            5 => VREFSEL_A::VREFPNWATT,
77            6 => VREFSEL_A::VREFPN,
78            7 => VREFSEL_A::VBGRLOW,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `VBGR`"]
83    #[inline(always)]
84    pub fn is_vbgr(&self) -> bool {
85        *self == VREFSEL_A::VBGR
86    }
87    #[doc = "Checks if the value of the field is `VDDXWATT`"]
88    #[inline(always)]
89    pub fn is_vddxwatt(&self) -> bool {
90        *self == VREFSEL_A::VDDXWATT
91    }
92    #[doc = "Checks if the value of the field is `VREFPWATT`"]
93    #[inline(always)]
94    pub fn is_vrefpwatt(&self) -> bool {
95        *self == VREFSEL_A::VREFPWATT
96    }
97    #[doc = "Checks if the value of the field is `VREFP`"]
98    #[inline(always)]
99    pub fn is_vrefp(&self) -> bool {
100        *self == VREFSEL_A::VREFP
101    }
102    #[doc = "Checks if the value of the field is `VENTROPY`"]
103    #[inline(always)]
104    pub fn is_ventropy(&self) -> bool {
105        *self == VREFSEL_A::VENTROPY
106    }
107    #[doc = "Checks if the value of the field is `VREFPNWATT`"]
108    #[inline(always)]
109    pub fn is_vrefpnwatt(&self) -> bool {
110        *self == VREFSEL_A::VREFPNWATT
111    }
112    #[doc = "Checks if the value of the field is `VREFPN`"]
113    #[inline(always)]
114    pub fn is_vrefpn(&self) -> bool {
115        *self == VREFSEL_A::VREFPN
116    }
117    #[doc = "Checks if the value of the field is `VBGRLOW`"]
118    #[inline(always)]
119    pub fn is_vbgrlow(&self) -> bool {
120        *self == VREFSEL_A::VBGRLOW
121    }
122}
123#[doc = "Field `VREFSEL` writer - Single Channel Reference Selection"]
124pub type VREFSEL_W<'a> = crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, VREFSEL_A, 3, 0>;
125impl<'a> VREFSEL_W<'a> {
126    #[doc = "Internal 0.83V Bandgap reference"]
127    #[inline(always)]
128    pub fn vbgr(self) -> &'a mut W {
129        self.variant(VREFSEL_A::VBGR)
130    }
131    #[doc = "Scaled AVDD: AVDD*(the VREF attenuation factor)"]
132    #[inline(always)]
133    pub fn vddxwatt(self) -> &'a mut W {
134        self.variant(VREFSEL_A::VDDXWATT)
135    }
136    #[doc = "Scaled singled ended external Vref: ADCn_EXTP*(the VREF attenuation factor)"]
137    #[inline(always)]
138    pub fn vrefpwatt(self) -> &'a mut W {
139        self.variant(VREFSEL_A::VREFPWATT)
140    }
141    #[doc = "Raw single ended external Vref: ADCn_EXTP"]
142    #[inline(always)]
143    pub fn vrefp(self) -> &'a mut W {
144        self.variant(VREFSEL_A::VREFP)
145    }
146    #[doc = "Special mode used to generate ENTROPY."]
147    #[inline(always)]
148    pub fn ventropy(self) -> &'a mut W {
149        self.variant(VREFSEL_A::VENTROPY)
150    }
151    #[doc = "Scaled differential external Vref from : (ADCn_EXTP-ADCn_EXTN)*(the VREF attenuation factor)"]
152    #[inline(always)]
153    pub fn vrefpnwatt(self) -> &'a mut W {
154        self.variant(VREFSEL_A::VREFPNWATT)
155    }
156    #[doc = "Raw differential external Vref from : (ADCn_EXTP-ADCn_EXTN)"]
157    #[inline(always)]
158    pub fn vrefpn(self) -> &'a mut W {
159        self.variant(VREFSEL_A::VREFPN)
160    }
161    #[doc = "Internal Bandgap reference at low setting 0.78V"]
162    #[inline(always)]
163    pub fn vbgrlow(self) -> &'a mut W {
164        self.variant(VREFSEL_A::VBGRLOW)
165    }
166}
167#[doc = "Field `VREFATTFIX` reader - Enable Fixed Scaling on VREF"]
168pub type VREFATTFIX_R = crate::BitReader<bool>;
169#[doc = "Field `VREFATTFIX` writer - Enable Fixed Scaling on VREF"]
170pub type VREFATTFIX_W<'a> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, 3>;
171#[doc = "Field `VREFATT` reader - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
172pub type VREFATT_R = crate::FieldReader<u8, u8>;
173#[doc = "Field `VREFATT` writer - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
174pub type VREFATT_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, 4>;
175#[doc = "Field `VINATT` reader - Code for VIN Attenuation Factor"]
176pub type VINATT_R = crate::FieldReader<u8, u8>;
177#[doc = "Field `VINATT` writer - Code for VIN Attenuation Factor"]
178pub type VINATT_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 4, 8>;
179#[doc = "Field `DVL` reader - Single Channel DV Level Select"]
180pub type DVL_R = crate::FieldReader<u8, u8>;
181#[doc = "Field `DVL` writer - Single Channel DV Level Select"]
182pub type DVL_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 2, 12>;
183#[doc = "Field `FIFOOFACT` reader - Single Channel FIFO Overflow Action"]
184pub type FIFOOFACT_R = crate::BitReader<bool>;
185#[doc = "Field `FIFOOFACT` writer - Single Channel FIFO Overflow Action"]
186pub type FIFOOFACT_W<'a> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, 14>;
187#[doc = "Field `PRSMODE` reader - Single Channel PRS Trigger Mode"]
188pub type PRSMODE_R = crate::BitReader<bool>;
189#[doc = "Field `PRSMODE` writer - Single Channel PRS Trigger Mode"]
190pub type PRSMODE_W<'a> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, 16>;
191#[doc = "Single Channel PRS Trigger Select\n\nValue on reset: 0"]
192#[derive(Clone, Copy, Debug, PartialEq)]
193#[repr(u8)]
194pub enum PRSSEL_A {
195    #[doc = "0: PRS ch 0 triggers single channel"]
196    PRSCH0 = 0,
197    #[doc = "1: PRS ch 1 triggers single channel"]
198    PRSCH1 = 1,
199    #[doc = "2: PRS ch 2 triggers single channel"]
200    PRSCH2 = 2,
201    #[doc = "3: PRS ch 3 triggers single channel"]
202    PRSCH3 = 3,
203    #[doc = "4: PRS ch 4 triggers single channel"]
204    PRSCH4 = 4,
205    #[doc = "5: PRS ch 5 triggers single channel"]
206    PRSCH5 = 5,
207    #[doc = "6: PRS ch 6 triggers single channel"]
208    PRSCH6 = 6,
209    #[doc = "7: PRS ch 7 triggers single channel"]
210    PRSCH7 = 7,
211    #[doc = "8: PRS ch 8 triggers single channel"]
212    PRSCH8 = 8,
213    #[doc = "9: PRS ch 9 triggers single channel"]
214    PRSCH9 = 9,
215    #[doc = "10: PRS ch 10 triggers single channel"]
216    PRSCH10 = 10,
217    #[doc = "11: PRS ch 11 triggers single channel"]
218    PRSCH11 = 11,
219    #[doc = "12: PRS ch 12 triggers single channel"]
220    PRSCH12 = 12,
221    #[doc = "13: PRS ch 13 triggers single channel"]
222    PRSCH13 = 13,
223    #[doc = "14: PRS ch 14 triggers single channel"]
224    PRSCH14 = 14,
225    #[doc = "15: PRS ch 15 triggers single channel"]
226    PRSCH15 = 15,
227}
228impl From<PRSSEL_A> for u8 {
229    #[inline(always)]
230    fn from(variant: PRSSEL_A) -> Self {
231        variant as _
232    }
233}
234#[doc = "Field `PRSSEL` reader - Single Channel PRS Trigger Select"]
235pub type PRSSEL_R = crate::FieldReader<u8, PRSSEL_A>;
236impl PRSSEL_R {
237    #[doc = "Get enumerated values variant"]
238    #[inline(always)]
239    pub fn variant(&self) -> PRSSEL_A {
240        match self.bits {
241            0 => PRSSEL_A::PRSCH0,
242            1 => PRSSEL_A::PRSCH1,
243            2 => PRSSEL_A::PRSCH2,
244            3 => PRSSEL_A::PRSCH3,
245            4 => PRSSEL_A::PRSCH4,
246            5 => PRSSEL_A::PRSCH5,
247            6 => PRSSEL_A::PRSCH6,
248            7 => PRSSEL_A::PRSCH7,
249            8 => PRSSEL_A::PRSCH8,
250            9 => PRSSEL_A::PRSCH9,
251            10 => PRSSEL_A::PRSCH10,
252            11 => PRSSEL_A::PRSCH11,
253            12 => PRSSEL_A::PRSCH12,
254            13 => PRSSEL_A::PRSCH13,
255            14 => PRSSEL_A::PRSCH14,
256            15 => PRSSEL_A::PRSCH15,
257            _ => unreachable!(),
258        }
259    }
260    #[doc = "Checks if the value of the field is `PRSCH0`"]
261    #[inline(always)]
262    pub fn is_prsch0(&self) -> bool {
263        *self == PRSSEL_A::PRSCH0
264    }
265    #[doc = "Checks if the value of the field is `PRSCH1`"]
266    #[inline(always)]
267    pub fn is_prsch1(&self) -> bool {
268        *self == PRSSEL_A::PRSCH1
269    }
270    #[doc = "Checks if the value of the field is `PRSCH2`"]
271    #[inline(always)]
272    pub fn is_prsch2(&self) -> bool {
273        *self == PRSSEL_A::PRSCH2
274    }
275    #[doc = "Checks if the value of the field is `PRSCH3`"]
276    #[inline(always)]
277    pub fn is_prsch3(&self) -> bool {
278        *self == PRSSEL_A::PRSCH3
279    }
280    #[doc = "Checks if the value of the field is `PRSCH4`"]
281    #[inline(always)]
282    pub fn is_prsch4(&self) -> bool {
283        *self == PRSSEL_A::PRSCH4
284    }
285    #[doc = "Checks if the value of the field is `PRSCH5`"]
286    #[inline(always)]
287    pub fn is_prsch5(&self) -> bool {
288        *self == PRSSEL_A::PRSCH5
289    }
290    #[doc = "Checks if the value of the field is `PRSCH6`"]
291    #[inline(always)]
292    pub fn is_prsch6(&self) -> bool {
293        *self == PRSSEL_A::PRSCH6
294    }
295    #[doc = "Checks if the value of the field is `PRSCH7`"]
296    #[inline(always)]
297    pub fn is_prsch7(&self) -> bool {
298        *self == PRSSEL_A::PRSCH7
299    }
300    #[doc = "Checks if the value of the field is `PRSCH8`"]
301    #[inline(always)]
302    pub fn is_prsch8(&self) -> bool {
303        *self == PRSSEL_A::PRSCH8
304    }
305    #[doc = "Checks if the value of the field is `PRSCH9`"]
306    #[inline(always)]
307    pub fn is_prsch9(&self) -> bool {
308        *self == PRSSEL_A::PRSCH9
309    }
310    #[doc = "Checks if the value of the field is `PRSCH10`"]
311    #[inline(always)]
312    pub fn is_prsch10(&self) -> bool {
313        *self == PRSSEL_A::PRSCH10
314    }
315    #[doc = "Checks if the value of the field is `PRSCH11`"]
316    #[inline(always)]
317    pub fn is_prsch11(&self) -> bool {
318        *self == PRSSEL_A::PRSCH11
319    }
320    #[doc = "Checks if the value of the field is `PRSCH12`"]
321    #[inline(always)]
322    pub fn is_prsch12(&self) -> bool {
323        *self == PRSSEL_A::PRSCH12
324    }
325    #[doc = "Checks if the value of the field is `PRSCH13`"]
326    #[inline(always)]
327    pub fn is_prsch13(&self) -> bool {
328        *self == PRSSEL_A::PRSCH13
329    }
330    #[doc = "Checks if the value of the field is `PRSCH14`"]
331    #[inline(always)]
332    pub fn is_prsch14(&self) -> bool {
333        *self == PRSSEL_A::PRSCH14
334    }
335    #[doc = "Checks if the value of the field is `PRSCH15`"]
336    #[inline(always)]
337    pub fn is_prsch15(&self) -> bool {
338        *self == PRSSEL_A::PRSCH15
339    }
340}
341#[doc = "Field `PRSSEL` writer - Single Channel PRS Trigger Select"]
342pub type PRSSEL_W<'a> = crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, PRSSEL_A, 4, 17>;
343impl<'a> PRSSEL_W<'a> {
344    #[doc = "PRS ch 0 triggers single channel"]
345    #[inline(always)]
346    pub fn prsch0(self) -> &'a mut W {
347        self.variant(PRSSEL_A::PRSCH0)
348    }
349    #[doc = "PRS ch 1 triggers single channel"]
350    #[inline(always)]
351    pub fn prsch1(self) -> &'a mut W {
352        self.variant(PRSSEL_A::PRSCH1)
353    }
354    #[doc = "PRS ch 2 triggers single channel"]
355    #[inline(always)]
356    pub fn prsch2(self) -> &'a mut W {
357        self.variant(PRSSEL_A::PRSCH2)
358    }
359    #[doc = "PRS ch 3 triggers single channel"]
360    #[inline(always)]
361    pub fn prsch3(self) -> &'a mut W {
362        self.variant(PRSSEL_A::PRSCH3)
363    }
364    #[doc = "PRS ch 4 triggers single channel"]
365    #[inline(always)]
366    pub fn prsch4(self) -> &'a mut W {
367        self.variant(PRSSEL_A::PRSCH4)
368    }
369    #[doc = "PRS ch 5 triggers single channel"]
370    #[inline(always)]
371    pub fn prsch5(self) -> &'a mut W {
372        self.variant(PRSSEL_A::PRSCH5)
373    }
374    #[doc = "PRS ch 6 triggers single channel"]
375    #[inline(always)]
376    pub fn prsch6(self) -> &'a mut W {
377        self.variant(PRSSEL_A::PRSCH6)
378    }
379    #[doc = "PRS ch 7 triggers single channel"]
380    #[inline(always)]
381    pub fn prsch7(self) -> &'a mut W {
382        self.variant(PRSSEL_A::PRSCH7)
383    }
384    #[doc = "PRS ch 8 triggers single channel"]
385    #[inline(always)]
386    pub fn prsch8(self) -> &'a mut W {
387        self.variant(PRSSEL_A::PRSCH8)
388    }
389    #[doc = "PRS ch 9 triggers single channel"]
390    #[inline(always)]
391    pub fn prsch9(self) -> &'a mut W {
392        self.variant(PRSSEL_A::PRSCH9)
393    }
394    #[doc = "PRS ch 10 triggers single channel"]
395    #[inline(always)]
396    pub fn prsch10(self) -> &'a mut W {
397        self.variant(PRSSEL_A::PRSCH10)
398    }
399    #[doc = "PRS ch 11 triggers single channel"]
400    #[inline(always)]
401    pub fn prsch11(self) -> &'a mut W {
402        self.variant(PRSSEL_A::PRSCH11)
403    }
404    #[doc = "PRS ch 12 triggers single channel"]
405    #[inline(always)]
406    pub fn prsch12(self) -> &'a mut W {
407        self.variant(PRSSEL_A::PRSCH12)
408    }
409    #[doc = "PRS ch 13 triggers single channel"]
410    #[inline(always)]
411    pub fn prsch13(self) -> &'a mut W {
412        self.variant(PRSSEL_A::PRSCH13)
413    }
414    #[doc = "PRS ch 14 triggers single channel"]
415    #[inline(always)]
416    pub fn prsch14(self) -> &'a mut W {
417        self.variant(PRSSEL_A::PRSCH14)
418    }
419    #[doc = "PRS ch 15 triggers single channel"]
420    #[inline(always)]
421    pub fn prsch15(self) -> &'a mut W {
422        self.variant(PRSSEL_A::PRSCH15)
423    }
424}
425#[doc = "Field `CONVSTARTDELAY` reader - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
426pub type CONVSTARTDELAY_R = crate::FieldReader<u8, u8>;
427#[doc = "Field `CONVSTARTDELAY` writer - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
428pub type CONVSTARTDELAY_W<'a> = crate::FieldWriter<'a, u32, SINGLECTRLX_SPEC, u8, u8, 5, 22>;
429#[doc = "Field `CONVSTARTDELAYEN` reader - Enable Delaying Next Conversion Start"]
430pub type CONVSTARTDELAYEN_R = crate::BitReader<bool>;
431#[doc = "Field `CONVSTARTDELAYEN` writer - Enable Delaying Next Conversion Start"]
432pub type CONVSTARTDELAYEN_W<'a> = crate::BitWriter<'a, u32, SINGLECTRLX_SPEC, bool, 27>;
433#[doc = "REPDELAY Select for SINGLE REP Mode\n\nValue on reset: 0"]
434#[derive(Clone, Copy, Debug, PartialEq)]
435#[repr(u8)]
436pub enum REPDELAY_A {
437    #[doc = "0: No delay"]
438    NODELAY = 0,
439    #[doc = "1: 4 conversion clock cycles"]
440    _4CYCLES = 1,
441    #[doc = "2: 8 conversion clock cycles"]
442    _8CYCLES = 2,
443    #[doc = "3: 16 conversion clock cycles"]
444    _16CYCLES = 3,
445    #[doc = "4: 32 conversion clock cycles"]
446    _32CYCLES = 4,
447    #[doc = "5: 64 conversion clock cycles"]
448    _64CYCLES = 5,
449    #[doc = "6: 128 conversion clock cycles"]
450    _128CYCLES = 6,
451    #[doc = "7: 256 conversion clock cycles"]
452    _256CYCLES = 7,
453}
454impl From<REPDELAY_A> for u8 {
455    #[inline(always)]
456    fn from(variant: REPDELAY_A) -> Self {
457        variant as _
458    }
459}
460#[doc = "Field `REPDELAY` reader - REPDELAY Select for SINGLE REP Mode"]
461pub type REPDELAY_R = crate::FieldReader<u8, REPDELAY_A>;
462impl REPDELAY_R {
463    #[doc = "Get enumerated values variant"]
464    #[inline(always)]
465    pub fn variant(&self) -> REPDELAY_A {
466        match self.bits {
467            0 => REPDELAY_A::NODELAY,
468            1 => REPDELAY_A::_4CYCLES,
469            2 => REPDELAY_A::_8CYCLES,
470            3 => REPDELAY_A::_16CYCLES,
471            4 => REPDELAY_A::_32CYCLES,
472            5 => REPDELAY_A::_64CYCLES,
473            6 => REPDELAY_A::_128CYCLES,
474            7 => REPDELAY_A::_256CYCLES,
475            _ => unreachable!(),
476        }
477    }
478    #[doc = "Checks if the value of the field is `NODELAY`"]
479    #[inline(always)]
480    pub fn is_nodelay(&self) -> bool {
481        *self == REPDELAY_A::NODELAY
482    }
483    #[doc = "Checks if the value of the field is `_4CYCLES`"]
484    #[inline(always)]
485    pub fn is_4cycles(&self) -> bool {
486        *self == REPDELAY_A::_4CYCLES
487    }
488    #[doc = "Checks if the value of the field is `_8CYCLES`"]
489    #[inline(always)]
490    pub fn is_8cycles(&self) -> bool {
491        *self == REPDELAY_A::_8CYCLES
492    }
493    #[doc = "Checks if the value of the field is `_16CYCLES`"]
494    #[inline(always)]
495    pub fn is_16cycles(&self) -> bool {
496        *self == REPDELAY_A::_16CYCLES
497    }
498    #[doc = "Checks if the value of the field is `_32CYCLES`"]
499    #[inline(always)]
500    pub fn is_32cycles(&self) -> bool {
501        *self == REPDELAY_A::_32CYCLES
502    }
503    #[doc = "Checks if the value of the field is `_64CYCLES`"]
504    #[inline(always)]
505    pub fn is_64cycles(&self) -> bool {
506        *self == REPDELAY_A::_64CYCLES
507    }
508    #[doc = "Checks if the value of the field is `_128CYCLES`"]
509    #[inline(always)]
510    pub fn is_128cycles(&self) -> bool {
511        *self == REPDELAY_A::_128CYCLES
512    }
513    #[doc = "Checks if the value of the field is `_256CYCLES`"]
514    #[inline(always)]
515    pub fn is_256cycles(&self) -> bool {
516        *self == REPDELAY_A::_256CYCLES
517    }
518}
519#[doc = "Field `REPDELAY` writer - REPDELAY Select for SINGLE REP Mode"]
520pub type REPDELAY_W<'a> = crate::FieldWriterSafe<'a, u32, SINGLECTRLX_SPEC, u8, REPDELAY_A, 3, 29>;
521impl<'a> REPDELAY_W<'a> {
522    #[doc = "No delay"]
523    #[inline(always)]
524    pub fn nodelay(self) -> &'a mut W {
525        self.variant(REPDELAY_A::NODELAY)
526    }
527    #[doc = "4 conversion clock cycles"]
528    #[inline(always)]
529    pub fn _4cycles(self) -> &'a mut W {
530        self.variant(REPDELAY_A::_4CYCLES)
531    }
532    #[doc = "8 conversion clock cycles"]
533    #[inline(always)]
534    pub fn _8cycles(self) -> &'a mut W {
535        self.variant(REPDELAY_A::_8CYCLES)
536    }
537    #[doc = "16 conversion clock cycles"]
538    #[inline(always)]
539    pub fn _16cycles(self) -> &'a mut W {
540        self.variant(REPDELAY_A::_16CYCLES)
541    }
542    #[doc = "32 conversion clock cycles"]
543    #[inline(always)]
544    pub fn _32cycles(self) -> &'a mut W {
545        self.variant(REPDELAY_A::_32CYCLES)
546    }
547    #[doc = "64 conversion clock cycles"]
548    #[inline(always)]
549    pub fn _64cycles(self) -> &'a mut W {
550        self.variant(REPDELAY_A::_64CYCLES)
551    }
552    #[doc = "128 conversion clock cycles"]
553    #[inline(always)]
554    pub fn _128cycles(self) -> &'a mut W {
555        self.variant(REPDELAY_A::_128CYCLES)
556    }
557    #[doc = "256 conversion clock cycles"]
558    #[inline(always)]
559    pub fn _256cycles(self) -> &'a mut W {
560        self.variant(REPDELAY_A::_256CYCLES)
561    }
562}
563impl R {
564    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
565    #[inline(always)]
566    pub fn vrefsel(&self) -> VREFSEL_R {
567        VREFSEL_R::new((self.bits & 7) as u8)
568    }
569    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
570    #[inline(always)]
571    pub fn vrefattfix(&self) -> VREFATTFIX_R {
572        VREFATTFIX_R::new(((self.bits >> 3) & 1) != 0)
573    }
574    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
575    #[inline(always)]
576    pub fn vrefatt(&self) -> VREFATT_R {
577        VREFATT_R::new(((self.bits >> 4) & 0x0f) as u8)
578    }
579    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
580    #[inline(always)]
581    pub fn vinatt(&self) -> VINATT_R {
582        VINATT_R::new(((self.bits >> 8) & 0x0f) as u8)
583    }
584    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
585    #[inline(always)]
586    pub fn dvl(&self) -> DVL_R {
587        DVL_R::new(((self.bits >> 12) & 3) as u8)
588    }
589    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
590    #[inline(always)]
591    pub fn fifoofact(&self) -> FIFOOFACT_R {
592        FIFOOFACT_R::new(((self.bits >> 14) & 1) != 0)
593    }
594    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
595    #[inline(always)]
596    pub fn prsmode(&self) -> PRSMODE_R {
597        PRSMODE_R::new(((self.bits >> 16) & 1) != 0)
598    }
599    #[doc = "Bits 17:20 - Single Channel PRS Trigger Select"]
600    #[inline(always)]
601    pub fn prssel(&self) -> PRSSEL_R {
602        PRSSEL_R::new(((self.bits >> 17) & 0x0f) as u8)
603    }
604    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
605    #[inline(always)]
606    pub fn convstartdelay(&self) -> CONVSTARTDELAY_R {
607        CONVSTARTDELAY_R::new(((self.bits >> 22) & 0x1f) as u8)
608    }
609    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
610    #[inline(always)]
611    pub fn convstartdelayen(&self) -> CONVSTARTDELAYEN_R {
612        CONVSTARTDELAYEN_R::new(((self.bits >> 27) & 1) != 0)
613    }
614    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
615    #[inline(always)]
616    pub fn repdelay(&self) -> REPDELAY_R {
617        REPDELAY_R::new(((self.bits >> 29) & 7) as u8)
618    }
619}
620impl W {
621    #[doc = "Bits 0:2 - Single Channel Reference Selection"]
622    #[inline(always)]
623    pub fn vrefsel(&mut self) -> VREFSEL_W {
624        VREFSEL_W::new(self)
625    }
626    #[doc = "Bit 3 - Enable Fixed Scaling on VREF"]
627    #[inline(always)]
628    pub fn vrefattfix(&mut self) -> VREFATTFIX_W {
629        VREFATTFIX_W::new(self)
630    }
631    #[doc = "Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5"]
632    #[inline(always)]
633    pub fn vrefatt(&mut self) -> VREFATT_W {
634        VREFATT_W::new(self)
635    }
636    #[doc = "Bits 8:11 - Code for VIN Attenuation Factor"]
637    #[inline(always)]
638    pub fn vinatt(&mut self) -> VINATT_W {
639        VINATT_W::new(self)
640    }
641    #[doc = "Bits 12:13 - Single Channel DV Level Select"]
642    #[inline(always)]
643    pub fn dvl(&mut self) -> DVL_W {
644        DVL_W::new(self)
645    }
646    #[doc = "Bit 14 - Single Channel FIFO Overflow Action"]
647    #[inline(always)]
648    pub fn fifoofact(&mut self) -> FIFOOFACT_W {
649        FIFOOFACT_W::new(self)
650    }
651    #[doc = "Bit 16 - Single Channel PRS Trigger Mode"]
652    #[inline(always)]
653    pub fn prsmode(&mut self) -> PRSMODE_W {
654        PRSMODE_W::new(self)
655    }
656    #[doc = "Bits 17:20 - Single Channel PRS Trigger Select"]
657    #[inline(always)]
658    pub fn prssel(&mut self) -> PRSSEL_W {
659        PRSSEL_W::new(self)
660    }
661    #[doc = "Bits 22:26 - Delay Value for Next Conversion Start If CONVSTARTDELAYEN is Set"]
662    #[inline(always)]
663    pub fn convstartdelay(&mut self) -> CONVSTARTDELAY_W {
664        CONVSTARTDELAY_W::new(self)
665    }
666    #[doc = "Bit 27 - Enable Delaying Next Conversion Start"]
667    #[inline(always)]
668    pub fn convstartdelayen(&mut self) -> CONVSTARTDELAYEN_W {
669        CONVSTARTDELAYEN_W::new(self)
670    }
671    #[doc = "Bits 29:31 - REPDELAY Select for SINGLE REP Mode"]
672    #[inline(always)]
673    pub fn repdelay(&mut self) -> REPDELAY_W {
674        REPDELAY_W::new(self)
675    }
676    #[doc = "Writes raw bits to the register."]
677    #[inline(always)]
678    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
679        self.0.bits(bits);
680        self
681    }
682}
683#[doc = "Single Channel Control Register Continued\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [singlectrlx](index.html) module"]
684pub struct SINGLECTRLX_SPEC;
685impl crate::RegisterSpec for SINGLECTRLX_SPEC {
686    type Ux = u32;
687}
688#[doc = "`read()` method returns [singlectrlx::R](R) reader structure"]
689impl crate::Readable for SINGLECTRLX_SPEC {
690    type Reader = R;
691}
692#[doc = "`write(|w| ..)` method takes [singlectrlx::W](W) writer structure"]
693impl crate::Writable for SINGLECTRLX_SPEC {
694    type Writer = W;
695}
696#[doc = "`reset()` method sets SINGLECTRLX to value 0"]
697impl crate::Resettable for SINGLECTRLX_SPEC {
698    #[inline(always)]
699    fn reset_value() -> Self::Ux {
700        0
701    }
702}
efm32gg12b430_pac/adc0/singlectrlx.rs

efm32gg12b430_pac/adc0/
singlectrlx.rs
