efm32gg12b410_pac/usb/
grstctl.rs1#[doc = "Register `GRSTCTL` reader"]
2pub struct R(crate::R<GRSTCTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<GRSTCTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<GRSTCTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<GRSTCTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `GRSTCTL` writer"]
17pub struct W(crate::W<GRSTCTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<GRSTCTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<GRSTCTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<GRSTCTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CSFTRST` reader - Core Soft Reset (host and device)"]
38pub type CSFTRST_R = crate::BitReader<bool>;
39#[doc = "Field `CSFTRST` writer - Core Soft Reset (host and device)"]
40pub type CSFTRST_W<'a> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, 0>;
41#[doc = "Field `PIUFSSFTRST` reader - PIU FS Dedicated Controller Soft Reset"]
42pub type PIUFSSFTRST_R = crate::BitReader<bool>;
43#[doc = "Field `PIUFSSFTRST` writer - PIU FS Dedicated Controller Soft Reset"]
44pub type PIUFSSFTRST_W<'a> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, 1>;
45#[doc = "Field `FRMCNTRRST` reader - Host Frame Counter Reset"]
46pub type FRMCNTRRST_R = crate::BitReader<bool>;
47#[doc = "Field `FRMCNTRRST` writer - Host Frame Counter Reset"]
48pub type FRMCNTRRST_W<'a> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, 2>;
49#[doc = "Field `RXFFLSH` reader - RxFIFO Flush"]
50pub type RXFFLSH_R = crate::BitReader<bool>;
51#[doc = "Field `RXFFLSH` writer - RxFIFO Flush"]
52pub type RXFFLSH_W<'a> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, 4>;
53#[doc = "Field `TXFFLSH` reader - TxFIFO Flush"]
54pub type TXFFLSH_R = crate::BitReader<bool>;
55#[doc = "Field `TXFFLSH` writer - TxFIFO Flush"]
56pub type TXFFLSH_W<'a> = crate::BitWriter<'a, u32, GRSTCTL_SPEC, bool, 5>;
57#[doc = "TxFIFO Number (host and device)\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum TXFNUM_A {
61 #[doc = "0: Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush"]
62 F0 = 0,
63 #[doc = "1: Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush."]
64 F1 = 1,
65 #[doc = "2: Device mode: TXFIFO 2 flush."]
66 F2 = 2,
67 #[doc = "3: Device mode: TXFIFO 3 flush."]
68 F3 = 3,
69 #[doc = "4: Device mode: TXFIFO 4 flush."]
70 F4 = 4,
71 #[doc = "5: Device mode: TXFIFO 5 flush."]
72 F5 = 5,
73 #[doc = "6: Device mode: TXFIFO 6 flush."]
74 F6 = 6,
75 #[doc = "16: Flush all the transmit FIFOs in device or host mode."]
76 FALL = 16,
77}
78impl From<TXFNUM_A> for u8 {
79 #[inline(always)]
80 fn from(variant: TXFNUM_A) -> Self {
81 variant as _
82 }
83}
84#[doc = "Field `TXFNUM` reader - TxFIFO Number (host and device)"]
85pub type TXFNUM_R = crate::FieldReader<u8, TXFNUM_A>;
86impl TXFNUM_R {
87 #[doc = "Get enumerated values variant"]
88 #[inline(always)]
89 pub fn variant(&self) -> Option<TXFNUM_A> {
90 match self.bits {
91 0 => Some(TXFNUM_A::F0),
92 1 => Some(TXFNUM_A::F1),
93 2 => Some(TXFNUM_A::F2),
94 3 => Some(TXFNUM_A::F3),
95 4 => Some(TXFNUM_A::F4),
96 5 => Some(TXFNUM_A::F5),
97 6 => Some(TXFNUM_A::F6),
98 16 => Some(TXFNUM_A::FALL),
99 _ => None,
100 }
101 }
102 #[doc = "Checks if the value of the field is `F0`"]
103 #[inline(always)]
104 pub fn is_f0(&self) -> bool {
105 *self == TXFNUM_A::F0
106 }
107 #[doc = "Checks if the value of the field is `F1`"]
108 #[inline(always)]
109 pub fn is_f1(&self) -> bool {
110 *self == TXFNUM_A::F1
111 }
112 #[doc = "Checks if the value of the field is `F2`"]
113 #[inline(always)]
114 pub fn is_f2(&self) -> bool {
115 *self == TXFNUM_A::F2
116 }
117 #[doc = "Checks if the value of the field is `F3`"]
118 #[inline(always)]
119 pub fn is_f3(&self) -> bool {
120 *self == TXFNUM_A::F3
121 }
122 #[doc = "Checks if the value of the field is `F4`"]
123 #[inline(always)]
124 pub fn is_f4(&self) -> bool {
125 *self == TXFNUM_A::F4
126 }
127 #[doc = "Checks if the value of the field is `F5`"]
128 #[inline(always)]
129 pub fn is_f5(&self) -> bool {
130 *self == TXFNUM_A::F5
131 }
132 #[doc = "Checks if the value of the field is `F6`"]
133 #[inline(always)]
134 pub fn is_f6(&self) -> bool {
135 *self == TXFNUM_A::F6
136 }
137 #[doc = "Checks if the value of the field is `FALL`"]
138 #[inline(always)]
139 pub fn is_fall(&self) -> bool {
140 *self == TXFNUM_A::FALL
141 }
142}
143#[doc = "Field `TXFNUM` writer - TxFIFO Number (host and device)"]
144pub type TXFNUM_W<'a> = crate::FieldWriter<'a, u32, GRSTCTL_SPEC, u8, TXFNUM_A, 5, 6>;
145impl<'a> TXFNUM_W<'a> {
146 #[doc = "Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush"]
147 #[inline(always)]
148 pub fn f0(self) -> &'a mut W {
149 self.variant(TXFNUM_A::F0)
150 }
151 #[doc = "Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush."]
152 #[inline(always)]
153 pub fn f1(self) -> &'a mut W {
154 self.variant(TXFNUM_A::F1)
155 }
156 #[doc = "Device mode: TXFIFO 2 flush."]
157 #[inline(always)]
158 pub fn f2(self) -> &'a mut W {
159 self.variant(TXFNUM_A::F2)
160 }
161 #[doc = "Device mode: TXFIFO 3 flush."]
162 #[inline(always)]
163 pub fn f3(self) -> &'a mut W {
164 self.variant(TXFNUM_A::F3)
165 }
166 #[doc = "Device mode: TXFIFO 4 flush."]
167 #[inline(always)]
168 pub fn f4(self) -> &'a mut W {
169 self.variant(TXFNUM_A::F4)
170 }
171 #[doc = "Device mode: TXFIFO 5 flush."]
172 #[inline(always)]
173 pub fn f5(self) -> &'a mut W {
174 self.variant(TXFNUM_A::F5)
175 }
176 #[doc = "Device mode: TXFIFO 6 flush."]
177 #[inline(always)]
178 pub fn f6(self) -> &'a mut W {
179 self.variant(TXFNUM_A::F6)
180 }
181 #[doc = "Flush all the transmit FIFOs in device or host mode."]
182 #[inline(always)]
183 pub fn fall(self) -> &'a mut W {
184 self.variant(TXFNUM_A::FALL)
185 }
186}
187#[doc = "Field `DMAREQ` reader - DMA Request Signal"]
188pub type DMAREQ_R = crate::BitReader<bool>;
189#[doc = "Field `AHBIDLE` reader - AHB Master Idle"]
190pub type AHBIDLE_R = crate::BitReader<bool>;
191impl R {
192 #[doc = "Bit 0 - Core Soft Reset (host and device)"]
193 #[inline(always)]
194 pub fn csftrst(&self) -> CSFTRST_R {
195 CSFTRST_R::new((self.bits & 1) != 0)
196 }
197 #[doc = "Bit 1 - PIU FS Dedicated Controller Soft Reset"]
198 #[inline(always)]
199 pub fn piufssftrst(&self) -> PIUFSSFTRST_R {
200 PIUFSSFTRST_R::new(((self.bits >> 1) & 1) != 0)
201 }
202 #[doc = "Bit 2 - Host Frame Counter Reset"]
203 #[inline(always)]
204 pub fn frmcntrrst(&self) -> FRMCNTRRST_R {
205 FRMCNTRRST_R::new(((self.bits >> 2) & 1) != 0)
206 }
207 #[doc = "Bit 4 - RxFIFO Flush"]
208 #[inline(always)]
209 pub fn rxfflsh(&self) -> RXFFLSH_R {
210 RXFFLSH_R::new(((self.bits >> 4) & 1) != 0)
211 }
212 #[doc = "Bit 5 - TxFIFO Flush"]
213 #[inline(always)]
214 pub fn txfflsh(&self) -> TXFFLSH_R {
215 TXFFLSH_R::new(((self.bits >> 5) & 1) != 0)
216 }
217 #[doc = "Bits 6:10 - TxFIFO Number (host and device)"]
218 #[inline(always)]
219 pub fn txfnum(&self) -> TXFNUM_R {
220 TXFNUM_R::new(((self.bits >> 6) & 0x1f) as u8)
221 }
222 #[doc = "Bit 30 - DMA Request Signal"]
223 #[inline(always)]
224 pub fn dmareq(&self) -> DMAREQ_R {
225 DMAREQ_R::new(((self.bits >> 30) & 1) != 0)
226 }
227 #[doc = "Bit 31 - AHB Master Idle"]
228 #[inline(always)]
229 pub fn ahbidle(&self) -> AHBIDLE_R {
230 AHBIDLE_R::new(((self.bits >> 31) & 1) != 0)
231 }
232}
233impl W {
234 #[doc = "Bit 0 - Core Soft Reset (host and device)"]
235 #[inline(always)]
236 pub fn csftrst(&mut self) -> CSFTRST_W {
237 CSFTRST_W::new(self)
238 }
239 #[doc = "Bit 1 - PIU FS Dedicated Controller Soft Reset"]
240 #[inline(always)]
241 pub fn piufssftrst(&mut self) -> PIUFSSFTRST_W {
242 PIUFSSFTRST_W::new(self)
243 }
244 #[doc = "Bit 2 - Host Frame Counter Reset"]
245 #[inline(always)]
246 pub fn frmcntrrst(&mut self) -> FRMCNTRRST_W {
247 FRMCNTRRST_W::new(self)
248 }
249 #[doc = "Bit 4 - RxFIFO Flush"]
250 #[inline(always)]
251 pub fn rxfflsh(&mut self) -> RXFFLSH_W {
252 RXFFLSH_W::new(self)
253 }
254 #[doc = "Bit 5 - TxFIFO Flush"]
255 #[inline(always)]
256 pub fn txfflsh(&mut self) -> TXFFLSH_W {
257 TXFFLSH_W::new(self)
258 }
259 #[doc = "Bits 6:10 - TxFIFO Number (host and device)"]
260 #[inline(always)]
261 pub fn txfnum(&mut self) -> TXFNUM_W {
262 TXFNUM_W::new(self)
263 }
264 #[doc = "Writes raw bits to the register."]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267 self.0.bits(bits);
268 self
269 }
270}
271#[doc = "Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](index.html) module"]
272pub struct GRSTCTL_SPEC;
273impl crate::RegisterSpec for GRSTCTL_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [grstctl::R](R) reader structure"]
277impl crate::Readable for GRSTCTL_SPEC {
278 type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [grstctl::W](W) writer structure"]
281impl crate::Writable for GRSTCTL_SPEC {
282 type Writer = W;
283}
284#[doc = "`reset()` method sets GRSTCTL to value 0x8000_0000"]
285impl crate::Resettable for GRSTCTL_SPEC {
286 #[inline(always)]
287 fn reset_value() -> Self::Ux {
288 0x8000_0000
289 }
290}