efm32gg12b410_pac/usb/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VBUSENAP` reader - VBUSEN Active Polarity"]
38pub type VBUSENAP_R = crate::BitReader<bool>;
39#[doc = "Field `VBUSENAP` writer - VBUSEN Active Polarity"]
40pub type VBUSENAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `SELFPOWERED` reader - PHY Power"]
42pub type SELFPOWERED_R = crate::BitReader<bool>;
43#[doc = "Field `SELFPOWERED` writer - PHY Power"]
44pub type SELFPOWERED_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
45#[doc = "Low Energy Mode Oscillator Control\n\nValue on reset: 2"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47#[repr(u8)]
48pub enum LEMOSCCTRL_A {
49    #[doc = "0: Low Energy Mode has no effect on neither USBC or USHFRCO."]
50    NONE = 0,
51    #[doc = "1: The USBC clock is gated when Low Energy Mode is active."]
52    GATE = 1,
53}
54impl From<LEMOSCCTRL_A> for u8 {
55    #[inline(always)]
56    fn from(variant: LEMOSCCTRL_A) -> Self {
57        variant as _
58    }
59}
60#[doc = "Field `LEMOSCCTRL` reader - Low Energy Mode Oscillator Control"]
61pub type LEMOSCCTRL_R = crate::FieldReader<u8, LEMOSCCTRL_A>;
62impl LEMOSCCTRL_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> Option<LEMOSCCTRL_A> {
66        match self.bits {
67            0 => Some(LEMOSCCTRL_A::NONE),
68            1 => Some(LEMOSCCTRL_A::GATE),
69            _ => None,
70        }
71    }
72    #[doc = "Checks if the value of the field is `NONE`"]
73    #[inline(always)]
74    pub fn is_none(&self) -> bool {
75        *self == LEMOSCCTRL_A::NONE
76    }
77    #[doc = "Checks if the value of the field is `GATE`"]
78    #[inline(always)]
79    pub fn is_gate(&self) -> bool {
80        *self == LEMOSCCTRL_A::GATE
81    }
82}
83#[doc = "Field `LEMOSCCTRL` writer - Low Energy Mode Oscillator Control"]
84pub type LEMOSCCTRL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, LEMOSCCTRL_A, 2, 4>;
85impl<'a> LEMOSCCTRL_W<'a> {
86    #[doc = "Low Energy Mode has no effect on neither USBC or USHFRCO."]
87    #[inline(always)]
88    pub fn none(self) -> &'a mut W {
89        self.variant(LEMOSCCTRL_A::NONE)
90    }
91    #[doc = "The USBC clock is gated when Low Energy Mode is active."]
92    #[inline(always)]
93    pub fn gate(self) -> &'a mut W {
94        self.variant(LEMOSCCTRL_A::GATE)
95    }
96}
97#[doc = "Field `LEMPHYCTRL` reader - Low Energy Mode USB PHY Control"]
98pub type LEMPHYCTRL_R = crate::BitReader<bool>;
99#[doc = "Field `LEMPHYCTRL` writer - Low Energy Mode USB PHY Control"]
100pub type LEMPHYCTRL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 7>;
101#[doc = "Field `LEMIDLEEN` reader - Low Energy Mode on Bus Idle Enable"]
102pub type LEMIDLEEN_R = crate::BitReader<bool>;
103#[doc = "Field `LEMIDLEEN` writer - Low Energy Mode on Bus Idle Enable"]
104pub type LEMIDLEEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
105#[doc = "Field `IDCDEN` reader - ID Pull-up Enable"]
106pub type IDCDEN_R = crate::BitReader<bool>;
107#[doc = "Field `IDCDEN` writer - ID Pull-up Enable"]
108pub type IDCDEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
109#[doc = "Field `OTGCLKCDIS` reader - OTG CLKC Disable"]
110pub type OTGCLKCDIS_R = crate::BitReader<bool>;
111#[doc = "Field `OTGCLKCDIS` writer - OTG CLKC Disable"]
112pub type OTGCLKCDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 25>;
113#[doc = "Field `OTGIDINDIS` reader - OTG ID Input Disable"]
114pub type OTGIDINDIS_R = crate::BitReader<bool>;
115#[doc = "Field `OTGIDINDIS` writer - OTG ID Input Disable"]
116pub type OTGIDINDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 26>;
117#[doc = "Field `OTGPHYCTRLDIS` reader - OTG Control Signals to PHY Disable"]
118pub type OTGPHYCTRLDIS_R = crate::BitReader<bool>;
119#[doc = "Field `OTGPHYCTRLDIS` writer - OTG Control Signals to PHY Disable"]
120pub type OTGPHYCTRLDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 27>;
121#[doc = "Data Contact Detection Enable\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123#[repr(u8)]
124pub enum DCDEN_A {
125    #[doc = "0: DCD is disabled."]
126    DISABLED = 0,
127    #[doc = "2: Only DCD timeout will be initiated."]
128    TIMEOUT = 2,
129    #[doc = "3: Full DCD operation (physical contact and timeout) will be initiated."]
130    ENABLED = 3,
131}
132impl From<DCDEN_A> for u8 {
133    #[inline(always)]
134    fn from(variant: DCDEN_A) -> Self {
135        variant as _
136    }
137}
138#[doc = "Field `DCDEN` reader - Data Contact Detection Enable"]
139pub type DCDEN_R = crate::FieldReader<u8, DCDEN_A>;
140impl DCDEN_R {
141    #[doc = "Get enumerated values variant"]
142    #[inline(always)]
143    pub fn variant(&self) -> Option<DCDEN_A> {
144        match self.bits {
145            0 => Some(DCDEN_A::DISABLED),
146            2 => Some(DCDEN_A::TIMEOUT),
147            3 => Some(DCDEN_A::ENABLED),
148            _ => None,
149        }
150    }
151    #[doc = "Checks if the value of the field is `DISABLED`"]
152    #[inline(always)]
153    pub fn is_disabled(&self) -> bool {
154        *self == DCDEN_A::DISABLED
155    }
156    #[doc = "Checks if the value of the field is `TIMEOUT`"]
157    #[inline(always)]
158    pub fn is_timeout(&self) -> bool {
159        *self == DCDEN_A::TIMEOUT
160    }
161    #[doc = "Checks if the value of the field is `ENABLED`"]
162    #[inline(always)]
163    pub fn is_enabled(&self) -> bool {
164        *self == DCDEN_A::ENABLED
165    }
166}
167#[doc = "Field `DCDEN` writer - Data Contact Detection Enable"]
168pub type DCDEN_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, DCDEN_A, 2, 28>;
169impl<'a> DCDEN_W<'a> {
170    #[doc = "DCD is disabled."]
171    #[inline(always)]
172    pub fn disabled(self) -> &'a mut W {
173        self.variant(DCDEN_A::DISABLED)
174    }
175    #[doc = "Only DCD timeout will be initiated."]
176    #[inline(always)]
177    pub fn timeout(self) -> &'a mut W {
178        self.variant(DCDEN_A::TIMEOUT)
179    }
180    #[doc = "Full DCD operation (physical contact and timeout) will be initiated."]
181    #[inline(always)]
182    pub fn enabled(self) -> &'a mut W {
183        self.variant(DCDEN_A::ENABLED)
184    }
185}
186#[doc = "Field `PDEN` reader - Primary Detection Enable"]
187pub type PDEN_R = crate::BitReader<bool>;
188#[doc = "Field `PDEN` writer - Primary Detection Enable"]
189pub type PDEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 30>;
190#[doc = "Field `SDEN` reader - Secondary Detection Enable"]
191pub type SDEN_R = crate::BitReader<bool>;
192#[doc = "Field `SDEN` writer - Secondary Detection Enable"]
193pub type SDEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
194impl R {
195    #[doc = "Bit 0 - VBUSEN Active Polarity"]
196    #[inline(always)]
197    pub fn vbusenap(&self) -> VBUSENAP_R {
198        VBUSENAP_R::new((self.bits & 1) != 0)
199    }
200    #[doc = "Bit 3 - PHY Power"]
201    #[inline(always)]
202    pub fn selfpowered(&self) -> SELFPOWERED_R {
203        SELFPOWERED_R::new(((self.bits >> 3) & 1) != 0)
204    }
205    #[doc = "Bits 4:5 - Low Energy Mode Oscillator Control"]
206    #[inline(always)]
207    pub fn lemoscctrl(&self) -> LEMOSCCTRL_R {
208        LEMOSCCTRL_R::new(((self.bits >> 4) & 3) as u8)
209    }
210    #[doc = "Bit 7 - Low Energy Mode USB PHY Control"]
211    #[inline(always)]
212    pub fn lemphyctrl(&self) -> LEMPHYCTRL_R {
213        LEMPHYCTRL_R::new(((self.bits >> 7) & 1) != 0)
214    }
215    #[doc = "Bit 9 - Low Energy Mode on Bus Idle Enable"]
216    #[inline(always)]
217    pub fn lemidleen(&self) -> LEMIDLEEN_R {
218        LEMIDLEEN_R::new(((self.bits >> 9) & 1) != 0)
219    }
220    #[doc = "Bit 12 - ID Pull-up Enable"]
221    #[inline(always)]
222    pub fn idcden(&self) -> IDCDEN_R {
223        IDCDEN_R::new(((self.bits >> 12) & 1) != 0)
224    }
225    #[doc = "Bit 25 - OTG CLKC Disable"]
226    #[inline(always)]
227    pub fn otgclkcdis(&self) -> OTGCLKCDIS_R {
228        OTGCLKCDIS_R::new(((self.bits >> 25) & 1) != 0)
229    }
230    #[doc = "Bit 26 - OTG ID Input Disable"]
231    #[inline(always)]
232    pub fn otgidindis(&self) -> OTGIDINDIS_R {
233        OTGIDINDIS_R::new(((self.bits >> 26) & 1) != 0)
234    }
235    #[doc = "Bit 27 - OTG Control Signals to PHY Disable"]
236    #[inline(always)]
237    pub fn otgphyctrldis(&self) -> OTGPHYCTRLDIS_R {
238        OTGPHYCTRLDIS_R::new(((self.bits >> 27) & 1) != 0)
239    }
240    #[doc = "Bits 28:29 - Data Contact Detection Enable"]
241    #[inline(always)]
242    pub fn dcden(&self) -> DCDEN_R {
243        DCDEN_R::new(((self.bits >> 28) & 3) as u8)
244    }
245    #[doc = "Bit 30 - Primary Detection Enable"]
246    #[inline(always)]
247    pub fn pden(&self) -> PDEN_R {
248        PDEN_R::new(((self.bits >> 30) & 1) != 0)
249    }
250    #[doc = "Bit 31 - Secondary Detection Enable"]
251    #[inline(always)]
252    pub fn sden(&self) -> SDEN_R {
253        SDEN_R::new(((self.bits >> 31) & 1) != 0)
254    }
255}
256impl W {
257    #[doc = "Bit 0 - VBUSEN Active Polarity"]
258    #[inline(always)]
259    pub fn vbusenap(&mut self) -> VBUSENAP_W {
260        VBUSENAP_W::new(self)
261    }
262    #[doc = "Bit 3 - PHY Power"]
263    #[inline(always)]
264    pub fn selfpowered(&mut self) -> SELFPOWERED_W {
265        SELFPOWERED_W::new(self)
266    }
267    #[doc = "Bits 4:5 - Low Energy Mode Oscillator Control"]
268    #[inline(always)]
269    pub fn lemoscctrl(&mut self) -> LEMOSCCTRL_W {
270        LEMOSCCTRL_W::new(self)
271    }
272    #[doc = "Bit 7 - Low Energy Mode USB PHY Control"]
273    #[inline(always)]
274    pub fn lemphyctrl(&mut self) -> LEMPHYCTRL_W {
275        LEMPHYCTRL_W::new(self)
276    }
277    #[doc = "Bit 9 - Low Energy Mode on Bus Idle Enable"]
278    #[inline(always)]
279    pub fn lemidleen(&mut self) -> LEMIDLEEN_W {
280        LEMIDLEEN_W::new(self)
281    }
282    #[doc = "Bit 12 - ID Pull-up Enable"]
283    #[inline(always)]
284    pub fn idcden(&mut self) -> IDCDEN_W {
285        IDCDEN_W::new(self)
286    }
287    #[doc = "Bit 25 - OTG CLKC Disable"]
288    #[inline(always)]
289    pub fn otgclkcdis(&mut self) -> OTGCLKCDIS_W {
290        OTGCLKCDIS_W::new(self)
291    }
292    #[doc = "Bit 26 - OTG ID Input Disable"]
293    #[inline(always)]
294    pub fn otgidindis(&mut self) -> OTGIDINDIS_W {
295        OTGIDINDIS_W::new(self)
296    }
297    #[doc = "Bit 27 - OTG Control Signals to PHY Disable"]
298    #[inline(always)]
299    pub fn otgphyctrldis(&mut self) -> OTGPHYCTRLDIS_W {
300        OTGPHYCTRLDIS_W::new(self)
301    }
302    #[doc = "Bits 28:29 - Data Contact Detection Enable"]
303    #[inline(always)]
304    pub fn dcden(&mut self) -> DCDEN_W {
305        DCDEN_W::new(self)
306    }
307    #[doc = "Bit 30 - Primary Detection Enable"]
308    #[inline(always)]
309    pub fn pden(&mut self) -> PDEN_W {
310        PDEN_W::new(self)
311    }
312    #[doc = "Bit 31 - Secondary Detection Enable"]
313    #[inline(always)]
314    pub fn sden(&mut self) -> SDEN_W {
315        SDEN_W::new(self)
316    }
317    #[doc = "Writes raw bits to the register."]
318    #[inline(always)]
319    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
320        self.0.bits(bits);
321        self
322    }
323}
324#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
325pub struct CTRL_SPEC;
326impl crate::RegisterSpec for CTRL_SPEC {
327    type Ux = u32;
328}
329#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
330impl crate::Readable for CTRL_SPEC {
331    type Reader = R;
332}
333#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
334impl crate::Writable for CTRL_SPEC {
335    type Writer = W;
336}
337#[doc = "`reset()` method sets CTRL to value 0x20"]
338impl crate::Resettable for CTRL_SPEC {
339    #[inline(always)]
340    fn reset_value() -> Self::Ux {
341        0x20
342    }
343}
efm32gg12b410_pac/usb/ctrl.rs

efm32gg12b410_pac/usb/
ctrl.rs
