1#[doc = "Register `IFENC` reader"]
2pub struct R(crate::R<IFENC_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IFENC_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IFENC_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IFENC_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IFENC` writer"]
17pub struct W(crate::W<IFENC_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IFENC_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IFENC_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IFENC_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CMDCOMEN` reader - Command Complete Signal Enable"]
38pub type CMDCOMEN_R = crate::BitReader<bool>;
39#[doc = "Field `CMDCOMEN` writer - Command Complete Signal Enable"]
40pub type CMDCOMEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 0>;
41#[doc = "Field `TRANCOMEN` reader - Transfer Complete Signal Enable"]
42pub type TRANCOMEN_R = crate::BitReader<bool>;
43#[doc = "Field `TRANCOMEN` writer - Transfer Complete Signal Enable"]
44pub type TRANCOMEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 1>;
45#[doc = "Field `BLKGAPEVTEN` reader - Block Gap Event Signal Enable"]
46pub type BLKGAPEVTEN_R = crate::BitReader<bool>;
47#[doc = "Field `BLKGAPEVTEN` writer - Block Gap Event Signal Enable"]
48pub type BLKGAPEVTEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 2>;
49#[doc = "Field `DMAINTEN` reader - DMA Interrupt Signal Enable"]
50pub type DMAINTEN_R = crate::BitReader<bool>;
51#[doc = "Field `DMAINTEN` writer - DMA Interrupt Signal Enable"]
52pub type DMAINTEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 3>;
53#[doc = "Field `BUFWRRDYEN` reader - Buffer Write Ready Signal Enable"]
54pub type BUFWRRDYEN_R = crate::BitReader<bool>;
55#[doc = "Field `BUFWRRDYEN` writer - Buffer Write Ready Signal Enable"]
56pub type BUFWRRDYEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 4>;
57#[doc = "Field `BUFRDRDYEN` reader - Buffer Read Ready Signal Enable"]
58pub type BUFRDRDYEN_R = crate::BitReader<bool>;
59#[doc = "Field `BUFRDRDYEN` writer - Buffer Read Ready Signal Enable"]
60pub type BUFRDRDYEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 5>;
61#[doc = "Field `CARDINSEN` reader - Card Insertion Signal Enable"]
62pub type CARDINSEN_R = crate::BitReader<bool>;
63#[doc = "Field `CARDINSEN` writer - Card Insertion Signal Enable"]
64pub type CARDINSEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 6>;
65#[doc = "Field `CARDRMEN` reader - Card Removal Signal Enable"]
66pub type CARDRMEN_R = crate::BitReader<bool>;
67#[doc = "Field `CARDRMEN` writer - Card Removal Signal Enable"]
68pub type CARDRMEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 7>;
69#[doc = "Field `CARDINTEN` reader - Card Interrupt Signal Enable"]
70pub type CARDINTEN_R = crate::BitReader<bool>;
71#[doc = "Field `CARDINTEN` writer - Card Interrupt Signal Enable"]
72pub type CARDINTEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 8>;
73#[doc = "Field `RETUNINGEVTEN` reader - Re-Tunning Event Signal Enable"]
74pub type RETUNINGEVTEN_R = crate::BitReader<bool>;
75#[doc = "Field `RETUNINGEVTEN` writer - Re-Tunning Event Signal Enable"]
76pub type RETUNINGEVTEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 12>;
77#[doc = "Field `BOOTACKRCVEN` reader - Boot Ack Received Signal Enable"]
78pub type BOOTACKRCVEN_R = crate::BitReader<bool>;
79#[doc = "Field `BOOTACKRCVEN` writer - Boot Ack Received Signal Enable"]
80pub type BOOTACKRCVEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 13>;
81#[doc = "Field `BOOTTERMINATEEN` reader - Boot Terminate Interrupt Signal Enable"]
82pub type BOOTTERMINATEEN_R = crate::BitReader<bool>;
83#[doc = "Field `BOOTTERMINATEEN` writer - Boot Terminate Interrupt Signal Enable"]
84pub type BOOTTERMINATEEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 14>;
85#[doc = "Field `CMDTOUTERREN` reader - Command Time-out Error Status Enable"]
86pub type CMDTOUTERREN_R = crate::BitReader<bool>;
87#[doc = "Field `CMDTOUTERREN` writer - Command Time-out Error Status Enable"]
88pub type CMDTOUTERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 16>;
89#[doc = "Field `CMDCRCERREN` reader - Command CRC Error Status Enable"]
90pub type CMDCRCERREN_R = crate::BitReader<bool>;
91#[doc = "Field `CMDCRCERREN` writer - Command CRC Error Status Enable"]
92pub type CMDCRCERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 17>;
93#[doc = "Field `CMDENDBITERREN` reader - Command End Bit Error Status Enable"]
94pub type CMDENDBITERREN_R = crate::BitReader<bool>;
95#[doc = "Field `CMDENDBITERREN` writer - Command End Bit Error Status Enable"]
96pub type CMDENDBITERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 18>;
97#[doc = "Field `CMDINDEXERREN` reader - Command Index Error Status Enable"]
98pub type CMDINDEXERREN_R = crate::BitReader<bool>;
99#[doc = "Field `CMDINDEXERREN` writer - Command Index Error Status Enable"]
100pub type CMDINDEXERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 19>;
101#[doc = "Field `DATTOUTERREN` reader - Data Timeout Error Status Enable"]
102pub type DATTOUTERREN_R = crate::BitReader<bool>;
103#[doc = "Field `DATTOUTERREN` writer - Data Timeout Error Status Enable"]
104pub type DATTOUTERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 20>;
105#[doc = "Field `DATCRCERREN` reader - Data CRC Error Status Enable"]
106pub type DATCRCERREN_R = crate::BitReader<bool>;
107#[doc = "Field `DATCRCERREN` writer - Data CRC Error Status Enable"]
108pub type DATCRCERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 21>;
109#[doc = "Field `DATENDBITERREN` reader - Data End Bit Error Status Enable"]
110pub type DATENDBITERREN_R = crate::BitReader<bool>;
111#[doc = "Field `DATENDBITERREN` writer - Data End Bit Error Status Enable"]
112pub type DATENDBITERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 22>;
113#[doc = "Field `CURRENTLIMITERREN` reader - Current Limit Error Status Enable"]
114pub type CURRENTLIMITERREN_R = crate::BitReader<bool>;
115#[doc = "Field `CURRENTLIMITERREN` writer - Current Limit Error Status Enable"]
116pub type CURRENTLIMITERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 23>;
117#[doc = "Field `AUTOCMDERREN` reader - Auto CMD12 Error Status Enable"]
118pub type AUTOCMDERREN_R = crate::BitReader<bool>;
119#[doc = "Field `AUTOCMDERREN` writer - Auto CMD12 Error Status Enable"]
120pub type AUTOCMDERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 24>;
121#[doc = "Field `ADMAERREN` reader - ADMA Error Status Enable"]
122pub type ADMAERREN_R = crate::BitReader<bool>;
123#[doc = "Field `ADMAERREN` writer - ADMA Error Status Enable"]
124pub type ADMAERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 25>;
125#[doc = "Field `TUNINGERREN` reader - Tuning Error Status Enable"]
126pub type TUNINGERREN_R = crate::BitReader<bool>;
127#[doc = "Field `TUNINGERREN` writer - Tuning Error Status Enable"]
128pub type TUNINGERREN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 26>;
129#[doc = "Field `TARGETRESPEN` reader - Target Response/Host Error Status Enable"]
130pub type TARGETRESPEN_R = crate::BitReader<bool>;
131#[doc = "Field `TARGETRESPEN` writer - Target Response/Host Error Status Enable"]
132pub type TARGETRESPEN_W<'a> = crate::BitWriter<'a, u32, IFENC_SPEC, bool, 28>;
133impl R {
134 #[doc = "Bit 0 - Command Complete Signal Enable"]
135 #[inline(always)]
136 pub fn cmdcomen(&self) -> CMDCOMEN_R {
137 CMDCOMEN_R::new((self.bits & 1) != 0)
138 }
139 #[doc = "Bit 1 - Transfer Complete Signal Enable"]
140 #[inline(always)]
141 pub fn trancomen(&self) -> TRANCOMEN_R {
142 TRANCOMEN_R::new(((self.bits >> 1) & 1) != 0)
143 }
144 #[doc = "Bit 2 - Block Gap Event Signal Enable"]
145 #[inline(always)]
146 pub fn blkgapevten(&self) -> BLKGAPEVTEN_R {
147 BLKGAPEVTEN_R::new(((self.bits >> 2) & 1) != 0)
148 }
149 #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
150 #[inline(always)]
151 pub fn dmainten(&self) -> DMAINTEN_R {
152 DMAINTEN_R::new(((self.bits >> 3) & 1) != 0)
153 }
154 #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
155 #[inline(always)]
156 pub fn bufwrrdyen(&self) -> BUFWRRDYEN_R {
157 BUFWRRDYEN_R::new(((self.bits >> 4) & 1) != 0)
158 }
159 #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
160 #[inline(always)]
161 pub fn bufrdrdyen(&self) -> BUFRDRDYEN_R {
162 BUFRDRDYEN_R::new(((self.bits >> 5) & 1) != 0)
163 }
164 #[doc = "Bit 6 - Card Insertion Signal Enable"]
165 #[inline(always)]
166 pub fn cardinsen(&self) -> CARDINSEN_R {
167 CARDINSEN_R::new(((self.bits >> 6) & 1) != 0)
168 }
169 #[doc = "Bit 7 - Card Removal Signal Enable"]
170 #[inline(always)]
171 pub fn cardrmen(&self) -> CARDRMEN_R {
172 CARDRMEN_R::new(((self.bits >> 7) & 1) != 0)
173 }
174 #[doc = "Bit 8 - Card Interrupt Signal Enable"]
175 #[inline(always)]
176 pub fn cardinten(&self) -> CARDINTEN_R {
177 CARDINTEN_R::new(((self.bits >> 8) & 1) != 0)
178 }
179 #[doc = "Bit 12 - Re-Tunning Event Signal Enable"]
180 #[inline(always)]
181 pub fn retuningevten(&self) -> RETUNINGEVTEN_R {
182 RETUNINGEVTEN_R::new(((self.bits >> 12) & 1) != 0)
183 }
184 #[doc = "Bit 13 - Boot Ack Received Signal Enable"]
185 #[inline(always)]
186 pub fn bootackrcven(&self) -> BOOTACKRCVEN_R {
187 BOOTACKRCVEN_R::new(((self.bits >> 13) & 1) != 0)
188 }
189 #[doc = "Bit 14 - Boot Terminate Interrupt Signal Enable"]
190 #[inline(always)]
191 pub fn bootterminateen(&self) -> BOOTTERMINATEEN_R {
192 BOOTTERMINATEEN_R::new(((self.bits >> 14) & 1) != 0)
193 }
194 #[doc = "Bit 16 - Command Time-out Error Status Enable"]
195 #[inline(always)]
196 pub fn cmdtouterren(&self) -> CMDTOUTERREN_R {
197 CMDTOUTERREN_R::new(((self.bits >> 16) & 1) != 0)
198 }
199 #[doc = "Bit 17 - Command CRC Error Status Enable"]
200 #[inline(always)]
201 pub fn cmdcrcerren(&self) -> CMDCRCERREN_R {
202 CMDCRCERREN_R::new(((self.bits >> 17) & 1) != 0)
203 }
204 #[doc = "Bit 18 - Command End Bit Error Status Enable"]
205 #[inline(always)]
206 pub fn cmdendbiterren(&self) -> CMDENDBITERREN_R {
207 CMDENDBITERREN_R::new(((self.bits >> 18) & 1) != 0)
208 }
209 #[doc = "Bit 19 - Command Index Error Status Enable"]
210 #[inline(always)]
211 pub fn cmdindexerren(&self) -> CMDINDEXERREN_R {
212 CMDINDEXERREN_R::new(((self.bits >> 19) & 1) != 0)
213 }
214 #[doc = "Bit 20 - Data Timeout Error Status Enable"]
215 #[inline(always)]
216 pub fn dattouterren(&self) -> DATTOUTERREN_R {
217 DATTOUTERREN_R::new(((self.bits >> 20) & 1) != 0)
218 }
219 #[doc = "Bit 21 - Data CRC Error Status Enable"]
220 #[inline(always)]
221 pub fn datcrcerren(&self) -> DATCRCERREN_R {
222 DATCRCERREN_R::new(((self.bits >> 21) & 1) != 0)
223 }
224 #[doc = "Bit 22 - Data End Bit Error Status Enable"]
225 #[inline(always)]
226 pub fn datendbiterren(&self) -> DATENDBITERREN_R {
227 DATENDBITERREN_R::new(((self.bits >> 22) & 1) != 0)
228 }
229 #[doc = "Bit 23 - Current Limit Error Status Enable"]
230 #[inline(always)]
231 pub fn currentlimiterren(&self) -> CURRENTLIMITERREN_R {
232 CURRENTLIMITERREN_R::new(((self.bits >> 23) & 1) != 0)
233 }
234 #[doc = "Bit 24 - Auto CMD12 Error Status Enable"]
235 #[inline(always)]
236 pub fn autocmderren(&self) -> AUTOCMDERREN_R {
237 AUTOCMDERREN_R::new(((self.bits >> 24) & 1) != 0)
238 }
239 #[doc = "Bit 25 - ADMA Error Status Enable"]
240 #[inline(always)]
241 pub fn admaerren(&self) -> ADMAERREN_R {
242 ADMAERREN_R::new(((self.bits >> 25) & 1) != 0)
243 }
244 #[doc = "Bit 26 - Tuning Error Status Enable"]
245 #[inline(always)]
246 pub fn tuningerren(&self) -> TUNINGERREN_R {
247 TUNINGERREN_R::new(((self.bits >> 26) & 1) != 0)
248 }
249 #[doc = "Bit 28 - Target Response/Host Error Status Enable"]
250 #[inline(always)]
251 pub fn targetrespen(&self) -> TARGETRESPEN_R {
252 TARGETRESPEN_R::new(((self.bits >> 28) & 1) != 0)
253 }
254}
255impl W {
256 #[doc = "Bit 0 - Command Complete Signal Enable"]
257 #[inline(always)]
258 pub fn cmdcomen(&mut self) -> CMDCOMEN_W {
259 CMDCOMEN_W::new(self)
260 }
261 #[doc = "Bit 1 - Transfer Complete Signal Enable"]
262 #[inline(always)]
263 pub fn trancomen(&mut self) -> TRANCOMEN_W {
264 TRANCOMEN_W::new(self)
265 }
266 #[doc = "Bit 2 - Block Gap Event Signal Enable"]
267 #[inline(always)]
268 pub fn blkgapevten(&mut self) -> BLKGAPEVTEN_W {
269 BLKGAPEVTEN_W::new(self)
270 }
271 #[doc = "Bit 3 - DMA Interrupt Signal Enable"]
272 #[inline(always)]
273 pub fn dmainten(&mut self) -> DMAINTEN_W {
274 DMAINTEN_W::new(self)
275 }
276 #[doc = "Bit 4 - Buffer Write Ready Signal Enable"]
277 #[inline(always)]
278 pub fn bufwrrdyen(&mut self) -> BUFWRRDYEN_W {
279 BUFWRRDYEN_W::new(self)
280 }
281 #[doc = "Bit 5 - Buffer Read Ready Signal Enable"]
282 #[inline(always)]
283 pub fn bufrdrdyen(&mut self) -> BUFRDRDYEN_W {
284 BUFRDRDYEN_W::new(self)
285 }
286 #[doc = "Bit 6 - Card Insertion Signal Enable"]
287 #[inline(always)]
288 pub fn cardinsen(&mut self) -> CARDINSEN_W {
289 CARDINSEN_W::new(self)
290 }
291 #[doc = "Bit 7 - Card Removal Signal Enable"]
292 #[inline(always)]
293 pub fn cardrmen(&mut self) -> CARDRMEN_W {
294 CARDRMEN_W::new(self)
295 }
296 #[doc = "Bit 8 - Card Interrupt Signal Enable"]
297 #[inline(always)]
298 pub fn cardinten(&mut self) -> CARDINTEN_W {
299 CARDINTEN_W::new(self)
300 }
301 #[doc = "Bit 12 - Re-Tunning Event Signal Enable"]
302 #[inline(always)]
303 pub fn retuningevten(&mut self) -> RETUNINGEVTEN_W {
304 RETUNINGEVTEN_W::new(self)
305 }
306 #[doc = "Bit 13 - Boot Ack Received Signal Enable"]
307 #[inline(always)]
308 pub fn bootackrcven(&mut self) -> BOOTACKRCVEN_W {
309 BOOTACKRCVEN_W::new(self)
310 }
311 #[doc = "Bit 14 - Boot Terminate Interrupt Signal Enable"]
312 #[inline(always)]
313 pub fn bootterminateen(&mut self) -> BOOTTERMINATEEN_W {
314 BOOTTERMINATEEN_W::new(self)
315 }
316 #[doc = "Bit 16 - Command Time-out Error Status Enable"]
317 #[inline(always)]
318 pub fn cmdtouterren(&mut self) -> CMDTOUTERREN_W {
319 CMDTOUTERREN_W::new(self)
320 }
321 #[doc = "Bit 17 - Command CRC Error Status Enable"]
322 #[inline(always)]
323 pub fn cmdcrcerren(&mut self) -> CMDCRCERREN_W {
324 CMDCRCERREN_W::new(self)
325 }
326 #[doc = "Bit 18 - Command End Bit Error Status Enable"]
327 #[inline(always)]
328 pub fn cmdendbiterren(&mut self) -> CMDENDBITERREN_W {
329 CMDENDBITERREN_W::new(self)
330 }
331 #[doc = "Bit 19 - Command Index Error Status Enable"]
332 #[inline(always)]
333 pub fn cmdindexerren(&mut self) -> CMDINDEXERREN_W {
334 CMDINDEXERREN_W::new(self)
335 }
336 #[doc = "Bit 20 - Data Timeout Error Status Enable"]
337 #[inline(always)]
338 pub fn dattouterren(&mut self) -> DATTOUTERREN_W {
339 DATTOUTERREN_W::new(self)
340 }
341 #[doc = "Bit 21 - Data CRC Error Status Enable"]
342 #[inline(always)]
343 pub fn datcrcerren(&mut self) -> DATCRCERREN_W {
344 DATCRCERREN_W::new(self)
345 }
346 #[doc = "Bit 22 - Data End Bit Error Status Enable"]
347 #[inline(always)]
348 pub fn datendbiterren(&mut self) -> DATENDBITERREN_W {
349 DATENDBITERREN_W::new(self)
350 }
351 #[doc = "Bit 23 - Current Limit Error Status Enable"]
352 #[inline(always)]
353 pub fn currentlimiterren(&mut self) -> CURRENTLIMITERREN_W {
354 CURRENTLIMITERREN_W::new(self)
355 }
356 #[doc = "Bit 24 - Auto CMD12 Error Status Enable"]
357 #[inline(always)]
358 pub fn autocmderren(&mut self) -> AUTOCMDERREN_W {
359 AUTOCMDERREN_W::new(self)
360 }
361 #[doc = "Bit 25 - ADMA Error Status Enable"]
362 #[inline(always)]
363 pub fn admaerren(&mut self) -> ADMAERREN_W {
364 ADMAERREN_W::new(self)
365 }
366 #[doc = "Bit 26 - Tuning Error Status Enable"]
367 #[inline(always)]
368 pub fn tuningerren(&mut self) -> TUNINGERREN_W {
369 TUNINGERREN_W::new(self)
370 }
371 #[doc = "Bit 28 - Target Response/Host Error Status Enable"]
372 #[inline(always)]
373 pub fn targetrespen(&mut self) -> TARGETRESPEN_W {
374 TARGETRESPEN_W::new(self)
375 }
376 #[doc = "Writes raw bits to the register."]
377 #[inline(always)]
378 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
379 self.0.bits(bits);
380 self
381 }
382}
383#[doc = "Normal and Error Interrupt Status Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifenc](index.html) module"]
384pub struct IFENC_SPEC;
385impl crate::RegisterSpec for IFENC_SPEC {
386 type Ux = u32;
387}
388#[doc = "`read()` method returns [ifenc::R](R) reader structure"]
389impl crate::Readable for IFENC_SPEC {
390 type Reader = R;
391}
392#[doc = "`write(|w| ..)` method takes [ifenc::W](W) writer structure"]
393impl crate::Writable for IFENC_SPEC {
394 type Writer = W;
395}
396#[doc = "`reset()` method sets IFENC to value 0"]
397impl crate::Resettable for IFENC_SPEC {
398 #[inline(always)]
399 fn reset_value() -> Self::Ux {
400 0
401 }
402}