efm32gg12b410_pac/sdio/
clockctrl.rs

1#[doc = "Register `CLOCKCTRL` reader"]
2pub struct R(crate::R<CLOCKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLOCKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLOCKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLOCKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLOCKCTRL` writer"]
17pub struct W(crate::W<CLOCKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLOCKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLOCKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLOCKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `INTCLKEN` reader - Internal Clock Enable"]
38pub type INTCLKEN_R = crate::BitReader<bool>;
39#[doc = "Field `INTCLKEN` writer - Internal Clock Enable"]
40pub type INTCLKEN_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 0>;
41#[doc = "Field `INTCLKSTABLE` reader - Internal Clock Stable"]
42pub type INTCLKSTABLE_R = crate::BitReader<bool>;
43#[doc = "Field `SDCLKEN` reader - SDIO_CLK Pin Clock Enable"]
44pub type SDCLKEN_R = crate::BitReader<bool>;
45#[doc = "Field `SDCLKEN` writer - SDIO_CLK Pin Clock Enable"]
46pub type SDCLKEN_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 2>;
47#[doc = "Field `CLKGENSEL` reader - Clock Generator Select"]
48pub type CLKGENSEL_R = crate::BitReader<bool>;
49#[doc = "Field `CLKGENSEL` writer - Clock Generator Select"]
50pub type CLKGENSEL_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 5>;
51#[doc = "Field `UPPSDCLKFRE` reader - Upper Bits of SD_CLK Frequency Select"]
52pub type UPPSDCLKFRE_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `UPPSDCLKFRE` writer - Upper Bits of SD_CLK Frequency Select"]
54pub type UPPSDCLKFRE_W<'a> = crate::FieldWriter<'a, u32, CLOCKCTRL_SPEC, u8, u8, 2, 6>;
55#[doc = "SD_CLK Frequency Select\n\nValue on reset: 0"]
56#[derive(Clone, Copy, Debug, PartialEq)]
57#[repr(u8)]
58pub enum SDCLKFREQSEL_A {
59    #[doc = "0: `0`"]
60    NODIVISION = 0,
61}
62impl From<SDCLKFREQSEL_A> for u8 {
63    #[inline(always)]
64    fn from(variant: SDCLKFREQSEL_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `SDCLKFREQSEL` reader - SD_CLK Frequency Select"]
69pub type SDCLKFREQSEL_R = crate::FieldReader<u8, SDCLKFREQSEL_A>;
70impl SDCLKFREQSEL_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<SDCLKFREQSEL_A> {
74        match self.bits {
75            0 => Some(SDCLKFREQSEL_A::NODIVISION),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `NODIVISION`"]
80    #[inline(always)]
81    pub fn is_nodivision(&self) -> bool {
82        *self == SDCLKFREQSEL_A::NODIVISION
83    }
84}
85#[doc = "Field `SDCLKFREQSEL` writer - SD_CLK Frequency Select"]
86pub type SDCLKFREQSEL_W<'a> = crate::FieldWriter<'a, u32, CLOCKCTRL_SPEC, u8, SDCLKFREQSEL_A, 8, 8>;
87impl<'a> SDCLKFREQSEL_W<'a> {
88    #[doc = "`0`"]
89    #[inline(always)]
90    pub fn nodivision(self) -> &'a mut W {
91        self.variant(SDCLKFREQSEL_A::NODIVISION)
92    }
93}
94#[doc = "Field `DATTOUTCNTVAL` reader - Data Timeout Counter Value"]
95pub type DATTOUTCNTVAL_R = crate::FieldReader<u8, u8>;
96#[doc = "Field `DATTOUTCNTVAL` writer - Data Timeout Counter Value"]
97pub type DATTOUTCNTVAL_W<'a> = crate::FieldWriter<'a, u32, CLOCKCTRL_SPEC, u8, u8, 4, 16>;
98#[doc = "Field `SFTRSTA` reader - Software Reset for All"]
99pub type SFTRSTA_R = crate::BitReader<bool>;
100#[doc = "Field `SFTRSTA` writer - Software Reset for All"]
101pub type SFTRSTA_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 24>;
102#[doc = "Field `SFTRSTCMD` reader - Software Reset for CMD Line"]
103pub type SFTRSTCMD_R = crate::BitReader<bool>;
104#[doc = "Field `SFTRSTCMD` writer - Software Reset for CMD Line"]
105pub type SFTRSTCMD_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 25>;
106#[doc = "Field `SFTRSTDAT` reader - Software Reset for DAT Line"]
107pub type SFTRSTDAT_R = crate::BitReader<bool>;
108#[doc = "Field `SFTRSTDAT` writer - Software Reset for DAT Line"]
109pub type SFTRSTDAT_W<'a> = crate::BitWriter<'a, u32, CLOCKCTRL_SPEC, bool, 26>;
110impl R {
111    #[doc = "Bit 0 - Internal Clock Enable"]
112    #[inline(always)]
113    pub fn intclken(&self) -> INTCLKEN_R {
114        INTCLKEN_R::new((self.bits & 1) != 0)
115    }
116    #[doc = "Bit 1 - Internal Clock Stable"]
117    #[inline(always)]
118    pub fn intclkstable(&self) -> INTCLKSTABLE_R {
119        INTCLKSTABLE_R::new(((self.bits >> 1) & 1) != 0)
120    }
121    #[doc = "Bit 2 - SDIO_CLK Pin Clock Enable"]
122    #[inline(always)]
123    pub fn sdclken(&self) -> SDCLKEN_R {
124        SDCLKEN_R::new(((self.bits >> 2) & 1) != 0)
125    }
126    #[doc = "Bit 5 - Clock Generator Select"]
127    #[inline(always)]
128    pub fn clkgensel(&self) -> CLKGENSEL_R {
129        CLKGENSEL_R::new(((self.bits >> 5) & 1) != 0)
130    }
131    #[doc = "Bits 6:7 - Upper Bits of SD_CLK Frequency Select"]
132    #[inline(always)]
133    pub fn uppsdclkfre(&self) -> UPPSDCLKFRE_R {
134        UPPSDCLKFRE_R::new(((self.bits >> 6) & 3) as u8)
135    }
136    #[doc = "Bits 8:15 - SD_CLK Frequency Select"]
137    #[inline(always)]
138    pub fn sdclkfreqsel(&self) -> SDCLKFREQSEL_R {
139        SDCLKFREQSEL_R::new(((self.bits >> 8) & 0xff) as u8)
140    }
141    #[doc = "Bits 16:19 - Data Timeout Counter Value"]
142    #[inline(always)]
143    pub fn dattoutcntval(&self) -> DATTOUTCNTVAL_R {
144        DATTOUTCNTVAL_R::new(((self.bits >> 16) & 0x0f) as u8)
145    }
146    #[doc = "Bit 24 - Software Reset for All"]
147    #[inline(always)]
148    pub fn sftrsta(&self) -> SFTRSTA_R {
149        SFTRSTA_R::new(((self.bits >> 24) & 1) != 0)
150    }
151    #[doc = "Bit 25 - Software Reset for CMD Line"]
152    #[inline(always)]
153    pub fn sftrstcmd(&self) -> SFTRSTCMD_R {
154        SFTRSTCMD_R::new(((self.bits >> 25) & 1) != 0)
155    }
156    #[doc = "Bit 26 - Software Reset for DAT Line"]
157    #[inline(always)]
158    pub fn sftrstdat(&self) -> SFTRSTDAT_R {
159        SFTRSTDAT_R::new(((self.bits >> 26) & 1) != 0)
160    }
161}
162impl W {
163    #[doc = "Bit 0 - Internal Clock Enable"]
164    #[inline(always)]
165    pub fn intclken(&mut self) -> INTCLKEN_W {
166        INTCLKEN_W::new(self)
167    }
168    #[doc = "Bit 2 - SDIO_CLK Pin Clock Enable"]
169    #[inline(always)]
170    pub fn sdclken(&mut self) -> SDCLKEN_W {
171        SDCLKEN_W::new(self)
172    }
173    #[doc = "Bit 5 - Clock Generator Select"]
174    #[inline(always)]
175    pub fn clkgensel(&mut self) -> CLKGENSEL_W {
176        CLKGENSEL_W::new(self)
177    }
178    #[doc = "Bits 6:7 - Upper Bits of SD_CLK Frequency Select"]
179    #[inline(always)]
180    pub fn uppsdclkfre(&mut self) -> UPPSDCLKFRE_W {
181        UPPSDCLKFRE_W::new(self)
182    }
183    #[doc = "Bits 8:15 - SD_CLK Frequency Select"]
184    #[inline(always)]
185    pub fn sdclkfreqsel(&mut self) -> SDCLKFREQSEL_W {
186        SDCLKFREQSEL_W::new(self)
187    }
188    #[doc = "Bits 16:19 - Data Timeout Counter Value"]
189    #[inline(always)]
190    pub fn dattoutcntval(&mut self) -> DATTOUTCNTVAL_W {
191        DATTOUTCNTVAL_W::new(self)
192    }
193    #[doc = "Bit 24 - Software Reset for All"]
194    #[inline(always)]
195    pub fn sftrsta(&mut self) -> SFTRSTA_W {
196        SFTRSTA_W::new(self)
197    }
198    #[doc = "Bit 25 - Software Reset for CMD Line"]
199    #[inline(always)]
200    pub fn sftrstcmd(&mut self) -> SFTRSTCMD_W {
201        SFTRSTCMD_W::new(self)
202    }
203    #[doc = "Bit 26 - Software Reset for DAT Line"]
204    #[inline(always)]
205    pub fn sftrstdat(&mut self) -> SFTRSTDAT_W {
206        SFTRSTDAT_W::new(self)
207    }
208    #[doc = "Writes raw bits to the register."]
209    #[inline(always)]
210    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
211        self.0.bits(bits);
212        self
213    }
214}
215#[doc = "Clock Control, Timeout Control and Software Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clockctrl](index.html) module"]
216pub struct CLOCKCTRL_SPEC;
217impl crate::RegisterSpec for CLOCKCTRL_SPEC {
218    type Ux = u32;
219}
220#[doc = "`read()` method returns [clockctrl::R](R) reader structure"]
221impl crate::Readable for CLOCKCTRL_SPEC {
222    type Reader = R;
223}
224#[doc = "`write(|w| ..)` method takes [clockctrl::W](W) writer structure"]
225impl crate::Writable for CLOCKCTRL_SPEC {
226    type Writer = W;
227}
228#[doc = "`reset()` method sets CLOCKCTRL to value 0"]
229impl crate::Resettable for CLOCKCTRL_SPEC {
230    #[inline(always)]
231    fn reset_value() -> Self::Ux {
232        0
233    }
234}
efm32gg12b410_pac/sdio/clockctrl.rs

efm32gg12b410_pac/sdio/
clockctrl.rs
