efm32gg12b410_pac/qspi0/
devinstrrdconfig.rs

1#[doc = "Register `DEVINSTRRDCONFIG` reader"]
2pub struct R(crate::R<DEVINSTRRDCONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DEVINSTRRDCONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DEVINSTRRDCONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DEVINSTRRDCONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DEVINSTRRDCONFIG` writer"]
17pub struct W(crate::W<DEVINSTRRDCONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DEVINSTRRDCONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DEVINSTRRDCONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DEVINSTRRDCONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RDOPCODENONXIP` reader - Read Opcode in Non-XIP Mode"]
38pub type RDOPCODENONXIP_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `RDOPCODENONXIP` writer - Read Opcode in Non-XIP Mode"]
40pub type RDOPCODENONXIP_W<'a> = crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 8, 0>;
41#[doc = "Field `INSTRTYPE` reader - Instruction Type"]
42pub type INSTRTYPE_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `INSTRTYPE` writer - Instruction Type"]
44pub type INSTRTYPE_W<'a> = crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, 8>;
45#[doc = "Field `DDREN` reader - DDR Enable"]
46pub type DDREN_R = crate::BitReader<bool>;
47#[doc = "Field `DDREN` writer - DDR Enable"]
48pub type DDREN_W<'a> = crate::BitWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, bool, 10>;
49#[doc = "Field `ADDRXFERTYPESTDMODE` reader - Address Transfer Type for Standard SPI Modes"]
50pub type ADDRXFERTYPESTDMODE_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `ADDRXFERTYPESTDMODE` writer - Address Transfer Type for Standard SPI Modes"]
52pub type ADDRXFERTYPESTDMODE_W<'a> =
53    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, 12>;
54#[doc = "Field `DATAXFERTYPEEXTMODE` reader - Data Transfer Type for Standard SPI Modes"]
55pub type DATAXFERTYPEEXTMODE_R = crate::FieldReader<u8, u8>;
56#[doc = "Field `DATAXFERTYPEEXTMODE` writer - Data Transfer Type for Standard SPI Modes"]
57pub type DATAXFERTYPEEXTMODE_W<'a> =
58    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, 16>;
59#[doc = "Field `MODEBITENABLE` reader - Mode Bit Enable"]
60pub type MODEBITENABLE_R = crate::BitReader<bool>;
61#[doc = "Field `MODEBITENABLE` writer - Mode Bit Enable"]
62pub type MODEBITENABLE_W<'a> = crate::BitWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, bool, 20>;
63#[doc = "Field `DUMMYRDCLKCYCLES` reader - Dummy Read Clock Cycles"]
64pub type DUMMYRDCLKCYCLES_R = crate::FieldReader<u8, u8>;
65#[doc = "Field `DUMMYRDCLKCYCLES` writer - Dummy Read Clock Cycles"]
66pub type DUMMYRDCLKCYCLES_W<'a> = crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 5, 24>;
67impl R {
68    #[doc = "Bits 0:7 - Read Opcode in Non-XIP Mode"]
69    #[inline(always)]
70    pub fn rdopcodenonxip(&self) -> RDOPCODENONXIP_R {
71        RDOPCODENONXIP_R::new((self.bits & 0xff) as u8)
72    }
73    #[doc = "Bits 8:9 - Instruction Type"]
74    #[inline(always)]
75    pub fn instrtype(&self) -> INSTRTYPE_R {
76        INSTRTYPE_R::new(((self.bits >> 8) & 3) as u8)
77    }
78    #[doc = "Bit 10 - DDR Enable"]
79    #[inline(always)]
80    pub fn ddren(&self) -> DDREN_R {
81        DDREN_R::new(((self.bits >> 10) & 1) != 0)
82    }
83    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
84    #[inline(always)]
85    pub fn addrxfertypestdmode(&self) -> ADDRXFERTYPESTDMODE_R {
86        ADDRXFERTYPESTDMODE_R::new(((self.bits >> 12) & 3) as u8)
87    }
88    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
89    #[inline(always)]
90    pub fn dataxfertypeextmode(&self) -> DATAXFERTYPEEXTMODE_R {
91        DATAXFERTYPEEXTMODE_R::new(((self.bits >> 16) & 3) as u8)
92    }
93    #[doc = "Bit 20 - Mode Bit Enable"]
94    #[inline(always)]
95    pub fn modebitenable(&self) -> MODEBITENABLE_R {
96        MODEBITENABLE_R::new(((self.bits >> 20) & 1) != 0)
97    }
98    #[doc = "Bits 24:28 - Dummy Read Clock Cycles"]
99    #[inline(always)]
100    pub fn dummyrdclkcycles(&self) -> DUMMYRDCLKCYCLES_R {
101        DUMMYRDCLKCYCLES_R::new(((self.bits >> 24) & 0x1f) as u8)
102    }
103}
104impl W {
105    #[doc = "Bits 0:7 - Read Opcode in Non-XIP Mode"]
106    #[inline(always)]
107    pub fn rdopcodenonxip(&mut self) -> RDOPCODENONXIP_W {
108        RDOPCODENONXIP_W::new(self)
109    }
110    #[doc = "Bits 8:9 - Instruction Type"]
111    #[inline(always)]
112    pub fn instrtype(&mut self) -> INSTRTYPE_W {
113        INSTRTYPE_W::new(self)
114    }
115    #[doc = "Bit 10 - DDR Enable"]
116    #[inline(always)]
117    pub fn ddren(&mut self) -> DDREN_W {
118        DDREN_W::new(self)
119    }
120    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
121    #[inline(always)]
122    pub fn addrxfertypestdmode(&mut self) -> ADDRXFERTYPESTDMODE_W {
123        ADDRXFERTYPESTDMODE_W::new(self)
124    }
125    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
126    #[inline(always)]
127    pub fn dataxfertypeextmode(&mut self) -> DATAXFERTYPEEXTMODE_W {
128        DATAXFERTYPEEXTMODE_W::new(self)
129    }
130    #[doc = "Bit 20 - Mode Bit Enable"]
131    #[inline(always)]
132    pub fn modebitenable(&mut self) -> MODEBITENABLE_W {
133        MODEBITENABLE_W::new(self)
134    }
135    #[doc = "Bits 24:28 - Dummy Read Clock Cycles"]
136    #[inline(always)]
137    pub fn dummyrdclkcycles(&mut self) -> DUMMYRDCLKCYCLES_W {
138        DUMMYRDCLKCYCLES_W::new(self)
139    }
140    #[doc = "Writes raw bits to the register."]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.0.bits(bits);
144        self
145    }
146}
147#[doc = "Device Read Instruction Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devinstrrdconfig](index.html) module"]
148pub struct DEVINSTRRDCONFIG_SPEC;
149impl crate::RegisterSpec for DEVINSTRRDCONFIG_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [devinstrrdconfig::R](R) reader structure"]
153impl crate::Readable for DEVINSTRRDCONFIG_SPEC {
154    type Reader = R;
155}
156#[doc = "`write(|w| ..)` method takes [devinstrrdconfig::W](W) writer structure"]
157impl crate::Writable for DEVINSTRRDCONFIG_SPEC {
158    type Writer = W;
159}
160#[doc = "`reset()` method sets DEVINSTRRDCONFIG to value 0x03"]
161impl crate::Resettable for DEVINSTRRDCONFIG_SPEC {
162    #[inline(always)]
163    fn reset_value() -> Self::Ux {
164        0x03
165    }
166}
efm32gg12b410_pac/qspi0/devinstrrdconfig.rs

efm32gg12b410_pac/qspi0/
devinstrrdconfig.rs
