efm32gg12b410_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
38pub type IFCDIS_R = crate::BitReader<bool>;
39#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
40pub type IFCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 3>;
41#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
42pub type AIDIS_R = crate::BitReader<bool>;
43#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
44pub type AIDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 4>;
45#[doc = "Field `ICCDIS` reader - Interrupt Context Cache Disable"]
46pub type ICCDIS_R = crate::BitReader<bool>;
47#[doc = "Field `ICCDIS` writer - Interrupt Context Cache Disable"]
48pub type ICCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 5>;
49#[doc = "Field `EBICDIS` reader - External Bus Interface Cache Disable"]
50pub type EBICDIS_R = crate::BitReader<bool>;
51#[doc = "Field `EBICDIS` writer - External Bus Interface Cache Disable"]
52pub type EBICDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 6>;
53#[doc = "Field `PREFETCH` reader - Prefetch Mode"]
54pub type PREFETCH_R = crate::BitReader<bool>;
55#[doc = "Field `PREFETCH` writer - Prefetch Mode"]
56pub type PREFETCH_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 8>;
57#[doc = "Field `USEHPROT` reader - AHB_HPROT Mode"]
58pub type USEHPROT_R = crate::BitReader<bool>;
59#[doc = "Field `USEHPROT` writer - AHB_HPROT Mode"]
60pub type USEHPROT_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 9>;
61#[doc = "Field `QSPICDIS` reader - QSPI Cache Disable"]
62pub type QSPICDIS_R = crate::BitReader<bool>;
63#[doc = "Field `QSPICDIS` writer - QSPI Cache Disable"]
64pub type QSPICDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 10>;
65#[doc = "Read Mode\n\nValue on reset: 1"]
66#[derive(Clone, Copy, Debug, PartialEq)]
67#[repr(u8)]
68pub enum MODE_A {
69    #[doc = "0: Zero wait-states inserted in fetch or read transfers"]
70    WS0 = 0,
71    #[doc = "1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
72    WS1 = 1,
73    #[doc = "2: Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
74    WS2 = 2,
75    #[doc = "3: Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
76    WS3 = 3,
77}
78impl From<MODE_A> for u8 {
79    #[inline(always)]
80    fn from(variant: MODE_A) -> Self {
81        variant as _
82    }
83}
84#[doc = "Field `MODE` reader - Read Mode"]
85pub type MODE_R = crate::FieldReader<u8, MODE_A>;
86impl MODE_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> MODE_A {
90        match self.bits {
91            0 => MODE_A::WS0,
92            1 => MODE_A::WS1,
93            2 => MODE_A::WS2,
94            3 => MODE_A::WS3,
95            _ => unreachable!(),
96        }
97    }
98    #[doc = "Checks if the value of the field is `WS0`"]
99    #[inline(always)]
100    pub fn is_ws0(&self) -> bool {
101        *self == MODE_A::WS0
102    }
103    #[doc = "Checks if the value of the field is `WS1`"]
104    #[inline(always)]
105    pub fn is_ws1(&self) -> bool {
106        *self == MODE_A::WS1
107    }
108    #[doc = "Checks if the value of the field is `WS2`"]
109    #[inline(always)]
110    pub fn is_ws2(&self) -> bool {
111        *self == MODE_A::WS2
112    }
113    #[doc = "Checks if the value of the field is `WS3`"]
114    #[inline(always)]
115    pub fn is_ws3(&self) -> bool {
116        *self == MODE_A::WS3
117    }
118}
119#[doc = "Field `MODE` writer - Read Mode"]
120pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, READCTRL_SPEC, u8, MODE_A, 2, 24>;
121impl<'a> MODE_W<'a> {
122    #[doc = "Zero wait-states inserted in fetch or read transfers"]
123    #[inline(always)]
124    pub fn ws0(self) -> &'a mut W {
125        self.variant(MODE_A::WS0)
126    }
127    #[doc = "One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
128    #[inline(always)]
129    pub fn ws1(self) -> &'a mut W {
130        self.variant(MODE_A::WS1)
131    }
132    #[doc = "Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
133    #[inline(always)]
134    pub fn ws2(self) -> &'a mut W {
135        self.variant(MODE_A::WS2)
136    }
137    #[doc = "Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
138    #[inline(always)]
139    pub fn ws3(self) -> &'a mut W {
140        self.variant(MODE_A::WS3)
141    }
142}
143#[doc = "Field `SCBTP` reader - Suppress Conditional Branch Target Perfetch"]
144pub type SCBTP_R = crate::BitReader<bool>;
145#[doc = "Field `SCBTP` writer - Suppress Conditional Branch Target Perfetch"]
146pub type SCBTP_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 28>;
147impl R {
148    #[doc = "Bit 3 - Internal Flash Cache Disable"]
149    #[inline(always)]
150    pub fn ifcdis(&self) -> IFCDIS_R {
151        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
152    }
153    #[doc = "Bit 4 - Automatic Invalidate Disable"]
154    #[inline(always)]
155    pub fn aidis(&self) -> AIDIS_R {
156        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
157    }
158    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
159    #[inline(always)]
160    pub fn iccdis(&self) -> ICCDIS_R {
161        ICCDIS_R::new(((self.bits >> 5) & 1) != 0)
162    }
163    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
164    #[inline(always)]
165    pub fn ebicdis(&self) -> EBICDIS_R {
166        EBICDIS_R::new(((self.bits >> 6) & 1) != 0)
167    }
168    #[doc = "Bit 8 - Prefetch Mode"]
169    #[inline(always)]
170    pub fn prefetch(&self) -> PREFETCH_R {
171        PREFETCH_R::new(((self.bits >> 8) & 1) != 0)
172    }
173    #[doc = "Bit 9 - AHB_HPROT Mode"]
174    #[inline(always)]
175    pub fn usehprot(&self) -> USEHPROT_R {
176        USEHPROT_R::new(((self.bits >> 9) & 1) != 0)
177    }
178    #[doc = "Bit 10 - QSPI Cache Disable"]
179    #[inline(always)]
180    pub fn qspicdis(&self) -> QSPICDIS_R {
181        QSPICDIS_R::new(((self.bits >> 10) & 1) != 0)
182    }
183    #[doc = "Bits 24:25 - Read Mode"]
184    #[inline(always)]
185    pub fn mode(&self) -> MODE_R {
186        MODE_R::new(((self.bits >> 24) & 3) as u8)
187    }
188    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
189    #[inline(always)]
190    pub fn scbtp(&self) -> SCBTP_R {
191        SCBTP_R::new(((self.bits >> 28) & 1) != 0)
192    }
193}
194impl W {
195    #[doc = "Bit 3 - Internal Flash Cache Disable"]
196    #[inline(always)]
197    pub fn ifcdis(&mut self) -> IFCDIS_W {
198        IFCDIS_W::new(self)
199    }
200    #[doc = "Bit 4 - Automatic Invalidate Disable"]
201    #[inline(always)]
202    pub fn aidis(&mut self) -> AIDIS_W {
203        AIDIS_W::new(self)
204    }
205    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
206    #[inline(always)]
207    pub fn iccdis(&mut self) -> ICCDIS_W {
208        ICCDIS_W::new(self)
209    }
210    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
211    #[inline(always)]
212    pub fn ebicdis(&mut self) -> EBICDIS_W {
213        EBICDIS_W::new(self)
214    }
215    #[doc = "Bit 8 - Prefetch Mode"]
216    #[inline(always)]
217    pub fn prefetch(&mut self) -> PREFETCH_W {
218        PREFETCH_W::new(self)
219    }
220    #[doc = "Bit 9 - AHB_HPROT Mode"]
221    #[inline(always)]
222    pub fn usehprot(&mut self) -> USEHPROT_W {
223        USEHPROT_W::new(self)
224    }
225    #[doc = "Bit 10 - QSPI Cache Disable"]
226    #[inline(always)]
227    pub fn qspicdis(&mut self) -> QSPICDIS_W {
228        QSPICDIS_W::new(self)
229    }
230    #[doc = "Bits 24:25 - Read Mode"]
231    #[inline(always)]
232    pub fn mode(&mut self) -> MODE_W {
233        MODE_W::new(self)
234    }
235    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
236    #[inline(always)]
237    pub fn scbtp(&mut self) -> SCBTP_W {
238        SCBTP_W::new(self)
239    }
240    #[doc = "Writes raw bits to the register."]
241    #[inline(always)]
242    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
243        self.0.bits(bits);
244        self
245    }
246}
247#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
248pub struct READCTRL_SPEC;
249impl crate::RegisterSpec for READCTRL_SPEC {
250    type Ux = u32;
251}
252#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
253impl crate::Readable for READCTRL_SPEC {
254    type Reader = R;
255}
256#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
257impl crate::Writable for READCTRL_SPEC {
258    type Writer = W;
259}
260#[doc = "`reset()` method sets READCTRL to value 0x0100_0100"]
261impl crate::Resettable for READCTRL_SPEC {
262    #[inline(always)]
263    fn reset_value() -> Self::Ux {
264        0x0100_0100
265    }
266}
efm32gg12b410_pac/msc/readctrl.rs

efm32gg12b410_pac/msc/
readctrl.rs
