efm32gg12b410_pac/cmu/
qspictrl.rs

1#[doc = "Register `QSPICTRL` reader"]
2pub struct R(crate::R<QSPICTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<QSPICTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<QSPICTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<QSPICTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `QSPICTRL` writer"]
17pub struct W(crate::W<QSPICTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<QSPICTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<QSPICTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<QSPICTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "QSPI0 Reference Clock Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum QSPI0CLKSEL_A {
41    #[doc = "0: HFRCO clock is used to clock QSPI0"]
42    HFRCO = 0,
43    #[doc = "1: HFXO clock is used to clock QSPI0"]
44    HFXO = 1,
45    #[doc = "2: AUXHFRCO is used to clock QSPI0"]
46    AUXHFRCO = 2,
47    #[doc = "3: USHFRCO is used to clock QSPI0"]
48    USHFRCO = 3,
49}
50impl From<QSPI0CLKSEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: QSPI0CLKSEL_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `QSPI0CLKSEL` reader - QSPI0 Reference Clock Select"]
57pub type QSPI0CLKSEL_R = crate::FieldReader<u8, QSPI0CLKSEL_A>;
58impl QSPI0CLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> QSPI0CLKSEL_A {
62        match self.bits {
63            0 => QSPI0CLKSEL_A::HFRCO,
64            1 => QSPI0CLKSEL_A::HFXO,
65            2 => QSPI0CLKSEL_A::AUXHFRCO,
66            3 => QSPI0CLKSEL_A::USHFRCO,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `HFRCO`"]
71    #[inline(always)]
72    pub fn is_hfrco(&self) -> bool {
73        *self == QSPI0CLKSEL_A::HFRCO
74    }
75    #[doc = "Checks if the value of the field is `HFXO`"]
76    #[inline(always)]
77    pub fn is_hfxo(&self) -> bool {
78        *self == QSPI0CLKSEL_A::HFXO
79    }
80    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
81    #[inline(always)]
82    pub fn is_auxhfrco(&self) -> bool {
83        *self == QSPI0CLKSEL_A::AUXHFRCO
84    }
85    #[doc = "Checks if the value of the field is `USHFRCO`"]
86    #[inline(always)]
87    pub fn is_ushfrco(&self) -> bool {
88        *self == QSPI0CLKSEL_A::USHFRCO
89    }
90}
91#[doc = "Field `QSPI0CLKSEL` writer - QSPI0 Reference Clock Select"]
92pub type QSPI0CLKSEL_W<'a> =
93    crate::FieldWriterSafe<'a, u32, QSPICTRL_SPEC, u8, QSPI0CLKSEL_A, 2, 0>;
94impl<'a> QSPI0CLKSEL_W<'a> {
95    #[doc = "HFRCO clock is used to clock QSPI0"]
96    #[inline(always)]
97    pub fn hfrco(self) -> &'a mut W {
98        self.variant(QSPI0CLKSEL_A::HFRCO)
99    }
100    #[doc = "HFXO clock is used to clock QSPI0"]
101    #[inline(always)]
102    pub fn hfxo(self) -> &'a mut W {
103        self.variant(QSPI0CLKSEL_A::HFXO)
104    }
105    #[doc = "AUXHFRCO is used to clock QSPI0"]
106    #[inline(always)]
107    pub fn auxhfrco(self) -> &'a mut W {
108        self.variant(QSPI0CLKSEL_A::AUXHFRCO)
109    }
110    #[doc = "USHFRCO is used to clock QSPI0"]
111    #[inline(always)]
112    pub fn ushfrco(self) -> &'a mut W {
113        self.variant(QSPI0CLKSEL_A::USHFRCO)
114    }
115}
116#[doc = "Field `QSPI0CLKDIS` reader - QSPI0 Reference Clock Disable"]
117pub type QSPI0CLKDIS_R = crate::BitReader<bool>;
118#[doc = "Field `QSPI0CLKDIS` writer - QSPI0 Reference Clock Disable"]
119pub type QSPI0CLKDIS_W<'a> = crate::BitWriter<'a, u32, QSPICTRL_SPEC, bool, 7>;
120impl R {
121    #[doc = "Bits 0:1 - QSPI0 Reference Clock Select"]
122    #[inline(always)]
123    pub fn qspi0clksel(&self) -> QSPI0CLKSEL_R {
124        QSPI0CLKSEL_R::new((self.bits & 3) as u8)
125    }
126    #[doc = "Bit 7 - QSPI0 Reference Clock Disable"]
127    #[inline(always)]
128    pub fn qspi0clkdis(&self) -> QSPI0CLKDIS_R {
129        QSPI0CLKDIS_R::new(((self.bits >> 7) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 0:1 - QSPI0 Reference Clock Select"]
134    #[inline(always)]
135    pub fn qspi0clksel(&mut self) -> QSPI0CLKSEL_W {
136        QSPI0CLKSEL_W::new(self)
137    }
138    #[doc = "Bit 7 - QSPI0 Reference Clock Disable"]
139    #[inline(always)]
140    pub fn qspi0clkdis(&mut self) -> QSPI0CLKDIS_W {
141        QSPI0CLKDIS_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.0.bits(bits);
147        self
148    }
149}
150#[doc = "QSPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qspictrl](index.html) module"]
151pub struct QSPICTRL_SPEC;
152impl crate::RegisterSpec for QSPICTRL_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [qspictrl::R](R) reader structure"]
156impl crate::Readable for QSPICTRL_SPEC {
157    type Reader = R;
158}
159#[doc = "`write(|w| ..)` method takes [qspictrl::W](W) writer structure"]
160impl crate::Writable for QSPICTRL_SPEC {
161    type Writer = W;
162}
163#[doc = "`reset()` method sets QSPICTRL to value 0"]
164impl crate::Resettable for QSPICTRL_SPEC {
165    #[inline(always)]
166    fn reset_value() -> Self::Ux {
167        0
168    }
169}
efm32gg12b410_pac/cmu/qspictrl.rs

efm32gg12b410_pac/cmu/
qspictrl.rs
