efm32gg12b410_pac/qspi0/
devdelay.rs

1#[doc = "Register `DEVDELAY` reader"]
2pub struct R(crate::R<DEVDELAY_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DEVDELAY_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DEVDELAY_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DEVDELAY_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DEVDELAY` writer"]
17pub struct W(crate::W<DEVDELAY_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DEVDELAY_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DEVDELAY_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DEVDELAY_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DINIT` reader - Clock Delay for CS"]
38pub type DINIT_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DINIT` writer - Clock Delay for CS"]
40pub type DINIT_W<'a> = crate::FieldWriter<'a, u32, DEVDELAY_SPEC, u8, u8, 8, 0>;
41#[doc = "Field `DAFTER` reader - Clock Delay for Last Transaction Bit"]
42pub type DAFTER_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `DAFTER` writer - Clock Delay for Last Transaction Bit"]
44pub type DAFTER_W<'a> = crate::FieldWriter<'a, u32, DEVDELAY_SPEC, u8, u8, 8, 8>;
45#[doc = "Field `DBTWN` reader - Clock Delay Between Two Chip Selects"]
46pub type DBTWN_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `DBTWN` writer - Clock Delay Between Two Chip Selects"]
48pub type DBTWN_W<'a> = crate::FieldWriter<'a, u32, DEVDELAY_SPEC, u8, u8, 8, 16>;
49#[doc = "Field `DNSS` reader - Clock Delay for Chip Select Deassert"]
50pub type DNSS_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `DNSS` writer - Clock Delay for Chip Select Deassert"]
52pub type DNSS_W<'a> = crate::FieldWriter<'a, u32, DEVDELAY_SPEC, u8, u8, 8, 24>;
53impl R {
54    #[doc = "Bits 0:7 - Clock Delay for CS"]
55    #[inline(always)]
56    pub fn dinit(&self) -> DINIT_R {
57        DINIT_R::new((self.bits & 0xff) as u8)
58    }
59    #[doc = "Bits 8:15 - Clock Delay for Last Transaction Bit"]
60    #[inline(always)]
61    pub fn dafter(&self) -> DAFTER_R {
62        DAFTER_R::new(((self.bits >> 8) & 0xff) as u8)
63    }
64    #[doc = "Bits 16:23 - Clock Delay Between Two Chip Selects"]
65    #[inline(always)]
66    pub fn dbtwn(&self) -> DBTWN_R {
67        DBTWN_R::new(((self.bits >> 16) & 0xff) as u8)
68    }
69    #[doc = "Bits 24:31 - Clock Delay for Chip Select Deassert"]
70    #[inline(always)]
71    pub fn dnss(&self) -> DNSS_R {
72        DNSS_R::new(((self.bits >> 24) & 0xff) as u8)
73    }
74}
75impl W {
76    #[doc = "Bits 0:7 - Clock Delay for CS"]
77    #[inline(always)]
78    pub fn dinit(&mut self) -> DINIT_W {
79        DINIT_W::new(self)
80    }
81    #[doc = "Bits 8:15 - Clock Delay for Last Transaction Bit"]
82    #[inline(always)]
83    pub fn dafter(&mut self) -> DAFTER_W {
84        DAFTER_W::new(self)
85    }
86    #[doc = "Bits 16:23 - Clock Delay Between Two Chip Selects"]
87    #[inline(always)]
88    pub fn dbtwn(&mut self) -> DBTWN_W {
89        DBTWN_W::new(self)
90    }
91    #[doc = "Bits 24:31 - Clock Delay for Chip Select Deassert"]
92    #[inline(always)]
93    pub fn dnss(&mut self) -> DNSS_W {
94        DNSS_W::new(self)
95    }
96    #[doc = "Writes raw bits to the register."]
97    #[inline(always)]
98    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
99        self.0.bits(bits);
100        self
101    }
102}
103#[doc = "Device Delay Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devdelay](index.html) module"]
104pub struct DEVDELAY_SPEC;
105impl crate::RegisterSpec for DEVDELAY_SPEC {
106    type Ux = u32;
107}
108#[doc = "`read()` method returns [devdelay::R](R) reader structure"]
109impl crate::Readable for DEVDELAY_SPEC {
110    type Reader = R;
111}
112#[doc = "`write(|w| ..)` method takes [devdelay::W](W) writer structure"]
113impl crate::Writable for DEVDELAY_SPEC {
114    type Writer = W;
115}
116#[doc = "`reset()` method sets DEVDELAY to value 0"]
117impl crate::Resettable for DEVDELAY_SPEC {
118    #[inline(always)]
119    fn reset_value() -> Self::Ux {
120        0
121    }
122}
efm32gg12b410_pac/qspi0/devdelay.rs

efm32gg12b410_pac/qspi0/
devdelay.rs
