efm32gg12b410_pac/msc/
if_.rs

1#[doc = "Register `IF` reader"]
2pub struct R(crate::R<IF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `ERASE` reader - Erase Done Interrupt Read Flag"]
17pub type ERASE_R = crate::BitReader<bool>;
18#[doc = "Field `WRITE` reader - Write Done Interrupt Read Flag"]
19pub type WRITE_R = crate::BitReader<bool>;
20#[doc = "Field `CHOF` reader - Cache Hits Overflow Interrupt Flag"]
21pub type CHOF_R = crate::BitReader<bool>;
22#[doc = "Field `CMOF` reader - Cache Misses Overflow Interrupt Flag"]
23pub type CMOF_R = crate::BitReader<bool>;
24#[doc = "Field `PWRUPF` reader - Flash Power Up Sequence Complete Flag"]
25pub type PWRUPF_R = crate::BitReader<bool>;
26#[doc = "Field `ICACHERR` reader - ICache RAM Parity Error Flag"]
27pub type ICACHERR_R = crate::BitReader<bool>;
28#[doc = "Field `WDATAOV` reader - Flash Controller Write Buffer Overflow"]
29pub type WDATAOV_R = crate::BitReader<bool>;
30#[doc = "Field `LVEWRITE` reader - Flash LVE Write Error Flag"]
31pub type LVEWRITE_R = crate::BitReader<bool>;
32#[doc = "Field `RAMERR1B` reader - RAM 1-bit ECC Error Interrupt Flag"]
33pub type RAMERR1B_R = crate::BitReader<bool>;
34#[doc = "Field `RAMERR2B` reader - RAM 2-bit ECC Error Interrupt Flag"]
35pub type RAMERR2B_R = crate::BitReader<bool>;
36#[doc = "Field `RAM1ERR1B` reader - RAM1 1-bit ECC Error Interrupt Flag"]
37pub type RAM1ERR1B_R = crate::BitReader<bool>;
38#[doc = "Field `RAM1ERR2B` reader - RAM1 2-bit ECC Error Interrupt Flag"]
39pub type RAM1ERR2B_R = crate::BitReader<bool>;
40#[doc = "Field `RAM2ERR1B` reader - RAM2 1-bit ECC Error Interrupt Flag"]
41pub type RAM2ERR1B_R = crate::BitReader<bool>;
42#[doc = "Field `RAM2ERR2B` reader - RAM2 2-bit ECC Error Interrupt Flag"]
43pub type RAM2ERR2B_R = crate::BitReader<bool>;
44impl R {
45    #[doc = "Bit 0 - Erase Done Interrupt Read Flag"]
46    #[inline(always)]
47    pub fn erase(&self) -> ERASE_R {
48        ERASE_R::new((self.bits & 1) != 0)
49    }
50    #[doc = "Bit 1 - Write Done Interrupt Read Flag"]
51    #[inline(always)]
52    pub fn write(&self) -> WRITE_R {
53        WRITE_R::new(((self.bits >> 1) & 1) != 0)
54    }
55    #[doc = "Bit 2 - Cache Hits Overflow Interrupt Flag"]
56    #[inline(always)]
57    pub fn chof(&self) -> CHOF_R {
58        CHOF_R::new(((self.bits >> 2) & 1) != 0)
59    }
60    #[doc = "Bit 3 - Cache Misses Overflow Interrupt Flag"]
61    #[inline(always)]
62    pub fn cmof(&self) -> CMOF_R {
63        CMOF_R::new(((self.bits >> 3) & 1) != 0)
64    }
65    #[doc = "Bit 4 - Flash Power Up Sequence Complete Flag"]
66    #[inline(always)]
67    pub fn pwrupf(&self) -> PWRUPF_R {
68        PWRUPF_R::new(((self.bits >> 4) & 1) != 0)
69    }
70    #[doc = "Bit 5 - ICache RAM Parity Error Flag"]
71    #[inline(always)]
72    pub fn icacherr(&self) -> ICACHERR_R {
73        ICACHERR_R::new(((self.bits >> 5) & 1) != 0)
74    }
75    #[doc = "Bit 6 - Flash Controller Write Buffer Overflow"]
76    #[inline(always)]
77    pub fn wdataov(&self) -> WDATAOV_R {
78        WDATAOV_R::new(((self.bits >> 6) & 1) != 0)
79    }
80    #[doc = "Bit 8 - Flash LVE Write Error Flag"]
81    #[inline(always)]
82    pub fn lvewrite(&self) -> LVEWRITE_R {
83        LVEWRITE_R::new(((self.bits >> 8) & 1) != 0)
84    }
85    #[doc = "Bit 16 - RAM 1-bit ECC Error Interrupt Flag"]
86    #[inline(always)]
87    pub fn ramerr1b(&self) -> RAMERR1B_R {
88        RAMERR1B_R::new(((self.bits >> 16) & 1) != 0)
89    }
90    #[doc = "Bit 17 - RAM 2-bit ECC Error Interrupt Flag"]
91    #[inline(always)]
92    pub fn ramerr2b(&self) -> RAMERR2B_R {
93        RAMERR2B_R::new(((self.bits >> 17) & 1) != 0)
94    }
95    #[doc = "Bit 18 - RAM1 1-bit ECC Error Interrupt Flag"]
96    #[inline(always)]
97    pub fn ram1err1b(&self) -> RAM1ERR1B_R {
98        RAM1ERR1B_R::new(((self.bits >> 18) & 1) != 0)
99    }
100    #[doc = "Bit 19 - RAM1 2-bit ECC Error Interrupt Flag"]
101    #[inline(always)]
102    pub fn ram1err2b(&self) -> RAM1ERR2B_R {
103        RAM1ERR2B_R::new(((self.bits >> 19) & 1) != 0)
104    }
105    #[doc = "Bit 20 - RAM2 1-bit ECC Error Interrupt Flag"]
106    #[inline(always)]
107    pub fn ram2err1b(&self) -> RAM2ERR1B_R {
108        RAM2ERR1B_R::new(((self.bits >> 20) & 1) != 0)
109    }
110    #[doc = "Bit 21 - RAM2 2-bit ECC Error Interrupt Flag"]
111    #[inline(always)]
112    pub fn ram2err2b(&self) -> RAM2ERR2B_R {
113        RAM2ERR2B_R::new(((self.bits >> 21) & 1) != 0)
114    }
115}
116#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [if_](index.html) module"]
117pub struct IF_SPEC;
118impl crate::RegisterSpec for IF_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [if_::R](R) reader structure"]
122impl crate::Readable for IF_SPEC {
123    type Reader = R;
124}
125#[doc = "`reset()` method sets IF to value 0"]
126impl crate::Resettable for IF_SPEC {
127    #[inline(always)]
128    fn reset_value() -> Self::Ux {
129        0
130    }
131}
efm32gg12b410_pac/msc/if_.rs

efm32gg12b410_pac/msc/
if_.rs
