efm32gg12b410_pac/emu/
r5vadcctrl.rs

1#[doc = "Register `R5VADCCTRL` reader"]
2pub struct R(crate::R<R5VADCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<R5VADCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<R5VADCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<R5VADCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `R5VADCCTRL` writer"]
17pub struct W(crate::W<R5VADCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<R5VADCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<R5VADCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<R5VADCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENAMUX` reader - Enable the 5V Subsystem ADC MUX"]
38pub type ENAMUX_R = crate::BitReader<bool>;
39#[doc = "Field `ENAMUX` writer - Enable the 5V Subsystem ADC MUX"]
40pub type ENAMUX_W<'a> = crate::BitWriter<'a, u32, R5VADCCTRL_SPEC, bool, 0>;
41#[doc = "ADC Mux Selection\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum AMUXSEL_A {
45    #[doc = "0: VBUS divided by 10"]
46    VBUSDIV10 = 0,
47    #[doc = "1: VREGI divided by 10"]
48    VREGIDIV10 = 1,
49    #[doc = "2: VREGO divided by 6"]
50    VREGODIV6 = 2,
51    #[doc = "3: VREGI current monitor"]
52    VREGIIMON = 3,
53    #[doc = "4: VBUS current monitor"]
54    VBUSIMON = 4,
55}
56impl From<AMUXSEL_A> for u8 {
57    #[inline(always)]
58    fn from(variant: AMUXSEL_A) -> Self {
59        variant as _
60    }
61}
62#[doc = "Field `AMUXSEL` reader - ADC Mux Selection"]
63pub type AMUXSEL_R = crate::FieldReader<u8, AMUXSEL_A>;
64impl AMUXSEL_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<AMUXSEL_A> {
68        match self.bits {
69            0 => Some(AMUXSEL_A::VBUSDIV10),
70            1 => Some(AMUXSEL_A::VREGIDIV10),
71            2 => Some(AMUXSEL_A::VREGODIV6),
72            3 => Some(AMUXSEL_A::VREGIIMON),
73            4 => Some(AMUXSEL_A::VBUSIMON),
74            _ => None,
75        }
76    }
77    #[doc = "Checks if the value of the field is `VBUSDIV10`"]
78    #[inline(always)]
79    pub fn is_vbusdiv10(&self) -> bool {
80        *self == AMUXSEL_A::VBUSDIV10
81    }
82    #[doc = "Checks if the value of the field is `VREGIDIV10`"]
83    #[inline(always)]
84    pub fn is_vregidiv10(&self) -> bool {
85        *self == AMUXSEL_A::VREGIDIV10
86    }
87    #[doc = "Checks if the value of the field is `VREGODIV6`"]
88    #[inline(always)]
89    pub fn is_vregodiv6(&self) -> bool {
90        *self == AMUXSEL_A::VREGODIV6
91    }
92    #[doc = "Checks if the value of the field is `VREGIIMON`"]
93    #[inline(always)]
94    pub fn is_vregiimon(&self) -> bool {
95        *self == AMUXSEL_A::VREGIIMON
96    }
97    #[doc = "Checks if the value of the field is `VBUSIMON`"]
98    #[inline(always)]
99    pub fn is_vbusimon(&self) -> bool {
100        *self == AMUXSEL_A::VBUSIMON
101    }
102}
103#[doc = "Field `AMUXSEL` writer - ADC Mux Selection"]
104pub type AMUXSEL_W<'a> = crate::FieldWriter<'a, u32, R5VADCCTRL_SPEC, u8, AMUXSEL_A, 4, 12>;
105impl<'a> AMUXSEL_W<'a> {
106    #[doc = "VBUS divided by 10"]
107    #[inline(always)]
108    pub fn vbusdiv10(self) -> &'a mut W {
109        self.variant(AMUXSEL_A::VBUSDIV10)
110    }
111    #[doc = "VREGI divided by 10"]
112    #[inline(always)]
113    pub fn vregidiv10(self) -> &'a mut W {
114        self.variant(AMUXSEL_A::VREGIDIV10)
115    }
116    #[doc = "VREGO divided by 6"]
117    #[inline(always)]
118    pub fn vregodiv6(self) -> &'a mut W {
119        self.variant(AMUXSEL_A::VREGODIV6)
120    }
121    #[doc = "VREGI current monitor"]
122    #[inline(always)]
123    pub fn vregiimon(self) -> &'a mut W {
124        self.variant(AMUXSEL_A::VREGIIMON)
125    }
126    #[doc = "VBUS current monitor"]
127    #[inline(always)]
128    pub fn vbusimon(self) -> &'a mut W {
129        self.variant(AMUXSEL_A::VBUSIMON)
130    }
131}
132impl R {
133    #[doc = "Bit 0 - Enable the 5V Subsystem ADC MUX"]
134    #[inline(always)]
135    pub fn enamux(&self) -> ENAMUX_R {
136        ENAMUX_R::new((self.bits & 1) != 0)
137    }
138    #[doc = "Bits 12:15 - ADC Mux Selection"]
139    #[inline(always)]
140    pub fn amuxsel(&self) -> AMUXSEL_R {
141        AMUXSEL_R::new(((self.bits >> 12) & 0x0f) as u8)
142    }
143}
144impl W {
145    #[doc = "Bit 0 - Enable the 5V Subsystem ADC MUX"]
146    #[inline(always)]
147    pub fn enamux(&mut self) -> ENAMUX_W {
148        ENAMUX_W::new(self)
149    }
150    #[doc = "Bits 12:15 - ADC Mux Selection"]
151    #[inline(always)]
152    pub fn amuxsel(&mut self) -> AMUXSEL_W {
153        AMUXSEL_W::new(self)
154    }
155    #[doc = "Writes raw bits to the register."]
156    #[inline(always)]
157    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
158        self.0.bits(bits);
159        self
160    }
161}
162#[doc = "5V Regulator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r5vadcctrl](index.html) module"]
163pub struct R5VADCCTRL_SPEC;
164impl crate::RegisterSpec for R5VADCCTRL_SPEC {
165    type Ux = u32;
166}
167#[doc = "`read()` method returns [r5vadcctrl::R](R) reader structure"]
168impl crate::Readable for R5VADCCTRL_SPEC {
169    type Reader = R;
170}
171#[doc = "`write(|w| ..)` method takes [r5vadcctrl::W](W) writer structure"]
172impl crate::Writable for R5VADCCTRL_SPEC {
173    type Writer = W;
174}
175#[doc = "`reset()` method sets R5VADCCTRL to value 0"]
176impl crate::Resettable for R5VADCCTRL_SPEC {
177    #[inline(always)]
178    fn reset_value() -> Self::Ux {
179        0
180    }
181}
efm32gg12b410_pac/emu/r5vadcctrl.rs

efm32gg12b410_pac/emu/
r5vadcctrl.rs
