efm32gg12b390_pac/qspi0/
indirectreadxferctrl.rs

1#[doc = "Register `INDIRECTREADXFERCTRL` reader"]
2pub struct R(crate::R<INDIRECTREADXFERCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INDIRECTREADXFERCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INDIRECTREADXFERCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INDIRECTREADXFERCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INDIRECTREADXFERCTRL` writer"]
17pub struct W(crate::W<INDIRECTREADXFERCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INDIRECTREADXFERCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INDIRECTREADXFERCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INDIRECTREADXFERCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `START` writer - Start Indirect Read"]
38pub type START_W<'a> = crate::BitWriter<'a, u32, INDIRECTREADXFERCTRL_SPEC, bool, 0>;
39#[doc = "Field `CANCEL` writer - Cancel Indirect Read"]
40pub type CANCEL_W<'a> = crate::BitWriter<'a, u32, INDIRECTREADXFERCTRL_SPEC, bool, 1>;
41#[doc = "Field `RDSTATUS` reader - Indirect Read Status"]
42pub type RDSTATUS_R = crate::BitReader<bool>;
43#[doc = "Field `SRAMFULL` reader - SRAM Full"]
44pub type SRAMFULL_R = crate::BitReader<bool>;
45#[doc = "Field `SRAMFULL` writer - SRAM Full"]
46pub type SRAMFULL_W<'a> = crate::BitWriter<'a, u32, INDIRECTREADXFERCTRL_SPEC, bool, 3>;
47#[doc = "Field `RDQUEUED` reader - Two Indirect Read Operations Have Been Queued"]
48pub type RDQUEUED_R = crate::BitReader<bool>;
49#[doc = "Field `INDOPSDONESTATUS` reader - Indirect Completion Status"]
50pub type INDOPSDONESTATUS_R = crate::BitReader<bool>;
51#[doc = "Field `INDOPSDONESTATUS` writer - Indirect Completion Status"]
52pub type INDOPSDONESTATUS_W<'a> = crate::BitWriter<'a, u32, INDIRECTREADXFERCTRL_SPEC, bool, 5>;
53#[doc = "Field `NUMINDOPSDONE` reader - Number Indirect Operations Done"]
54pub type NUMINDOPSDONE_R = crate::FieldReader<u8, u8>;
55impl R {
56    #[doc = "Bit 2 - Indirect Read Status"]
57    #[inline(always)]
58    pub fn rdstatus(&self) -> RDSTATUS_R {
59        RDSTATUS_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3 - SRAM Full"]
62    #[inline(always)]
63    pub fn sramfull(&self) -> SRAMFULL_R {
64        SRAMFULL_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4 - Two Indirect Read Operations Have Been Queued"]
67    #[inline(always)]
68    pub fn rdqueued(&self) -> RDQUEUED_R {
69        RDQUEUED_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 5 - Indirect Completion Status"]
72    #[inline(always)]
73    pub fn indopsdonestatus(&self) -> INDOPSDONESTATUS_R {
74        INDOPSDONESTATUS_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    #[doc = "Bits 6:7 - Number Indirect Operations Done"]
77    #[inline(always)]
78    pub fn numindopsdone(&self) -> NUMINDOPSDONE_R {
79        NUMINDOPSDONE_R::new(((self.bits >> 6) & 3) as u8)
80    }
81}
82impl W {
83    #[doc = "Bit 0 - Start Indirect Read"]
84    #[inline(always)]
85    pub fn start(&mut self) -> START_W {
86        START_W::new(self)
87    }
88    #[doc = "Bit 1 - Cancel Indirect Read"]
89    #[inline(always)]
90    pub fn cancel(&mut self) -> CANCEL_W {
91        CANCEL_W::new(self)
92    }
93    #[doc = "Bit 3 - SRAM Full"]
94    #[inline(always)]
95    pub fn sramfull(&mut self) -> SRAMFULL_W {
96        SRAMFULL_W::new(self)
97    }
98    #[doc = "Bit 5 - Indirect Completion Status"]
99    #[inline(always)]
100    pub fn indopsdonestatus(&mut self) -> INDOPSDONESTATUS_W {
101        INDOPSDONESTATUS_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Indirect Read Transfer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [indirectreadxferctrl](index.html) module"]
111pub struct INDIRECTREADXFERCTRL_SPEC;
112impl crate::RegisterSpec for INDIRECTREADXFERCTRL_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [indirectreadxferctrl::R](R) reader structure"]
116impl crate::Readable for INDIRECTREADXFERCTRL_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [indirectreadxferctrl::W](W) writer structure"]
120impl crate::Writable for INDIRECTREADXFERCTRL_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets INDIRECTREADXFERCTRL to value 0"]
124impl crate::Resettable for INDIRECTREADXFERCTRL_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
efm32gg12b390_pac/qspi0/indirectreadxferctrl.rs

efm32gg12b390_pac/qspi0/
indirectreadxferctrl.rs
