efm32gg12b330_pac/cmu/
auxhfrcoctrl.rs

1#[doc = "Register `AUXHFRCOCTRL` reader"]
2pub struct R(crate::R<AUXHFRCOCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<AUXHFRCOCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<AUXHFRCOCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<AUXHFRCOCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `AUXHFRCOCTRL` writer"]
17pub struct W(crate::W<AUXHFRCOCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<AUXHFRCOCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<AUXHFRCOCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<AUXHFRCOCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TUNING` reader - AUXHFRCO Tuning Value"]
38pub type TUNING_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `TUNING` writer - AUXHFRCO Tuning Value"]
40pub type TUNING_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, u8, 7, 0>;
41#[doc = "Field `FINETUNING` reader - AUXHFRCO Fine Tuning Value"]
42pub type FINETUNING_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `FINETUNING` writer - AUXHFRCO Fine Tuning Value"]
44pub type FINETUNING_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, u8, 6, 8>;
45#[doc = "Field `FREQRANGE` reader - AUXHFRCO Frequency Range"]
46pub type FREQRANGE_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `FREQRANGE` writer - AUXHFRCO Frequency Range"]
48pub type FREQRANGE_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, u8, 5, 16>;
49#[doc = "Field `CMPBIAS` reader - AUXHFRCO Comparator Bias Current"]
50pub type CMPBIAS_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `CMPBIAS` writer - AUXHFRCO Comparator Bias Current"]
52pub type CMPBIAS_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, u8, 3, 21>;
53#[doc = "Field `LDOHP` reader - AUXHFRCO LDO High Power Mode"]
54pub type LDOHP_R = crate::BitReader<bool>;
55#[doc = "Field `LDOHP` writer - AUXHFRCO LDO High Power Mode"]
56pub type LDOHP_W<'a> = crate::BitWriter<'a, u32, AUXHFRCOCTRL_SPEC, bool, 24>;
57#[doc = "Locally Divide AUXHFRCO Clock Output\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum CLKDIV_A {
61    #[doc = "0: Divide by 1."]
62    DIV1 = 0,
63    #[doc = "1: Divide by 2."]
64    DIV2 = 1,
65    #[doc = "2: Divide by 4."]
66    DIV4 = 2,
67}
68impl From<CLKDIV_A> for u8 {
69    #[inline(always)]
70    fn from(variant: CLKDIV_A) -> Self {
71        variant as _
72    }
73}
74#[doc = "Field `CLKDIV` reader - Locally Divide AUXHFRCO Clock Output"]
75pub type CLKDIV_R = crate::FieldReader<u8, CLKDIV_A>;
76impl CLKDIV_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> Option<CLKDIV_A> {
80        match self.bits {
81            0 => Some(CLKDIV_A::DIV1),
82            1 => Some(CLKDIV_A::DIV2),
83            2 => Some(CLKDIV_A::DIV4),
84            _ => None,
85        }
86    }
87    #[doc = "Checks if the value of the field is `DIV1`"]
88    #[inline(always)]
89    pub fn is_div1(&self) -> bool {
90        *self == CLKDIV_A::DIV1
91    }
92    #[doc = "Checks if the value of the field is `DIV2`"]
93    #[inline(always)]
94    pub fn is_div2(&self) -> bool {
95        *self == CLKDIV_A::DIV2
96    }
97    #[doc = "Checks if the value of the field is `DIV4`"]
98    #[inline(always)]
99    pub fn is_div4(&self) -> bool {
100        *self == CLKDIV_A::DIV4
101    }
102}
103#[doc = "Field `CLKDIV` writer - Locally Divide AUXHFRCO Clock Output"]
104pub type CLKDIV_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, CLKDIV_A, 2, 25>;
105impl<'a> CLKDIV_W<'a> {
106    #[doc = "Divide by 1."]
107    #[inline(always)]
108    pub fn div1(self) -> &'a mut W {
109        self.variant(CLKDIV_A::DIV1)
110    }
111    #[doc = "Divide by 2."]
112    #[inline(always)]
113    pub fn div2(self) -> &'a mut W {
114        self.variant(CLKDIV_A::DIV2)
115    }
116    #[doc = "Divide by 4."]
117    #[inline(always)]
118    pub fn div4(self) -> &'a mut W {
119        self.variant(CLKDIV_A::DIV4)
120    }
121}
122#[doc = "Field `FINETUNINGEN` reader - Enable Reference for Fine Tuning"]
123pub type FINETUNINGEN_R = crate::BitReader<bool>;
124#[doc = "Field `FINETUNINGEN` writer - Enable Reference for Fine Tuning"]
125pub type FINETUNINGEN_W<'a> = crate::BitWriter<'a, u32, AUXHFRCOCTRL_SPEC, bool, 27>;
126#[doc = "Field `VREFTC` reader - AUXHFRCO Temperature Coefficient Trim on Comparator Reference"]
127pub type VREFTC_R = crate::FieldReader<u8, u8>;
128#[doc = "Field `VREFTC` writer - AUXHFRCO Temperature Coefficient Trim on Comparator Reference"]
129pub type VREFTC_W<'a> = crate::FieldWriter<'a, u32, AUXHFRCOCTRL_SPEC, u8, u8, 4, 28>;
130impl R {
131    #[doc = "Bits 0:6 - AUXHFRCO Tuning Value"]
132    #[inline(always)]
133    pub fn tuning(&self) -> TUNING_R {
134        TUNING_R::new((self.bits & 0x7f) as u8)
135    }
136    #[doc = "Bits 8:13 - AUXHFRCO Fine Tuning Value"]
137    #[inline(always)]
138    pub fn finetuning(&self) -> FINETUNING_R {
139        FINETUNING_R::new(((self.bits >> 8) & 0x3f) as u8)
140    }
141    #[doc = "Bits 16:20 - AUXHFRCO Frequency Range"]
142    #[inline(always)]
143    pub fn freqrange(&self) -> FREQRANGE_R {
144        FREQRANGE_R::new(((self.bits >> 16) & 0x1f) as u8)
145    }
146    #[doc = "Bits 21:23 - AUXHFRCO Comparator Bias Current"]
147    #[inline(always)]
148    pub fn cmpbias(&self) -> CMPBIAS_R {
149        CMPBIAS_R::new(((self.bits >> 21) & 7) as u8)
150    }
151    #[doc = "Bit 24 - AUXHFRCO LDO High Power Mode"]
152    #[inline(always)]
153    pub fn ldohp(&self) -> LDOHP_R {
154        LDOHP_R::new(((self.bits >> 24) & 1) != 0)
155    }
156    #[doc = "Bits 25:26 - Locally Divide AUXHFRCO Clock Output"]
157    #[inline(always)]
158    pub fn clkdiv(&self) -> CLKDIV_R {
159        CLKDIV_R::new(((self.bits >> 25) & 3) as u8)
160    }
161    #[doc = "Bit 27 - Enable Reference for Fine Tuning"]
162    #[inline(always)]
163    pub fn finetuningen(&self) -> FINETUNINGEN_R {
164        FINETUNINGEN_R::new(((self.bits >> 27) & 1) != 0)
165    }
166    #[doc = "Bits 28:31 - AUXHFRCO Temperature Coefficient Trim on Comparator Reference"]
167    #[inline(always)]
168    pub fn vreftc(&self) -> VREFTC_R {
169        VREFTC_R::new(((self.bits >> 28) & 0x0f) as u8)
170    }
171}
172impl W {
173    #[doc = "Bits 0:6 - AUXHFRCO Tuning Value"]
174    #[inline(always)]
175    pub fn tuning(&mut self) -> TUNING_W {
176        TUNING_W::new(self)
177    }
178    #[doc = "Bits 8:13 - AUXHFRCO Fine Tuning Value"]
179    #[inline(always)]
180    pub fn finetuning(&mut self) -> FINETUNING_W {
181        FINETUNING_W::new(self)
182    }
183    #[doc = "Bits 16:20 - AUXHFRCO Frequency Range"]
184    #[inline(always)]
185    pub fn freqrange(&mut self) -> FREQRANGE_W {
186        FREQRANGE_W::new(self)
187    }
188    #[doc = "Bits 21:23 - AUXHFRCO Comparator Bias Current"]
189    #[inline(always)]
190    pub fn cmpbias(&mut self) -> CMPBIAS_W {
191        CMPBIAS_W::new(self)
192    }
193    #[doc = "Bit 24 - AUXHFRCO LDO High Power Mode"]
194    #[inline(always)]
195    pub fn ldohp(&mut self) -> LDOHP_W {
196        LDOHP_W::new(self)
197    }
198    #[doc = "Bits 25:26 - Locally Divide AUXHFRCO Clock Output"]
199    #[inline(always)]
200    pub fn clkdiv(&mut self) -> CLKDIV_W {
201        CLKDIV_W::new(self)
202    }
203    #[doc = "Bit 27 - Enable Reference for Fine Tuning"]
204    #[inline(always)]
205    pub fn finetuningen(&mut self) -> FINETUNINGEN_W {
206        FINETUNINGEN_W::new(self)
207    }
208    #[doc = "Bits 28:31 - AUXHFRCO Temperature Coefficient Trim on Comparator Reference"]
209    #[inline(always)]
210    pub fn vreftc(&mut self) -> VREFTC_W {
211        VREFTC_W::new(self)
212    }
213    #[doc = "Writes raw bits to the register."]
214    #[inline(always)]
215    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
216        self.0.bits(bits);
217        self
218    }
219}
220#[doc = "AUXHFRCO Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [auxhfrcoctrl](index.html) module"]
221pub struct AUXHFRCOCTRL_SPEC;
222impl crate::RegisterSpec for AUXHFRCOCTRL_SPEC {
223    type Ux = u32;
224}
225#[doc = "`read()` method returns [auxhfrcoctrl::R](R) reader structure"]
226impl crate::Readable for AUXHFRCOCTRL_SPEC {
227    type Reader = R;
228}
229#[doc = "`write(|w| ..)` method takes [auxhfrcoctrl::W](W) writer structure"]
230impl crate::Writable for AUXHFRCOCTRL_SPEC {
231    type Writer = W;
232}
233#[doc = "`reset()` method sets AUXHFRCOCTRL to value 0xb148_1f7f"]
234impl crate::Resettable for AUXHFRCOCTRL_SPEC {
235    #[inline(always)]
236    fn reset_value() -> Self::Ux {
237        0xb148_1f7f
238    }
239}
efm32gg12b330_pac/cmu/auxhfrcoctrl.rs

efm32gg12b330_pac/cmu/
auxhfrcoctrl.rs
