efm32gg12b130_pac/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
38pub type IFCDIS_R = crate::BitReader<bool>;
39#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
40pub type IFCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 3>;
41#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
42pub type AIDIS_R = crate::BitReader<bool>;
43#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
44pub type AIDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 4>;
45#[doc = "Field `ICCDIS` reader - Interrupt Context Cache Disable"]
46pub type ICCDIS_R = crate::BitReader<bool>;
47#[doc = "Field `ICCDIS` writer - Interrupt Context Cache Disable"]
48pub type ICCDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 5>;
49#[doc = "Field `EBICDIS` reader - External Bus Interface Cache Disable"]
50pub type EBICDIS_R = crate::BitReader<bool>;
51#[doc = "Field `EBICDIS` writer - External Bus Interface Cache Disable"]
52pub type EBICDIS_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 6>;
53#[doc = "Field `PREFETCH` reader - Prefetch Mode"]
54pub type PREFETCH_R = crate::BitReader<bool>;
55#[doc = "Field `PREFETCH` writer - Prefetch Mode"]
56pub type PREFETCH_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 8>;
57#[doc = "Field `USEHPROT` reader - AHB_HPROT Mode"]
58pub type USEHPROT_R = crate::BitReader<bool>;
59#[doc = "Field `USEHPROT` writer - AHB_HPROT Mode"]
60pub type USEHPROT_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 9>;
61#[doc = "Read Mode\n\nValue on reset: 1"]
62#[derive(Clone, Copy, Debug, PartialEq)]
63#[repr(u8)]
64pub enum MODE_A {
65    #[doc = "0: Zero wait-states inserted in fetch or read transfers"]
66    WS0 = 0,
67    #[doc = "1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
68    WS1 = 1,
69    #[doc = "2: Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
70    WS2 = 2,
71    #[doc = "3: Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
72    WS3 = 3,
73}
74impl From<MODE_A> for u8 {
75    #[inline(always)]
76    fn from(variant: MODE_A) -> Self {
77        variant as _
78    }
79}
80#[doc = "Field `MODE` reader - Read Mode"]
81pub type MODE_R = crate::FieldReader<u8, MODE_A>;
82impl MODE_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub fn variant(&self) -> MODE_A {
86        match self.bits {
87            0 => MODE_A::WS0,
88            1 => MODE_A::WS1,
89            2 => MODE_A::WS2,
90            3 => MODE_A::WS3,
91            _ => unreachable!(),
92        }
93    }
94    #[doc = "Checks if the value of the field is `WS0`"]
95    #[inline(always)]
96    pub fn is_ws0(&self) -> bool {
97        *self == MODE_A::WS0
98    }
99    #[doc = "Checks if the value of the field is `WS1`"]
100    #[inline(always)]
101    pub fn is_ws1(&self) -> bool {
102        *self == MODE_A::WS1
103    }
104    #[doc = "Checks if the value of the field is `WS2`"]
105    #[inline(always)]
106    pub fn is_ws2(&self) -> bool {
107        *self == MODE_A::WS2
108    }
109    #[doc = "Checks if the value of the field is `WS3`"]
110    #[inline(always)]
111    pub fn is_ws3(&self) -> bool {
112        *self == MODE_A::WS3
113    }
114}
115#[doc = "Field `MODE` writer - Read Mode"]
116pub type MODE_W<'a> = crate::FieldWriterSafe<'a, u32, READCTRL_SPEC, u8, MODE_A, 2, 24>;
117impl<'a> MODE_W<'a> {
118    #[doc = "Zero wait-states inserted in fetch or read transfers"]
119    #[inline(always)]
120    pub fn ws0(self) -> &'a mut W {
121        self.variant(MODE_A::WS0)
122    }
123    #[doc = "One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details"]
124    #[inline(always)]
125    pub fn ws1(self) -> &'a mut W {
126        self.variant(MODE_A::WS1)
127    }
128    #[doc = "Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
129    #[inline(always)]
130    pub fn ws2(self) -> &'a mut W {
131        self.variant(MODE_A::WS2)
132    }
133    #[doc = "Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details"]
134    #[inline(always)]
135    pub fn ws3(self) -> &'a mut W {
136        self.variant(MODE_A::WS3)
137    }
138}
139#[doc = "Field `SCBTP` reader - Suppress Conditional Branch Target Perfetch"]
140pub type SCBTP_R = crate::BitReader<bool>;
141#[doc = "Field `SCBTP` writer - Suppress Conditional Branch Target Perfetch"]
142pub type SCBTP_W<'a> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, 28>;
143impl R {
144    #[doc = "Bit 3 - Internal Flash Cache Disable"]
145    #[inline(always)]
146    pub fn ifcdis(&self) -> IFCDIS_R {
147        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
148    }
149    #[doc = "Bit 4 - Automatic Invalidate Disable"]
150    #[inline(always)]
151    pub fn aidis(&self) -> AIDIS_R {
152        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
153    }
154    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
155    #[inline(always)]
156    pub fn iccdis(&self) -> ICCDIS_R {
157        ICCDIS_R::new(((self.bits >> 5) & 1) != 0)
158    }
159    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
160    #[inline(always)]
161    pub fn ebicdis(&self) -> EBICDIS_R {
162        EBICDIS_R::new(((self.bits >> 6) & 1) != 0)
163    }
164    #[doc = "Bit 8 - Prefetch Mode"]
165    #[inline(always)]
166    pub fn prefetch(&self) -> PREFETCH_R {
167        PREFETCH_R::new(((self.bits >> 8) & 1) != 0)
168    }
169    #[doc = "Bit 9 - AHB_HPROT Mode"]
170    #[inline(always)]
171    pub fn usehprot(&self) -> USEHPROT_R {
172        USEHPROT_R::new(((self.bits >> 9) & 1) != 0)
173    }
174    #[doc = "Bits 24:25 - Read Mode"]
175    #[inline(always)]
176    pub fn mode(&self) -> MODE_R {
177        MODE_R::new(((self.bits >> 24) & 3) as u8)
178    }
179    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
180    #[inline(always)]
181    pub fn scbtp(&self) -> SCBTP_R {
182        SCBTP_R::new(((self.bits >> 28) & 1) != 0)
183    }
184}
185impl W {
186    #[doc = "Bit 3 - Internal Flash Cache Disable"]
187    #[inline(always)]
188    pub fn ifcdis(&mut self) -> IFCDIS_W {
189        IFCDIS_W::new(self)
190    }
191    #[doc = "Bit 4 - Automatic Invalidate Disable"]
192    #[inline(always)]
193    pub fn aidis(&mut self) -> AIDIS_W {
194        AIDIS_W::new(self)
195    }
196    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
197    #[inline(always)]
198    pub fn iccdis(&mut self) -> ICCDIS_W {
199        ICCDIS_W::new(self)
200    }
201    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
202    #[inline(always)]
203    pub fn ebicdis(&mut self) -> EBICDIS_W {
204        EBICDIS_W::new(self)
205    }
206    #[doc = "Bit 8 - Prefetch Mode"]
207    #[inline(always)]
208    pub fn prefetch(&mut self) -> PREFETCH_W {
209        PREFETCH_W::new(self)
210    }
211    #[doc = "Bit 9 - AHB_HPROT Mode"]
212    #[inline(always)]
213    pub fn usehprot(&mut self) -> USEHPROT_W {
214        USEHPROT_W::new(self)
215    }
216    #[doc = "Bits 24:25 - Read Mode"]
217    #[inline(always)]
218    pub fn mode(&mut self) -> MODE_W {
219        MODE_W::new(self)
220    }
221    #[doc = "Bit 28 - Suppress Conditional Branch Target Perfetch"]
222    #[inline(always)]
223    pub fn scbtp(&mut self) -> SCBTP_W {
224        SCBTP_W::new(self)
225    }
226    #[doc = "Writes raw bits to the register."]
227    #[inline(always)]
228    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
229        self.0.bits(bits);
230        self
231    }
232}
233#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
234pub struct READCTRL_SPEC;
235impl crate::RegisterSpec for READCTRL_SPEC {
236    type Ux = u32;
237}
238#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
239impl crate::Readable for READCTRL_SPEC {
240    type Reader = R;
241}
242#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
243impl crate::Writable for READCTRL_SPEC {
244    type Writer = W;
245}
246#[doc = "`reset()` method sets READCTRL to value 0x0100_0100"]
247impl crate::Resettable for READCTRL_SPEC {
248    #[inline(always)]
249    fn reset_value() -> Self::Ux {
250        0x0100_0100
251    }
252}
efm32gg12b130_pac/msc/readctrl.rs

efm32gg12b130_pac/msc/
readctrl.rs
