efm32gg12b130_pac/msc/
ien.rs1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IEN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IEN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IEN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IEN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ERASE` reader - ERASE Interrupt Enable"]
38pub type ERASE_R = crate::BitReader<bool>;
39#[doc = "Field `ERASE` writer - ERASE Interrupt Enable"]
40pub type ERASE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 0>;
41#[doc = "Field `WRITE` reader - WRITE Interrupt Enable"]
42pub type WRITE_R = crate::BitReader<bool>;
43#[doc = "Field `WRITE` writer - WRITE Interrupt Enable"]
44pub type WRITE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 1>;
45#[doc = "Field `CHOF` reader - CHOF Interrupt Enable"]
46pub type CHOF_R = crate::BitReader<bool>;
47#[doc = "Field `CHOF` writer - CHOF Interrupt Enable"]
48pub type CHOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 2>;
49#[doc = "Field `CMOF` reader - CMOF Interrupt Enable"]
50pub type CMOF_R = crate::BitReader<bool>;
51#[doc = "Field `CMOF` writer - CMOF Interrupt Enable"]
52pub type CMOF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 3>;
53#[doc = "Field `PWRUPF` reader - PWRUPF Interrupt Enable"]
54pub type PWRUPF_R = crate::BitReader<bool>;
55#[doc = "Field `PWRUPF` writer - PWRUPF Interrupt Enable"]
56pub type PWRUPF_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 4>;
57#[doc = "Field `ICACHERR` reader - ICACHERR Interrupt Enable"]
58pub type ICACHERR_R = crate::BitReader<bool>;
59#[doc = "Field `ICACHERR` writer - ICACHERR Interrupt Enable"]
60pub type ICACHERR_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 5>;
61#[doc = "Field `WDATAOV` reader - WDATAOV Interrupt Enable"]
62pub type WDATAOV_R = crate::BitReader<bool>;
63#[doc = "Field `WDATAOV` writer - WDATAOV Interrupt Enable"]
64pub type WDATAOV_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 6>;
65#[doc = "Field `LVEWRITE` reader - LVEWRITE Interrupt Enable"]
66pub type LVEWRITE_R = crate::BitReader<bool>;
67#[doc = "Field `LVEWRITE` writer - LVEWRITE Interrupt Enable"]
68pub type LVEWRITE_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 8>;
69#[doc = "Field `RAMERR1B` reader - RAMERR1B Interrupt Enable"]
70pub type RAMERR1B_R = crate::BitReader<bool>;
71#[doc = "Field `RAMERR1B` writer - RAMERR1B Interrupt Enable"]
72pub type RAMERR1B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 16>;
73#[doc = "Field `RAMERR2B` reader - RAMERR2B Interrupt Enable"]
74pub type RAMERR2B_R = crate::BitReader<bool>;
75#[doc = "Field `RAMERR2B` writer - RAMERR2B Interrupt Enable"]
76pub type RAMERR2B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 17>;
77#[doc = "Field `RAM1ERR1B` reader - RAM1ERR1B Interrupt Enable"]
78pub type RAM1ERR1B_R = crate::BitReader<bool>;
79#[doc = "Field `RAM1ERR1B` writer - RAM1ERR1B Interrupt Enable"]
80pub type RAM1ERR1B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 18>;
81#[doc = "Field `RAM1ERR2B` reader - RAM1ERR2B Interrupt Enable"]
82pub type RAM1ERR2B_R = crate::BitReader<bool>;
83#[doc = "Field `RAM1ERR2B` writer - RAM1ERR2B Interrupt Enable"]
84pub type RAM1ERR2B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 19>;
85#[doc = "Field `RAM2ERR1B` reader - RAM2ERR1B Interrupt Enable"]
86pub type RAM2ERR1B_R = crate::BitReader<bool>;
87#[doc = "Field `RAM2ERR1B` writer - RAM2ERR1B Interrupt Enable"]
88pub type RAM2ERR1B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 20>;
89#[doc = "Field `RAM2ERR2B` reader - RAM2ERR2B Interrupt Enable"]
90pub type RAM2ERR2B_R = crate::BitReader<bool>;
91#[doc = "Field `RAM2ERR2B` writer - RAM2ERR2B Interrupt Enable"]
92pub type RAM2ERR2B_W<'a> = crate::BitWriter<'a, u32, IEN_SPEC, bool, 21>;
93impl R {
94 #[doc = "Bit 0 - ERASE Interrupt Enable"]
95 #[inline(always)]
96 pub fn erase(&self) -> ERASE_R {
97 ERASE_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - WRITE Interrupt Enable"]
100 #[inline(always)]
101 pub fn write(&self) -> WRITE_R {
102 WRITE_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bit 2 - CHOF Interrupt Enable"]
105 #[inline(always)]
106 pub fn chof(&self) -> CHOF_R {
107 CHOF_R::new(((self.bits >> 2) & 1) != 0)
108 }
109 #[doc = "Bit 3 - CMOF Interrupt Enable"]
110 #[inline(always)]
111 pub fn cmof(&self) -> CMOF_R {
112 CMOF_R::new(((self.bits >> 3) & 1) != 0)
113 }
114 #[doc = "Bit 4 - PWRUPF Interrupt Enable"]
115 #[inline(always)]
116 pub fn pwrupf(&self) -> PWRUPF_R {
117 PWRUPF_R::new(((self.bits >> 4) & 1) != 0)
118 }
119 #[doc = "Bit 5 - ICACHERR Interrupt Enable"]
120 #[inline(always)]
121 pub fn icacherr(&self) -> ICACHERR_R {
122 ICACHERR_R::new(((self.bits >> 5) & 1) != 0)
123 }
124 #[doc = "Bit 6 - WDATAOV Interrupt Enable"]
125 #[inline(always)]
126 pub fn wdataov(&self) -> WDATAOV_R {
127 WDATAOV_R::new(((self.bits >> 6) & 1) != 0)
128 }
129 #[doc = "Bit 8 - LVEWRITE Interrupt Enable"]
130 #[inline(always)]
131 pub fn lvewrite(&self) -> LVEWRITE_R {
132 LVEWRITE_R::new(((self.bits >> 8) & 1) != 0)
133 }
134 #[doc = "Bit 16 - RAMERR1B Interrupt Enable"]
135 #[inline(always)]
136 pub fn ramerr1b(&self) -> RAMERR1B_R {
137 RAMERR1B_R::new(((self.bits >> 16) & 1) != 0)
138 }
139 #[doc = "Bit 17 - RAMERR2B Interrupt Enable"]
140 #[inline(always)]
141 pub fn ramerr2b(&self) -> RAMERR2B_R {
142 RAMERR2B_R::new(((self.bits >> 17) & 1) != 0)
143 }
144 #[doc = "Bit 18 - RAM1ERR1B Interrupt Enable"]
145 #[inline(always)]
146 pub fn ram1err1b(&self) -> RAM1ERR1B_R {
147 RAM1ERR1B_R::new(((self.bits >> 18) & 1) != 0)
148 }
149 #[doc = "Bit 19 - RAM1ERR2B Interrupt Enable"]
150 #[inline(always)]
151 pub fn ram1err2b(&self) -> RAM1ERR2B_R {
152 RAM1ERR2B_R::new(((self.bits >> 19) & 1) != 0)
153 }
154 #[doc = "Bit 20 - RAM2ERR1B Interrupt Enable"]
155 #[inline(always)]
156 pub fn ram2err1b(&self) -> RAM2ERR1B_R {
157 RAM2ERR1B_R::new(((self.bits >> 20) & 1) != 0)
158 }
159 #[doc = "Bit 21 - RAM2ERR2B Interrupt Enable"]
160 #[inline(always)]
161 pub fn ram2err2b(&self) -> RAM2ERR2B_R {
162 RAM2ERR2B_R::new(((self.bits >> 21) & 1) != 0)
163 }
164}
165impl W {
166 #[doc = "Bit 0 - ERASE Interrupt Enable"]
167 #[inline(always)]
168 pub fn erase(&mut self) -> ERASE_W {
169 ERASE_W::new(self)
170 }
171 #[doc = "Bit 1 - WRITE Interrupt Enable"]
172 #[inline(always)]
173 pub fn write(&mut self) -> WRITE_W {
174 WRITE_W::new(self)
175 }
176 #[doc = "Bit 2 - CHOF Interrupt Enable"]
177 #[inline(always)]
178 pub fn chof(&mut self) -> CHOF_W {
179 CHOF_W::new(self)
180 }
181 #[doc = "Bit 3 - CMOF Interrupt Enable"]
182 #[inline(always)]
183 pub fn cmof(&mut self) -> CMOF_W {
184 CMOF_W::new(self)
185 }
186 #[doc = "Bit 4 - PWRUPF Interrupt Enable"]
187 #[inline(always)]
188 pub fn pwrupf(&mut self) -> PWRUPF_W {
189 PWRUPF_W::new(self)
190 }
191 #[doc = "Bit 5 - ICACHERR Interrupt Enable"]
192 #[inline(always)]
193 pub fn icacherr(&mut self) -> ICACHERR_W {
194 ICACHERR_W::new(self)
195 }
196 #[doc = "Bit 6 - WDATAOV Interrupt Enable"]
197 #[inline(always)]
198 pub fn wdataov(&mut self) -> WDATAOV_W {
199 WDATAOV_W::new(self)
200 }
201 #[doc = "Bit 8 - LVEWRITE Interrupt Enable"]
202 #[inline(always)]
203 pub fn lvewrite(&mut self) -> LVEWRITE_W {
204 LVEWRITE_W::new(self)
205 }
206 #[doc = "Bit 16 - RAMERR1B Interrupt Enable"]
207 #[inline(always)]
208 pub fn ramerr1b(&mut self) -> RAMERR1B_W {
209 RAMERR1B_W::new(self)
210 }
211 #[doc = "Bit 17 - RAMERR2B Interrupt Enable"]
212 #[inline(always)]
213 pub fn ramerr2b(&mut self) -> RAMERR2B_W {
214 RAMERR2B_W::new(self)
215 }
216 #[doc = "Bit 18 - RAM1ERR1B Interrupt Enable"]
217 #[inline(always)]
218 pub fn ram1err1b(&mut self) -> RAM1ERR1B_W {
219 RAM1ERR1B_W::new(self)
220 }
221 #[doc = "Bit 19 - RAM1ERR2B Interrupt Enable"]
222 #[inline(always)]
223 pub fn ram1err2b(&mut self) -> RAM1ERR2B_W {
224 RAM1ERR2B_W::new(self)
225 }
226 #[doc = "Bit 20 - RAM2ERR1B Interrupt Enable"]
227 #[inline(always)]
228 pub fn ram2err1b(&mut self) -> RAM2ERR1B_W {
229 RAM2ERR1B_W::new(self)
230 }
231 #[doc = "Bit 21 - RAM2ERR2B Interrupt Enable"]
232 #[inline(always)]
233 pub fn ram2err2b(&mut self) -> RAM2ERR2B_W {
234 RAM2ERR2B_W::new(self)
235 }
236 #[doc = "Writes raw bits to the register."]
237 #[inline(always)]
238 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239 self.0.bits(bits);
240 self
241 }
242}
243#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
244pub struct IEN_SPEC;
245impl crate::RegisterSpec for IEN_SPEC {
246 type Ux = u32;
247}
248#[doc = "`read()` method returns [ien::R](R) reader structure"]
249impl crate::Readable for IEN_SPEC {
250 type Reader = R;
251}
252#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
253impl crate::Writable for IEN_SPEC {
254 type Writer = W;
255}
256#[doc = "`reset()` method sets IEN to value 0"]
257impl crate::Resettable for IEN_SPEC {
258 #[inline(always)]
259 fn reset_value() -> Self::Ux {
260 0
261 }
262}