efm32gg12b110_pac/prs/
ch11_ctrl.rs

1#[doc = "Register `CH11_CTRL` reader"]
2pub struct R(crate::R<CH11_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH11_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH11_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH11_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH11_CTRL` writer"]
17pub struct W(crate::W<CH11_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH11_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH11_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH11_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH11_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRS = 2,
51    #[doc = "4: Analog Comparator 0"]
52    ACMP0 = 4,
53    #[doc = "5: Analog Comparator 1"]
54    ACMP1 = 5,
55    #[doc = "6: Analog to Digital Converter 0"]
56    ADC0 = 6,
57    #[doc = "7: Real-Time Counter"]
58    RTC = 7,
59    #[doc = "8: Real-Time Counter and Calendar"]
60    RTCC = 8,
61    #[doc = "9: General purpose Input/Output"]
62    GPIOL = 9,
63    #[doc = "10: General purpose Input/Output"]
64    GPIOH = 10,
65    #[doc = "11: Low Energy Timer 0"]
66    LETIMER0 = 11,
67    #[doc = "12: Low Energy Timer 1"]
68    LETIMER1 = 12,
69    #[doc = "13: Pulse Counter 0"]
70    PCNT0 = 13,
71    #[doc = "14: Pulse Counter 1"]
72    PCNT1 = 14,
73    #[doc = "15: Pulse Counter 2"]
74    PCNT2 = 15,
75    #[doc = "16: CRYOTIMER"]
76    CRYOTIMER = 16,
77    #[doc = "17: Clock Management Unit"]
78    CMU = 17,
79    #[doc = "23: Digital to Analog Converter 0"]
80    VDAC0 = 23,
81    #[doc = "24: Low Energy Sensor Interface"]
82    LESENSEL = 24,
83    #[doc = "25: Low Energy Sensor Interface"]
84    LESENSEH = 25,
85    #[doc = "26: Low Energy Sensor Interface"]
86    LESENSED = 26,
87    #[doc = "27: Low Energy Sensor Interface"]
88    LESENSE = 27,
89    #[doc = "28: Analog Comparator 2"]
90    ACMP2 = 28,
91    #[doc = "29: Analog to Digital Converter 0"]
92    ADC1 = 29,
93    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
94    USART0 = 48,
95    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
96    USART1 = 49,
97    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
98    USART2 = 50,
99    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
100    USART3 = 51,
101    #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
102    USART4 = 52,
103    #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
104    UART0 = 54,
105    #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
106    UART1 = 55,
107    #[doc = "60: Timer 0"]
108    TIMER0 = 60,
109    #[doc = "61: Timer 1"]
110    TIMER1 = 61,
111    #[doc = "62: Timer 2"]
112    TIMER2 = 62,
113    #[doc = "67: `1000011`"]
114    CM4 = 67,
115    #[doc = "80: Timer 3"]
116    TIMER3 = 80,
117    #[doc = "82: Wide Timer 0"]
118    WTIMER0 = 82,
119    #[doc = "83: Wide Timer 0"]
120    WTIMER1 = 83,
121    #[doc = "121: PDM Interface"]
122    PDM = 121,
123}
124impl From<SOURCESEL_A> for u8 {
125    #[inline(always)]
126    fn from(variant: SOURCESEL_A) -> Self {
127        variant as _
128    }
129}
130#[doc = "Field `SOURCESEL` reader - Source Select"]
131pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
132impl SOURCESEL_R {
133    #[doc = "Get enumerated values variant"]
134    #[inline(always)]
135    pub fn variant(&self) -> Option<SOURCESEL_A> {
136        match self.bits {
137            0 => Some(SOURCESEL_A::NONE),
138            1 => Some(SOURCESEL_A::PRSL),
139            2 => Some(SOURCESEL_A::PRS),
140            4 => Some(SOURCESEL_A::ACMP0),
141            5 => Some(SOURCESEL_A::ACMP1),
142            6 => Some(SOURCESEL_A::ADC0),
143            7 => Some(SOURCESEL_A::RTC),
144            8 => Some(SOURCESEL_A::RTCC),
145            9 => Some(SOURCESEL_A::GPIOL),
146            10 => Some(SOURCESEL_A::GPIOH),
147            11 => Some(SOURCESEL_A::LETIMER0),
148            12 => Some(SOURCESEL_A::LETIMER1),
149            13 => Some(SOURCESEL_A::PCNT0),
150            14 => Some(SOURCESEL_A::PCNT1),
151            15 => Some(SOURCESEL_A::PCNT2),
152            16 => Some(SOURCESEL_A::CRYOTIMER),
153            17 => Some(SOURCESEL_A::CMU),
154            23 => Some(SOURCESEL_A::VDAC0),
155            24 => Some(SOURCESEL_A::LESENSEL),
156            25 => Some(SOURCESEL_A::LESENSEH),
157            26 => Some(SOURCESEL_A::LESENSED),
158            27 => Some(SOURCESEL_A::LESENSE),
159            28 => Some(SOURCESEL_A::ACMP2),
160            29 => Some(SOURCESEL_A::ADC1),
161            48 => Some(SOURCESEL_A::USART0),
162            49 => Some(SOURCESEL_A::USART1),
163            50 => Some(SOURCESEL_A::USART2),
164            51 => Some(SOURCESEL_A::USART3),
165            52 => Some(SOURCESEL_A::USART4),
166            54 => Some(SOURCESEL_A::UART0),
167            55 => Some(SOURCESEL_A::UART1),
168            60 => Some(SOURCESEL_A::TIMER0),
169            61 => Some(SOURCESEL_A::TIMER1),
170            62 => Some(SOURCESEL_A::TIMER2),
171            67 => Some(SOURCESEL_A::CM4),
172            80 => Some(SOURCESEL_A::TIMER3),
173            82 => Some(SOURCESEL_A::WTIMER0),
174            83 => Some(SOURCESEL_A::WTIMER1),
175            121 => Some(SOURCESEL_A::PDM),
176            _ => None,
177        }
178    }
179    #[doc = "Checks if the value of the field is `NONE`"]
180    #[inline(always)]
181    pub fn is_none(&self) -> bool {
182        *self == SOURCESEL_A::NONE
183    }
184    #[doc = "Checks if the value of the field is `PRSL`"]
185    #[inline(always)]
186    pub fn is_prsl(&self) -> bool {
187        *self == SOURCESEL_A::PRSL
188    }
189    #[doc = "Checks if the value of the field is `PRS`"]
190    #[inline(always)]
191    pub fn is_prs(&self) -> bool {
192        *self == SOURCESEL_A::PRS
193    }
194    #[doc = "Checks if the value of the field is `ACMP0`"]
195    #[inline(always)]
196    pub fn is_acmp0(&self) -> bool {
197        *self == SOURCESEL_A::ACMP0
198    }
199    #[doc = "Checks if the value of the field is `ACMP1`"]
200    #[inline(always)]
201    pub fn is_acmp1(&self) -> bool {
202        *self == SOURCESEL_A::ACMP1
203    }
204    #[doc = "Checks if the value of the field is `ADC0`"]
205    #[inline(always)]
206    pub fn is_adc0(&self) -> bool {
207        *self == SOURCESEL_A::ADC0
208    }
209    #[doc = "Checks if the value of the field is `RTC`"]
210    #[inline(always)]
211    pub fn is_rtc(&self) -> bool {
212        *self == SOURCESEL_A::RTC
213    }
214    #[doc = "Checks if the value of the field is `RTCC`"]
215    #[inline(always)]
216    pub fn is_rtcc(&self) -> bool {
217        *self == SOURCESEL_A::RTCC
218    }
219    #[doc = "Checks if the value of the field is `GPIOL`"]
220    #[inline(always)]
221    pub fn is_gpiol(&self) -> bool {
222        *self == SOURCESEL_A::GPIOL
223    }
224    #[doc = "Checks if the value of the field is `GPIOH`"]
225    #[inline(always)]
226    pub fn is_gpioh(&self) -> bool {
227        *self == SOURCESEL_A::GPIOH
228    }
229    #[doc = "Checks if the value of the field is `LETIMER0`"]
230    #[inline(always)]
231    pub fn is_letimer0(&self) -> bool {
232        *self == SOURCESEL_A::LETIMER0
233    }
234    #[doc = "Checks if the value of the field is `LETIMER1`"]
235    #[inline(always)]
236    pub fn is_letimer1(&self) -> bool {
237        *self == SOURCESEL_A::LETIMER1
238    }
239    #[doc = "Checks if the value of the field is `PCNT0`"]
240    #[inline(always)]
241    pub fn is_pcnt0(&self) -> bool {
242        *self == SOURCESEL_A::PCNT0
243    }
244    #[doc = "Checks if the value of the field is `PCNT1`"]
245    #[inline(always)]
246    pub fn is_pcnt1(&self) -> bool {
247        *self == SOURCESEL_A::PCNT1
248    }
249    #[doc = "Checks if the value of the field is `PCNT2`"]
250    #[inline(always)]
251    pub fn is_pcnt2(&self) -> bool {
252        *self == SOURCESEL_A::PCNT2
253    }
254    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
255    #[inline(always)]
256    pub fn is_cryotimer(&self) -> bool {
257        *self == SOURCESEL_A::CRYOTIMER
258    }
259    #[doc = "Checks if the value of the field is `CMU`"]
260    #[inline(always)]
261    pub fn is_cmu(&self) -> bool {
262        *self == SOURCESEL_A::CMU
263    }
264    #[doc = "Checks if the value of the field is `VDAC0`"]
265    #[inline(always)]
266    pub fn is_vdac0(&self) -> bool {
267        *self == SOURCESEL_A::VDAC0
268    }
269    #[doc = "Checks if the value of the field is `LESENSEL`"]
270    #[inline(always)]
271    pub fn is_lesensel(&self) -> bool {
272        *self == SOURCESEL_A::LESENSEL
273    }
274    #[doc = "Checks if the value of the field is `LESENSEH`"]
275    #[inline(always)]
276    pub fn is_lesenseh(&self) -> bool {
277        *self == SOURCESEL_A::LESENSEH
278    }
279    #[doc = "Checks if the value of the field is `LESENSED`"]
280    #[inline(always)]
281    pub fn is_lesensed(&self) -> bool {
282        *self == SOURCESEL_A::LESENSED
283    }
284    #[doc = "Checks if the value of the field is `LESENSE`"]
285    #[inline(always)]
286    pub fn is_lesense(&self) -> bool {
287        *self == SOURCESEL_A::LESENSE
288    }
289    #[doc = "Checks if the value of the field is `ACMP2`"]
290    #[inline(always)]
291    pub fn is_acmp2(&self) -> bool {
292        *self == SOURCESEL_A::ACMP2
293    }
294    #[doc = "Checks if the value of the field is `ADC1`"]
295    #[inline(always)]
296    pub fn is_adc1(&self) -> bool {
297        *self == SOURCESEL_A::ADC1
298    }
299    #[doc = "Checks if the value of the field is `USART0`"]
300    #[inline(always)]
301    pub fn is_usart0(&self) -> bool {
302        *self == SOURCESEL_A::USART0
303    }
304    #[doc = "Checks if the value of the field is `USART1`"]
305    #[inline(always)]
306    pub fn is_usart1(&self) -> bool {
307        *self == SOURCESEL_A::USART1
308    }
309    #[doc = "Checks if the value of the field is `USART2`"]
310    #[inline(always)]
311    pub fn is_usart2(&self) -> bool {
312        *self == SOURCESEL_A::USART2
313    }
314    #[doc = "Checks if the value of the field is `USART3`"]
315    #[inline(always)]
316    pub fn is_usart3(&self) -> bool {
317        *self == SOURCESEL_A::USART3
318    }
319    #[doc = "Checks if the value of the field is `USART4`"]
320    #[inline(always)]
321    pub fn is_usart4(&self) -> bool {
322        *self == SOURCESEL_A::USART4
323    }
324    #[doc = "Checks if the value of the field is `UART0`"]
325    #[inline(always)]
326    pub fn is_uart0(&self) -> bool {
327        *self == SOURCESEL_A::UART0
328    }
329    #[doc = "Checks if the value of the field is `UART1`"]
330    #[inline(always)]
331    pub fn is_uart1(&self) -> bool {
332        *self == SOURCESEL_A::UART1
333    }
334    #[doc = "Checks if the value of the field is `TIMER0`"]
335    #[inline(always)]
336    pub fn is_timer0(&self) -> bool {
337        *self == SOURCESEL_A::TIMER0
338    }
339    #[doc = "Checks if the value of the field is `TIMER1`"]
340    #[inline(always)]
341    pub fn is_timer1(&self) -> bool {
342        *self == SOURCESEL_A::TIMER1
343    }
344    #[doc = "Checks if the value of the field is `TIMER2`"]
345    #[inline(always)]
346    pub fn is_timer2(&self) -> bool {
347        *self == SOURCESEL_A::TIMER2
348    }
349    #[doc = "Checks if the value of the field is `CM4`"]
350    #[inline(always)]
351    pub fn is_cm4(&self) -> bool {
352        *self == SOURCESEL_A::CM4
353    }
354    #[doc = "Checks if the value of the field is `TIMER3`"]
355    #[inline(always)]
356    pub fn is_timer3(&self) -> bool {
357        *self == SOURCESEL_A::TIMER3
358    }
359    #[doc = "Checks if the value of the field is `WTIMER0`"]
360    #[inline(always)]
361    pub fn is_wtimer0(&self) -> bool {
362        *self == SOURCESEL_A::WTIMER0
363    }
364    #[doc = "Checks if the value of the field is `WTIMER1`"]
365    #[inline(always)]
366    pub fn is_wtimer1(&self) -> bool {
367        *self == SOURCESEL_A::WTIMER1
368    }
369    #[doc = "Checks if the value of the field is `PDM`"]
370    #[inline(always)]
371    pub fn is_pdm(&self) -> bool {
372        *self == SOURCESEL_A::PDM
373    }
374}
375#[doc = "Field `SOURCESEL` writer - Source Select"]
376pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH11_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
377impl<'a> SOURCESEL_W<'a> {
378    #[doc = "No source selected"]
379    #[inline(always)]
380    pub fn none(self) -> &'a mut W {
381        self.variant(SOURCESEL_A::NONE)
382    }
383    #[doc = "Peripheral Reflex System"]
384    #[inline(always)]
385    pub fn prsl(self) -> &'a mut W {
386        self.variant(SOURCESEL_A::PRSL)
387    }
388    #[doc = "Peripheral Reflex System"]
389    #[inline(always)]
390    pub fn prs(self) -> &'a mut W {
391        self.variant(SOURCESEL_A::PRS)
392    }
393    #[doc = "Analog Comparator 0"]
394    #[inline(always)]
395    pub fn acmp0(self) -> &'a mut W {
396        self.variant(SOURCESEL_A::ACMP0)
397    }
398    #[doc = "Analog Comparator 1"]
399    #[inline(always)]
400    pub fn acmp1(self) -> &'a mut W {
401        self.variant(SOURCESEL_A::ACMP1)
402    }
403    #[doc = "Analog to Digital Converter 0"]
404    #[inline(always)]
405    pub fn adc0(self) -> &'a mut W {
406        self.variant(SOURCESEL_A::ADC0)
407    }
408    #[doc = "Real-Time Counter"]
409    #[inline(always)]
410    pub fn rtc(self) -> &'a mut W {
411        self.variant(SOURCESEL_A::RTC)
412    }
413    #[doc = "Real-Time Counter and Calendar"]
414    #[inline(always)]
415    pub fn rtcc(self) -> &'a mut W {
416        self.variant(SOURCESEL_A::RTCC)
417    }
418    #[doc = "General purpose Input/Output"]
419    #[inline(always)]
420    pub fn gpiol(self) -> &'a mut W {
421        self.variant(SOURCESEL_A::GPIOL)
422    }
423    #[doc = "General purpose Input/Output"]
424    #[inline(always)]
425    pub fn gpioh(self) -> &'a mut W {
426        self.variant(SOURCESEL_A::GPIOH)
427    }
428    #[doc = "Low Energy Timer 0"]
429    #[inline(always)]
430    pub fn letimer0(self) -> &'a mut W {
431        self.variant(SOURCESEL_A::LETIMER0)
432    }
433    #[doc = "Low Energy Timer 1"]
434    #[inline(always)]
435    pub fn letimer1(self) -> &'a mut W {
436        self.variant(SOURCESEL_A::LETIMER1)
437    }
438    #[doc = "Pulse Counter 0"]
439    #[inline(always)]
440    pub fn pcnt0(self) -> &'a mut W {
441        self.variant(SOURCESEL_A::PCNT0)
442    }
443    #[doc = "Pulse Counter 1"]
444    #[inline(always)]
445    pub fn pcnt1(self) -> &'a mut W {
446        self.variant(SOURCESEL_A::PCNT1)
447    }
448    #[doc = "Pulse Counter 2"]
449    #[inline(always)]
450    pub fn pcnt2(self) -> &'a mut W {
451        self.variant(SOURCESEL_A::PCNT2)
452    }
453    #[doc = "CRYOTIMER"]
454    #[inline(always)]
455    pub fn cryotimer(self) -> &'a mut W {
456        self.variant(SOURCESEL_A::CRYOTIMER)
457    }
458    #[doc = "Clock Management Unit"]
459    #[inline(always)]
460    pub fn cmu(self) -> &'a mut W {
461        self.variant(SOURCESEL_A::CMU)
462    }
463    #[doc = "Digital to Analog Converter 0"]
464    #[inline(always)]
465    pub fn vdac0(self) -> &'a mut W {
466        self.variant(SOURCESEL_A::VDAC0)
467    }
468    #[doc = "Low Energy Sensor Interface"]
469    #[inline(always)]
470    pub fn lesensel(self) -> &'a mut W {
471        self.variant(SOURCESEL_A::LESENSEL)
472    }
473    #[doc = "Low Energy Sensor Interface"]
474    #[inline(always)]
475    pub fn lesenseh(self) -> &'a mut W {
476        self.variant(SOURCESEL_A::LESENSEH)
477    }
478    #[doc = "Low Energy Sensor Interface"]
479    #[inline(always)]
480    pub fn lesensed(self) -> &'a mut W {
481        self.variant(SOURCESEL_A::LESENSED)
482    }
483    #[doc = "Low Energy Sensor Interface"]
484    #[inline(always)]
485    pub fn lesense(self) -> &'a mut W {
486        self.variant(SOURCESEL_A::LESENSE)
487    }
488    #[doc = "Analog Comparator 2"]
489    #[inline(always)]
490    pub fn acmp2(self) -> &'a mut W {
491        self.variant(SOURCESEL_A::ACMP2)
492    }
493    #[doc = "Analog to Digital Converter 0"]
494    #[inline(always)]
495    pub fn adc1(self) -> &'a mut W {
496        self.variant(SOURCESEL_A::ADC1)
497    }
498    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
499    #[inline(always)]
500    pub fn usart0(self) -> &'a mut W {
501        self.variant(SOURCESEL_A::USART0)
502    }
503    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
504    #[inline(always)]
505    pub fn usart1(self) -> &'a mut W {
506        self.variant(SOURCESEL_A::USART1)
507    }
508    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
509    #[inline(always)]
510    pub fn usart2(self) -> &'a mut W {
511        self.variant(SOURCESEL_A::USART2)
512    }
513    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
514    #[inline(always)]
515    pub fn usart3(self) -> &'a mut W {
516        self.variant(SOURCESEL_A::USART3)
517    }
518    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
519    #[inline(always)]
520    pub fn usart4(self) -> &'a mut W {
521        self.variant(SOURCESEL_A::USART4)
522    }
523    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
524    #[inline(always)]
525    pub fn uart0(self) -> &'a mut W {
526        self.variant(SOURCESEL_A::UART0)
527    }
528    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
529    #[inline(always)]
530    pub fn uart1(self) -> &'a mut W {
531        self.variant(SOURCESEL_A::UART1)
532    }
533    #[doc = "Timer 0"]
534    #[inline(always)]
535    pub fn timer0(self) -> &'a mut W {
536        self.variant(SOURCESEL_A::TIMER0)
537    }
538    #[doc = "Timer 1"]
539    #[inline(always)]
540    pub fn timer1(self) -> &'a mut W {
541        self.variant(SOURCESEL_A::TIMER1)
542    }
543    #[doc = "Timer 2"]
544    #[inline(always)]
545    pub fn timer2(self) -> &'a mut W {
546        self.variant(SOURCESEL_A::TIMER2)
547    }
548    #[doc = "`1000011`"]
549    #[inline(always)]
550    pub fn cm4(self) -> &'a mut W {
551        self.variant(SOURCESEL_A::CM4)
552    }
553    #[doc = "Timer 3"]
554    #[inline(always)]
555    pub fn timer3(self) -> &'a mut W {
556        self.variant(SOURCESEL_A::TIMER3)
557    }
558    #[doc = "Wide Timer 0"]
559    #[inline(always)]
560    pub fn wtimer0(self) -> &'a mut W {
561        self.variant(SOURCESEL_A::WTIMER0)
562    }
563    #[doc = "Wide Timer 0"]
564    #[inline(always)]
565    pub fn wtimer1(self) -> &'a mut W {
566        self.variant(SOURCESEL_A::WTIMER1)
567    }
568    #[doc = "PDM Interface"]
569    #[inline(always)]
570    pub fn pdm(self) -> &'a mut W {
571        self.variant(SOURCESEL_A::PDM)
572    }
573}
574#[doc = "Edge Detect Select\n\nValue on reset: 0"]
575#[derive(Clone, Copy, Debug, PartialEq)]
576#[repr(u8)]
577pub enum EDSEL_A {
578    #[doc = "0: Signal is left as it is"]
579    OFF = 0,
580    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
581    POSEDGE = 1,
582    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
583    NEGEDGE = 2,
584    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
585    BOTHEDGES = 3,
586}
587impl From<EDSEL_A> for u8 {
588    #[inline(always)]
589    fn from(variant: EDSEL_A) -> Self {
590        variant as _
591    }
592}
593#[doc = "Field `EDSEL` reader - Edge Detect Select"]
594pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
595impl EDSEL_R {
596    #[doc = "Get enumerated values variant"]
597    #[inline(always)]
598    pub fn variant(&self) -> EDSEL_A {
599        match self.bits {
600            0 => EDSEL_A::OFF,
601            1 => EDSEL_A::POSEDGE,
602            2 => EDSEL_A::NEGEDGE,
603            3 => EDSEL_A::BOTHEDGES,
604            _ => unreachable!(),
605        }
606    }
607    #[doc = "Checks if the value of the field is `OFF`"]
608    #[inline(always)]
609    pub fn is_off(&self) -> bool {
610        *self == EDSEL_A::OFF
611    }
612    #[doc = "Checks if the value of the field is `POSEDGE`"]
613    #[inline(always)]
614    pub fn is_posedge(&self) -> bool {
615        *self == EDSEL_A::POSEDGE
616    }
617    #[doc = "Checks if the value of the field is `NEGEDGE`"]
618    #[inline(always)]
619    pub fn is_negedge(&self) -> bool {
620        *self == EDSEL_A::NEGEDGE
621    }
622    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
623    #[inline(always)]
624    pub fn is_bothedges(&self) -> bool {
625        *self == EDSEL_A::BOTHEDGES
626    }
627}
628#[doc = "Field `EDSEL` writer - Edge Detect Select"]
629pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH11_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
630impl<'a> EDSEL_W<'a> {
631    #[doc = "Signal is left as it is"]
632    #[inline(always)]
633    pub fn off(self) -> &'a mut W {
634        self.variant(EDSEL_A::OFF)
635    }
636    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
637    #[inline(always)]
638    pub fn posedge(self) -> &'a mut W {
639        self.variant(EDSEL_A::POSEDGE)
640    }
641    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
642    #[inline(always)]
643    pub fn negedge(self) -> &'a mut W {
644        self.variant(EDSEL_A::NEGEDGE)
645    }
646    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
647    #[inline(always)]
648    pub fn bothedges(self) -> &'a mut W {
649        self.variant(EDSEL_A::BOTHEDGES)
650    }
651}
652#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
653pub type STRETCH_R = crate::BitReader<bool>;
654#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
655pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 25>;
656#[doc = "Field `INV` reader - Invert Channel"]
657pub type INV_R = crate::BitReader<bool>;
658#[doc = "Field `INV` writer - Invert Channel"]
659pub type INV_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 26>;
660#[doc = "Field `ORPREV` reader - Or Previous"]
661pub type ORPREV_R = crate::BitReader<bool>;
662#[doc = "Field `ORPREV` writer - Or Previous"]
663pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 27>;
664#[doc = "Field `ANDNEXT` reader - And Next"]
665pub type ANDNEXT_R = crate::BitReader<bool>;
666#[doc = "Field `ANDNEXT` writer - And Next"]
667pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 28>;
668#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
669pub type ASYNC_R = crate::BitReader<bool>;
670#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
671pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH11_CTRL_SPEC, bool, 30>;
672impl R {
673    #[doc = "Bits 0:2 - Signal Select"]
674    #[inline(always)]
675    pub fn sigsel(&self) -> SIGSEL_R {
676        SIGSEL_R::new((self.bits & 7) as u8)
677    }
678    #[doc = "Bits 8:14 - Source Select"]
679    #[inline(always)]
680    pub fn sourcesel(&self) -> SOURCESEL_R {
681        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
682    }
683    #[doc = "Bits 20:21 - Edge Detect Select"]
684    #[inline(always)]
685    pub fn edsel(&self) -> EDSEL_R {
686        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
687    }
688    #[doc = "Bit 25 - Stretch Channel Output"]
689    #[inline(always)]
690    pub fn stretch(&self) -> STRETCH_R {
691        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
692    }
693    #[doc = "Bit 26 - Invert Channel"]
694    #[inline(always)]
695    pub fn inv(&self) -> INV_R {
696        INV_R::new(((self.bits >> 26) & 1) != 0)
697    }
698    #[doc = "Bit 27 - Or Previous"]
699    #[inline(always)]
700    pub fn orprev(&self) -> ORPREV_R {
701        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
702    }
703    #[doc = "Bit 28 - And Next"]
704    #[inline(always)]
705    pub fn andnext(&self) -> ANDNEXT_R {
706        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
707    }
708    #[doc = "Bit 30 - Asynchronous Reflex"]
709    #[inline(always)]
710    pub fn async_(&self) -> ASYNC_R {
711        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
712    }
713}
714impl W {
715    #[doc = "Bits 0:2 - Signal Select"]
716    #[inline(always)]
717    pub fn sigsel(&mut self) -> SIGSEL_W {
718        SIGSEL_W::new(self)
719    }
720    #[doc = "Bits 8:14 - Source Select"]
721    #[inline(always)]
722    pub fn sourcesel(&mut self) -> SOURCESEL_W {
723        SOURCESEL_W::new(self)
724    }
725    #[doc = "Bits 20:21 - Edge Detect Select"]
726    #[inline(always)]
727    pub fn edsel(&mut self) -> EDSEL_W {
728        EDSEL_W::new(self)
729    }
730    #[doc = "Bit 25 - Stretch Channel Output"]
731    #[inline(always)]
732    pub fn stretch(&mut self) -> STRETCH_W {
733        STRETCH_W::new(self)
734    }
735    #[doc = "Bit 26 - Invert Channel"]
736    #[inline(always)]
737    pub fn inv(&mut self) -> INV_W {
738        INV_W::new(self)
739    }
740    #[doc = "Bit 27 - Or Previous"]
741    #[inline(always)]
742    pub fn orprev(&mut self) -> ORPREV_W {
743        ORPREV_W::new(self)
744    }
745    #[doc = "Bit 28 - And Next"]
746    #[inline(always)]
747    pub fn andnext(&mut self) -> ANDNEXT_W {
748        ANDNEXT_W::new(self)
749    }
750    #[doc = "Bit 30 - Asynchronous Reflex"]
751    #[inline(always)]
752    pub fn async_(&mut self) -> ASYNC_W {
753        ASYNC_W::new(self)
754    }
755    #[doc = "Writes raw bits to the register."]
756    #[inline(always)]
757    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
758        self.0.bits(bits);
759        self
760    }
761}
762#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch11_ctrl](index.html) module"]
763pub struct CH11_CTRL_SPEC;
764impl crate::RegisterSpec for CH11_CTRL_SPEC {
765    type Ux = u32;
766}
767#[doc = "`read()` method returns [ch11_ctrl::R](R) reader structure"]
768impl crate::Readable for CH11_CTRL_SPEC {
769    type Reader = R;
770}
771#[doc = "`write(|w| ..)` method takes [ch11_ctrl::W](W) writer structure"]
772impl crate::Writable for CH11_CTRL_SPEC {
773    type Writer = W;
774}
775#[doc = "`reset()` method sets CH11_CTRL to value 0"]
776impl crate::Resettable for CH11_CTRL_SPEC {
777    #[inline(always)]
778    fn reset_value() -> Self::Ux {
779        0
780    }
781}
efm32gg12b110_pac/prs/ch11_ctrl.rs

efm32gg12b110_pac/prs/
ch11_ctrl.rs
