efm32gg12b_pac/efm32gg12b110/timer3/
dtfaultc.rs

1#[doc = "Register `DTFAULTC` writer"]
2pub struct W(crate::W<DTFAULTC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<DTFAULTC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<DTFAULTC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<DTFAULTC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `DTPRS0FC` writer - DTI PRS0 Fault Clear"]
23pub type DTPRS0FC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTFAULTC_SPEC, bool, O>;
24#[doc = "Field `DTPRS1FC` writer - DTI PRS1 Fault Clear"]
25pub type DTPRS1FC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTFAULTC_SPEC, bool, O>;
26#[doc = "Field `DTDBGFC` writer - DTI Debugger Fault Clear"]
27pub type DTDBGFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTFAULTC_SPEC, bool, O>;
28#[doc = "Field `TLOCKUPFC` writer - DTI Lockup Fault Clear"]
29pub type TLOCKUPFC_W<'a, const O: u8> = crate::BitWriter<'a, u32, DTFAULTC_SPEC, bool, O>;
30impl W {
31    #[doc = "Bit 0 - DTI PRS0 Fault Clear"]
32    #[inline(always)]
33    #[must_use]
34    pub fn dtprs0fc(&mut self) -> DTPRS0FC_W<0> {
35        DTPRS0FC_W::new(self)
36    }
37    #[doc = "Bit 1 - DTI PRS1 Fault Clear"]
38    #[inline(always)]
39    #[must_use]
40    pub fn dtprs1fc(&mut self) -> DTPRS1FC_W<1> {
41        DTPRS1FC_W::new(self)
42    }
43    #[doc = "Bit 2 - DTI Debugger Fault Clear"]
44    #[inline(always)]
45    #[must_use]
46    pub fn dtdbgfc(&mut self) -> DTDBGFC_W<2> {
47        DTDBGFC_W::new(self)
48    }
49    #[doc = "Bit 3 - DTI Lockup Fault Clear"]
50    #[inline(always)]
51    #[must_use]
52    pub fn tlockupfc(&mut self) -> TLOCKUPFC_W<3> {
53        TLOCKUPFC_W::new(self)
54    }
55    #[doc = "Writes raw bits to the register."]
56    #[inline(always)]
57    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
58        self.0.bits(bits);
59        self
60    }
61}
62#[doc = "DTI Fault Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtfaultc](index.html) module"]
63pub struct DTFAULTC_SPEC;
64impl crate::RegisterSpec for DTFAULTC_SPEC {
65    type Ux = u32;
66}
67#[doc = "`write(|w| ..)` method takes [dtfaultc::W](W) writer structure"]
68impl crate::Writable for DTFAULTC_SPEC {
69    type Writer = W;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
72}
73#[doc = "`reset()` method sets DTFAULTC to value 0"]
74impl crate::Resettable for DTFAULTC_SPEC {
75    const RESET_VALUE: Self::Ux = 0;
76}
efm32gg12b_pac/efm32gg12b110/timer3/dtfaultc.rs

efm32gg12b_pac/efm32gg12b110/timer3/
dtfaultc.rs
