efm32gg12b_pac/efm32gg12b110/can0/
mir1_cmdmask.rs

1#[doc = "Register `MIR1_CMDMASK` reader"]
2pub struct R(crate::R<MIR1_CMDMASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MIR1_CMDMASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MIR1_CMDMASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MIR1_CMDMASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MIR1_CMDMASK` writer"]
17pub struct W(crate::W<MIR1_CMDMASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MIR1_CMDMASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MIR1_CMDMASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MIR1_CMDMASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DATAB` reader - CC Channel Mode"]
38pub type DATAB_R = crate::BitReader<bool>;
39#[doc = "Field `DATAB` writer - CC Channel Mode"]
40pub type DATAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
41#[doc = "Field `DATAA` reader - Access Data Bytes 0-3"]
42pub type DATAA_R = crate::BitReader<bool>;
43#[doc = "Field `DATAA` writer - Access Data Bytes 0-3"]
44pub type DATAA_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
45#[doc = "Field `TXRQSTNEWDAT` reader - Transmission Request Bit/ New Data Bit"]
46pub type TXRQSTNEWDAT_R = crate::BitReader<bool>;
47#[doc = "Field `TXRQSTNEWDAT` writer - Transmission Request Bit/ New Data Bit"]
48pub type TXRQSTNEWDAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
49#[doc = "Field `CLRINTPND` reader - Clear Interrupt Pending Bit"]
50pub type CLRINTPND_R = crate::BitReader<bool>;
51#[doc = "Field `CLRINTPND` writer - Clear Interrupt Pending Bit"]
52pub type CLRINTPND_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
53#[doc = "Field `CONTROL` reader - Access Control Bits"]
54pub type CONTROL_R = crate::BitReader<bool>;
55#[doc = "Field `CONTROL` writer - Access Control Bits"]
56pub type CONTROL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
57#[doc = "Field `ARBACC` reader - Access Arbitration Bits"]
58pub type ARBACC_R = crate::BitReader<bool>;
59#[doc = "Field `ARBACC` writer - Access Arbitration Bits"]
60pub type ARBACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
61#[doc = "Field `MASKACC` reader - Access Mask Bits"]
62pub type MASKACC_R = crate::BitReader<bool>;
63#[doc = "Field `MASKACC` writer - Access Mask Bits"]
64pub type MASKACC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
65#[doc = "Field `WRRD` reader - Write/Read RAM"]
66pub type WRRD_R = crate::BitReader<bool>;
67#[doc = "Field `WRRD` writer - Write/Read RAM"]
68pub type WRRD_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR1_CMDMASK_SPEC, bool, O>;
69impl R {
70    #[doc = "Bit 0 - CC Channel Mode"]
71    #[inline(always)]
72    pub fn datab(&self) -> DATAB_R {
73        DATAB_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Access Data Bytes 0-3"]
76    #[inline(always)]
77    pub fn dataa(&self) -> DATAA_R {
78        DATAA_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Transmission Request Bit/ New Data Bit"]
81    #[inline(always)]
82    pub fn txrqstnewdat(&self) -> TXRQSTNEWDAT_R {
83        TXRQSTNEWDAT_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - Clear Interrupt Pending Bit"]
86    #[inline(always)]
87    pub fn clrintpnd(&self) -> CLRINTPND_R {
88        CLRINTPND_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - Access Control Bits"]
91    #[inline(always)]
92    pub fn control(&self) -> CONTROL_R {
93        CONTROL_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - Access Arbitration Bits"]
96    #[inline(always)]
97    pub fn arbacc(&self) -> ARBACC_R {
98        ARBACC_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - Access Mask Bits"]
101    #[inline(always)]
102    pub fn maskacc(&self) -> MASKACC_R {
103        MASKACC_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - Write/Read RAM"]
106    #[inline(always)]
107    pub fn wrrd(&self) -> WRRD_R {
108        WRRD_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - CC Channel Mode"]
113    #[inline(always)]
114    #[must_use]
115    pub fn datab(&mut self) -> DATAB_W<0> {
116        DATAB_W::new(self)
117    }
118    #[doc = "Bit 1 - Access Data Bytes 0-3"]
119    #[inline(always)]
120    #[must_use]
121    pub fn dataa(&mut self) -> DATAA_W<1> {
122        DATAA_W::new(self)
123    }
124    #[doc = "Bit 2 - Transmission Request Bit/ New Data Bit"]
125    #[inline(always)]
126    #[must_use]
127    pub fn txrqstnewdat(&mut self) -> TXRQSTNEWDAT_W<2> {
128        TXRQSTNEWDAT_W::new(self)
129    }
130    #[doc = "Bit 3 - Clear Interrupt Pending Bit"]
131    #[inline(always)]
132    #[must_use]
133    pub fn clrintpnd(&mut self) -> CLRINTPND_W<3> {
134        CLRINTPND_W::new(self)
135    }
136    #[doc = "Bit 4 - Access Control Bits"]
137    #[inline(always)]
138    #[must_use]
139    pub fn control(&mut self) -> CONTROL_W<4> {
140        CONTROL_W::new(self)
141    }
142    #[doc = "Bit 5 - Access Arbitration Bits"]
143    #[inline(always)]
144    #[must_use]
145    pub fn arbacc(&mut self) -> ARBACC_W<5> {
146        ARBACC_W::new(self)
147    }
148    #[doc = "Bit 6 - Access Mask Bits"]
149    #[inline(always)]
150    #[must_use]
151    pub fn maskacc(&mut self) -> MASKACC_W<6> {
152        MASKACC_W::new(self)
153    }
154    #[doc = "Bit 7 - Write/Read RAM"]
155    #[inline(always)]
156    #[must_use]
157    pub fn wrrd(&mut self) -> WRRD_W<7> {
158        WRRD_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Interface Command Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mir1_cmdmask](index.html) module"]
168pub struct MIR1_CMDMASK_SPEC;
169impl crate::RegisterSpec for MIR1_CMDMASK_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [mir1_cmdmask::R](R) reader structure"]
173impl crate::Readable for MIR1_CMDMASK_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [mir1_cmdmask::W](W) writer structure"]
177impl crate::Writable for MIR1_CMDMASK_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets MIR1_CMDMASK to value 0"]
183impl crate::Resettable for MIR1_CMDMASK_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}
efm32gg12b_pac/efm32gg12b110/can0/mir1_cmdmask.rs

efm32gg12b_pac/efm32gg12b110/can0/
mir1_cmdmask.rs
