efm32gg12b_pac/efm32gg12b830/usb/
hc1_char.rs

1#[doc = "Register `HC1_CHAR` reader"]
2pub struct R(crate::R<HC1_CHAR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HC1_CHAR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HC1_CHAR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HC1_CHAR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HC1_CHAR` writer"]
17pub struct W(crate::W<HC1_CHAR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HC1_CHAR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HC1_CHAR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HC1_CHAR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPS` reader - Maximum Packet Size"]
38pub type MPS_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `MPS` writer - Maximum Packet Size"]
40pub type MPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC1_CHAR_SPEC, u16, u16, 11, O>;
41#[doc = "Field `EPNUM` reader - Endpoint Number"]
42pub type EPNUM_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `EPNUM` writer - Endpoint Number"]
44pub type EPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC1_CHAR_SPEC, u8, u8, 4, O>;
45#[doc = "Field `EPDIR` reader - Endpoint Direction"]
46pub type EPDIR_R = crate::BitReader<bool>;
47#[doc = "Field `EPDIR` writer - Endpoint Direction"]
48pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC1_CHAR_SPEC, bool, O>;
49#[doc = "Field `LSPDDEV` reader - Low-Speed Device"]
50pub type LSPDDEV_R = crate::BitReader<bool>;
51#[doc = "Field `LSPDDEV` writer - Low-Speed Device"]
52pub type LSPDDEV_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC1_CHAR_SPEC, bool, O>;
53#[doc = "Field `EPTYPE` reader - Endpoint Type"]
54pub type EPTYPE_R = crate::FieldReader<u8, EPTYPE_A>;
55#[doc = "Endpoint Type\n\nValue on reset: 0"]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57#[repr(u8)]
58pub enum EPTYPE_A {
59    #[doc = "0: Control endpoint."]
60    CONTROL = 0,
61    #[doc = "1: Isochronous endpoint."]
62    ISO = 1,
63    #[doc = "2: Bulk endpoint."]
64    BULK = 2,
65    #[doc = "3: Interrupt endpoint."]
66    INT = 3,
67}
68impl From<EPTYPE_A> for u8 {
69    #[inline(always)]
70    fn from(variant: EPTYPE_A) -> Self {
71        variant as _
72    }
73}
74impl EPTYPE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> EPTYPE_A {
78        match self.bits {
79            0 => EPTYPE_A::CONTROL,
80            1 => EPTYPE_A::ISO,
81            2 => EPTYPE_A::BULK,
82            3 => EPTYPE_A::INT,
83            _ => unreachable!(),
84        }
85    }
86    #[doc = "Checks if the value of the field is `CONTROL`"]
87    #[inline(always)]
88    pub fn is_control(&self) -> bool {
89        *self == EPTYPE_A::CONTROL
90    }
91    #[doc = "Checks if the value of the field is `ISO`"]
92    #[inline(always)]
93    pub fn is_iso(&self) -> bool {
94        *self == EPTYPE_A::ISO
95    }
96    #[doc = "Checks if the value of the field is `BULK`"]
97    #[inline(always)]
98    pub fn is_bulk(&self) -> bool {
99        *self == EPTYPE_A::BULK
100    }
101    #[doc = "Checks if the value of the field is `INT`"]
102    #[inline(always)]
103    pub fn is_int(&self) -> bool {
104        *self == EPTYPE_A::INT
105    }
106}
107#[doc = "Field `EPTYPE` writer - Endpoint Type"]
108pub type EPTYPE_W<'a, const O: u8> =
109    crate::FieldWriterSafe<'a, u32, HC1_CHAR_SPEC, u8, EPTYPE_A, 2, O>;
110impl<'a, const O: u8> EPTYPE_W<'a, O> {
111    #[doc = "Control endpoint."]
112    #[inline(always)]
113    pub fn control(self) -> &'a mut W {
114        self.variant(EPTYPE_A::CONTROL)
115    }
116    #[doc = "Isochronous endpoint."]
117    #[inline(always)]
118    pub fn iso(self) -> &'a mut W {
119        self.variant(EPTYPE_A::ISO)
120    }
121    #[doc = "Bulk endpoint."]
122    #[inline(always)]
123    pub fn bulk(self) -> &'a mut W {
124        self.variant(EPTYPE_A::BULK)
125    }
126    #[doc = "Interrupt endpoint."]
127    #[inline(always)]
128    pub fn int(self) -> &'a mut W {
129        self.variant(EPTYPE_A::INT)
130    }
131}
132#[doc = "Field `MC` reader - Multi Count (MC) / Error Count"]
133pub type MC_R = crate::FieldReader<u8, u8>;
134#[doc = "Field `MC` writer - Multi Count (MC) / Error Count"]
135pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC1_CHAR_SPEC, u8, u8, 2, O>;
136#[doc = "Field `DEVADDR` reader - Device Address"]
137pub type DEVADDR_R = crate::FieldReader<u8, u8>;
138#[doc = "Field `DEVADDR` writer - Device Address"]
139pub type DEVADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC1_CHAR_SPEC, u8, u8, 7, O>;
140#[doc = "Field `ODDFRM` reader - Odd Frame"]
141pub type ODDFRM_R = crate::BitReader<bool>;
142#[doc = "Field `ODDFRM` writer - Odd Frame"]
143pub type ODDFRM_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC1_CHAR_SPEC, bool, O>;
144#[doc = "Field `CHDIS` reader - Channel Disable"]
145pub type CHDIS_R = crate::BitReader<bool>;
146#[doc = "Field `CHDIS` writer - Channel Disable"]
147pub type CHDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC1_CHAR_SPEC, bool, O>;
148#[doc = "Field `CHENA` reader - Channel Enable"]
149pub type CHENA_R = crate::BitReader<bool>;
150#[doc = "Field `CHENA` writer - Channel Enable"]
151pub type CHENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC1_CHAR_SPEC, bool, O>;
152impl R {
153    #[doc = "Bits 0:10 - Maximum Packet Size"]
154    #[inline(always)]
155    pub fn mps(&self) -> MPS_R {
156        MPS_R::new((self.bits & 0x07ff) as u16)
157    }
158    #[doc = "Bits 11:14 - Endpoint Number"]
159    #[inline(always)]
160    pub fn epnum(&self) -> EPNUM_R {
161        EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8)
162    }
163    #[doc = "Bit 15 - Endpoint Direction"]
164    #[inline(always)]
165    pub fn epdir(&self) -> EPDIR_R {
166        EPDIR_R::new(((self.bits >> 15) & 1) != 0)
167    }
168    #[doc = "Bit 17 - Low-Speed Device"]
169    #[inline(always)]
170    pub fn lspddev(&self) -> LSPDDEV_R {
171        LSPDDEV_R::new(((self.bits >> 17) & 1) != 0)
172    }
173    #[doc = "Bits 18:19 - Endpoint Type"]
174    #[inline(always)]
175    pub fn eptype(&self) -> EPTYPE_R {
176        EPTYPE_R::new(((self.bits >> 18) & 3) as u8)
177    }
178    #[doc = "Bits 20:21 - Multi Count (MC) / Error Count"]
179    #[inline(always)]
180    pub fn mc(&self) -> MC_R {
181        MC_R::new(((self.bits >> 20) & 3) as u8)
182    }
183    #[doc = "Bits 22:28 - Device Address"]
184    #[inline(always)]
185    pub fn devaddr(&self) -> DEVADDR_R {
186        DEVADDR_R::new(((self.bits >> 22) & 0x7f) as u8)
187    }
188    #[doc = "Bit 29 - Odd Frame"]
189    #[inline(always)]
190    pub fn oddfrm(&self) -> ODDFRM_R {
191        ODDFRM_R::new(((self.bits >> 29) & 1) != 0)
192    }
193    #[doc = "Bit 30 - Channel Disable"]
194    #[inline(always)]
195    pub fn chdis(&self) -> CHDIS_R {
196        CHDIS_R::new(((self.bits >> 30) & 1) != 0)
197    }
198    #[doc = "Bit 31 - Channel Enable"]
199    #[inline(always)]
200    pub fn chena(&self) -> CHENA_R {
201        CHENA_R::new(((self.bits >> 31) & 1) != 0)
202    }
203}
204impl W {
205    #[doc = "Bits 0:10 - Maximum Packet Size"]
206    #[inline(always)]
207    #[must_use]
208    pub fn mps(&mut self) -> MPS_W<0> {
209        MPS_W::new(self)
210    }
211    #[doc = "Bits 11:14 - Endpoint Number"]
212    #[inline(always)]
213    #[must_use]
214    pub fn epnum(&mut self) -> EPNUM_W<11> {
215        EPNUM_W::new(self)
216    }
217    #[doc = "Bit 15 - Endpoint Direction"]
218    #[inline(always)]
219    #[must_use]
220    pub fn epdir(&mut self) -> EPDIR_W<15> {
221        EPDIR_W::new(self)
222    }
223    #[doc = "Bit 17 - Low-Speed Device"]
224    #[inline(always)]
225    #[must_use]
226    pub fn lspddev(&mut self) -> LSPDDEV_W<17> {
227        LSPDDEV_W::new(self)
228    }
229    #[doc = "Bits 18:19 - Endpoint Type"]
230    #[inline(always)]
231    #[must_use]
232    pub fn eptype(&mut self) -> EPTYPE_W<18> {
233        EPTYPE_W::new(self)
234    }
235    #[doc = "Bits 20:21 - Multi Count (MC) / Error Count"]
236    #[inline(always)]
237    #[must_use]
238    pub fn mc(&mut self) -> MC_W<20> {
239        MC_W::new(self)
240    }
241    #[doc = "Bits 22:28 - Device Address"]
242    #[inline(always)]
243    #[must_use]
244    pub fn devaddr(&mut self) -> DEVADDR_W<22> {
245        DEVADDR_W::new(self)
246    }
247    #[doc = "Bit 29 - Odd Frame"]
248    #[inline(always)]
249    #[must_use]
250    pub fn oddfrm(&mut self) -> ODDFRM_W<29> {
251        ODDFRM_W::new(self)
252    }
253    #[doc = "Bit 30 - Channel Disable"]
254    #[inline(always)]
255    #[must_use]
256    pub fn chdis(&mut self) -> CHDIS_W<30> {
257        CHDIS_W::new(self)
258    }
259    #[doc = "Bit 31 - Channel Enable"]
260    #[inline(always)]
261    #[must_use]
262    pub fn chena(&mut self) -> CHENA_W<31> {
263        CHENA_W::new(self)
264    }
265    #[doc = "Writes raw bits to the register."]
266    #[inline(always)]
267    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
268        self.0.bits(bits);
269        self
270    }
271}
272#[doc = "Host Channel x Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_char](index.html) module"]
273pub struct HC1_CHAR_SPEC;
274impl crate::RegisterSpec for HC1_CHAR_SPEC {
275    type Ux = u32;
276}
277#[doc = "`read()` method returns [hc1_char::R](R) reader structure"]
278impl crate::Readable for HC1_CHAR_SPEC {
279    type Reader = R;
280}
281#[doc = "`write(|w| ..)` method takes [hc1_char::W](W) writer structure"]
282impl crate::Writable for HC1_CHAR_SPEC {
283    type Writer = W;
284    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
285    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
286}
287#[doc = "`reset()` method sets HC1_CHAR to value 0"]
288impl crate::Resettable for HC1_CHAR_SPEC {
289    const RESET_VALUE: Self::Ux = 0;
290}
efm32gg12b_pac/efm32gg12b830/usb/hc1_char.rs

efm32gg12b_pac/efm32gg12b830/usb/
hc1_char.rs
