efm32gg12b_pac/efm32gg12b830/pcnt2/
ien.rs

1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `UF` reader - UF Interrupt Enable"]
38pub type UF_R = crate::BitReader<bool>;
39#[doc = "Field `UF` writer - UF Interrupt Enable"]
40pub type UF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
41#[doc = "Field `OF` reader - OF Interrupt Enable"]
42pub type OF_R = crate::BitReader<bool>;
43#[doc = "Field `OF` writer - OF Interrupt Enable"]
44pub type OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
45#[doc = "Field `DIRCNG` reader - DIRCNG Interrupt Enable"]
46pub type DIRCNG_R = crate::BitReader<bool>;
47#[doc = "Field `DIRCNG` writer - DIRCNG Interrupt Enable"]
48pub type DIRCNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
49#[doc = "Field `AUXOF` reader - AUXOF Interrupt Enable"]
50pub type AUXOF_R = crate::BitReader<bool>;
51#[doc = "Field `AUXOF` writer - AUXOF Interrupt Enable"]
52pub type AUXOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
53#[doc = "Field `TCC` reader - TCC Interrupt Enable"]
54pub type TCC_R = crate::BitReader<bool>;
55#[doc = "Field `TCC` writer - TCC Interrupt Enable"]
56pub type TCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
57#[doc = "Field `OQSTERR` reader - OQSTERR Interrupt Enable"]
58pub type OQSTERR_R = crate::BitReader<bool>;
59#[doc = "Field `OQSTERR` writer - OQSTERR Interrupt Enable"]
60pub type OQSTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
61impl R {
62    #[doc = "Bit 0 - UF Interrupt Enable"]
63    #[inline(always)]
64    pub fn uf(&self) -> UF_R {
65        UF_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - OF Interrupt Enable"]
68    #[inline(always)]
69    pub fn of(&self) -> OF_R {
70        OF_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2 - DIRCNG Interrupt Enable"]
73    #[inline(always)]
74    pub fn dircng(&self) -> DIRCNG_R {
75        DIRCNG_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3 - AUXOF Interrupt Enable"]
78    #[inline(always)]
79    pub fn auxof(&self) -> AUXOF_R {
80        AUXOF_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bit 4 - TCC Interrupt Enable"]
83    #[inline(always)]
84    pub fn tcc(&self) -> TCC_R {
85        TCC_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    #[doc = "Bit 5 - OQSTERR Interrupt Enable"]
88    #[inline(always)]
89    pub fn oqsterr(&self) -> OQSTERR_R {
90        OQSTERR_R::new(((self.bits >> 5) & 1) != 0)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - UF Interrupt Enable"]
95    #[inline(always)]
96    #[must_use]
97    pub fn uf(&mut self) -> UF_W<0> {
98        UF_W::new(self)
99    }
100    #[doc = "Bit 1 - OF Interrupt Enable"]
101    #[inline(always)]
102    #[must_use]
103    pub fn of(&mut self) -> OF_W<1> {
104        OF_W::new(self)
105    }
106    #[doc = "Bit 2 - DIRCNG Interrupt Enable"]
107    #[inline(always)]
108    #[must_use]
109    pub fn dircng(&mut self) -> DIRCNG_W<2> {
110        DIRCNG_W::new(self)
111    }
112    #[doc = "Bit 3 - AUXOF Interrupt Enable"]
113    #[inline(always)]
114    #[must_use]
115    pub fn auxof(&mut self) -> AUXOF_W<3> {
116        AUXOF_W::new(self)
117    }
118    #[doc = "Bit 4 - TCC Interrupt Enable"]
119    #[inline(always)]
120    #[must_use]
121    pub fn tcc(&mut self) -> TCC_W<4> {
122        TCC_W::new(self)
123    }
124    #[doc = "Bit 5 - OQSTERR Interrupt Enable"]
125    #[inline(always)]
126    #[must_use]
127    pub fn oqsterr(&mut self) -> OQSTERR_W<5> {
128        OQSTERR_W::new(self)
129    }
130    #[doc = "Writes raw bits to the register."]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.0.bits(bits);
134        self
135    }
136}
137#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
138pub struct IEN_SPEC;
139impl crate::RegisterSpec for IEN_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [ien::R](R) reader structure"]
143impl crate::Readable for IEN_SPEC {
144    type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
147impl crate::Writable for IEN_SPEC {
148    type Writer = W;
149    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets IEN to value 0"]
153impl crate::Resettable for IEN_SPEC {
154    const RESET_VALUE: Self::Ux = 0;
155}
efm32gg12b_pac/efm32gg12b830/pcnt2/ien.rs

efm32gg12b_pac/efm32gg12b830/pcnt2/
ien.rs
