efm32gg12b_pac/efm32gg12b830/can1/
mir0_mask.rs

1#[doc = "Register `MIR0_MASK` reader"]
2pub struct R(crate::R<MIR0_MASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MIR0_MASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MIR0_MASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MIR0_MASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MIR0_MASK` writer"]
17pub struct W(crate::W<MIR0_MASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MIR0_MASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MIR0_MASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MIR0_MASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MASK` reader - Identifier Mask"]
38pub type MASK_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `MASK` writer - Identifier Mask"]
40pub type MASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MIR0_MASK_SPEC, u32, u32, 29, O>;
41#[doc = "Field `MDIR` reader - Mask Message Direction"]
42pub type MDIR_R = crate::BitReader<bool>;
43#[doc = "Field `MDIR` writer - Mask Message Direction"]
44pub type MDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR0_MASK_SPEC, bool, O>;
45#[doc = "Field `MXTD` reader - Mask Extended Identifier"]
46pub type MXTD_R = crate::BitReader<bool>;
47#[doc = "Field `MXTD` writer - Mask Extended Identifier"]
48pub type MXTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIR0_MASK_SPEC, bool, O>;
49impl R {
50    #[doc = "Bits 0:28 - Identifier Mask"]
51    #[inline(always)]
52    pub fn mask(&self) -> MASK_R {
53        MASK_R::new(self.bits & 0x1fff_ffff)
54    }
55    #[doc = "Bit 30 - Mask Message Direction"]
56    #[inline(always)]
57    pub fn mdir(&self) -> MDIR_R {
58        MDIR_R::new(((self.bits >> 30) & 1) != 0)
59    }
60    #[doc = "Bit 31 - Mask Extended Identifier"]
61    #[inline(always)]
62    pub fn mxtd(&self) -> MXTD_R {
63        MXTD_R::new(((self.bits >> 31) & 1) != 0)
64    }
65}
66impl W {
67    #[doc = "Bits 0:28 - Identifier Mask"]
68    #[inline(always)]
69    #[must_use]
70    pub fn mask(&mut self) -> MASK_W<0> {
71        MASK_W::new(self)
72    }
73    #[doc = "Bit 30 - Mask Message Direction"]
74    #[inline(always)]
75    #[must_use]
76    pub fn mdir(&mut self) -> MDIR_W<30> {
77        MDIR_W::new(self)
78    }
79    #[doc = "Bit 31 - Mask Extended Identifier"]
80    #[inline(always)]
81    #[must_use]
82    pub fn mxtd(&mut self) -> MXTD_W<31> {
83        MXTD_W::new(self)
84    }
85    #[doc = "Writes raw bits to the register."]
86    #[inline(always)]
87    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
88        self.0.bits(bits);
89        self
90    }
91}
92#[doc = "Interface Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mir0_mask](index.html) module"]
93pub struct MIR0_MASK_SPEC;
94impl crate::RegisterSpec for MIR0_MASK_SPEC {
95    type Ux = u32;
96}
97#[doc = "`read()` method returns [mir0_mask::R](R) reader structure"]
98impl crate::Readable for MIR0_MASK_SPEC {
99    type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [mir0_mask::W](W) writer structure"]
102impl crate::Writable for MIR0_MASK_SPEC {
103    type Writer = W;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets MIR0_MASK to value 0xdfff_ffff"]
108impl crate::Resettable for MIR0_MASK_SPEC {
109    const RESET_VALUE: Self::Ux = 0xdfff_ffff;
110}
efm32gg12b_pac/efm32gg12b830/can1/mir0_mask.rs

efm32gg12b_pac/efm32gg12b830/can1/
mir0_mask.rs
