efm32gg11b840_pac/msc/
ramctrl.rs

1#[doc = "Register `RAMCTRL` reader"]
2pub struct R(crate::R<RAMCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RAMCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RAMCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RAMCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RAMCTRL` writer"]
17pub struct W(crate::W<RAMCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RAMCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RAMCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RAMCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RAMWSEN` reader - RAM WAIT STATE Enable"]
38pub type RAMWSEN_R = crate::BitReader<bool>;
39#[doc = "Field `RAMWSEN` writer - RAM WAIT STATE Enable"]
40pub type RAMWSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 1>;
41#[doc = "Field `RAMPREFETCHEN` reader - RAM Prefetch Enable"]
42pub type RAMPREFETCHEN_R = crate::BitReader<bool>;
43#[doc = "Field `RAMPREFETCHEN` writer - RAM Prefetch Enable"]
44pub type RAMPREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 2>;
45#[doc = "Field `RAM1WSEN` reader - RAM1 WAIT STATE Enable"]
46pub type RAM1WSEN_R = crate::BitReader<bool>;
47#[doc = "Field `RAM1WSEN` writer - RAM1 WAIT STATE Enable"]
48pub type RAM1WSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 9>;
49#[doc = "Field `RAM1PREFETCHEN` reader - RAM1 Prefetch Enable"]
50pub type RAM1PREFETCHEN_R = crate::BitReader<bool>;
51#[doc = "Field `RAM1PREFETCHEN` writer - RAM1 Prefetch Enable"]
52pub type RAM1PREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 10>;
53#[doc = "Field `RAM2CACHEEN` reader - RAM2 CACHE Enable"]
54pub type RAM2CACHEEN_R = crate::BitReader<bool>;
55#[doc = "Field `RAM2CACHEEN` writer - RAM2 CACHE Enable"]
56pub type RAM2CACHEEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 16>;
57#[doc = "Field `RAM2WSEN` reader - RAM2 WAIT STATE Enable"]
58pub type RAM2WSEN_R = crate::BitReader<bool>;
59#[doc = "Field `RAM2WSEN` writer - RAM2 WAIT STATE Enable"]
60pub type RAM2WSEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 17>;
61#[doc = "Field `RAM2PREFETCHEN` reader - RAM2 Prefetch Enable"]
62pub type RAM2PREFETCHEN_R = crate::BitReader<bool>;
63#[doc = "Field `RAM2PREFETCHEN` writer - RAM2 Prefetch Enable"]
64pub type RAM2PREFETCHEN_W<'a> = crate::BitWriter<'a, u32, RAMCTRL_SPEC, bool, 18>;
65impl R {
66    #[doc = "Bit 1 - RAM WAIT STATE Enable"]
67    #[inline(always)]
68    pub fn ramwsen(&self) -> RAMWSEN_R {
69        RAMWSEN_R::new(((self.bits >> 1) & 1) != 0)
70    }
71    #[doc = "Bit 2 - RAM Prefetch Enable"]
72    #[inline(always)]
73    pub fn ramprefetchen(&self) -> RAMPREFETCHEN_R {
74        RAMPREFETCHEN_R::new(((self.bits >> 2) & 1) != 0)
75    }
76    #[doc = "Bit 9 - RAM1 WAIT STATE Enable"]
77    #[inline(always)]
78    pub fn ram1wsen(&self) -> RAM1WSEN_R {
79        RAM1WSEN_R::new(((self.bits >> 9) & 1) != 0)
80    }
81    #[doc = "Bit 10 - RAM1 Prefetch Enable"]
82    #[inline(always)]
83    pub fn ram1prefetchen(&self) -> RAM1PREFETCHEN_R {
84        RAM1PREFETCHEN_R::new(((self.bits >> 10) & 1) != 0)
85    }
86    #[doc = "Bit 16 - RAM2 CACHE Enable"]
87    #[inline(always)]
88    pub fn ram2cacheen(&self) -> RAM2CACHEEN_R {
89        RAM2CACHEEN_R::new(((self.bits >> 16) & 1) != 0)
90    }
91    #[doc = "Bit 17 - RAM2 WAIT STATE Enable"]
92    #[inline(always)]
93    pub fn ram2wsen(&self) -> RAM2WSEN_R {
94        RAM2WSEN_R::new(((self.bits >> 17) & 1) != 0)
95    }
96    #[doc = "Bit 18 - RAM2 Prefetch Enable"]
97    #[inline(always)]
98    pub fn ram2prefetchen(&self) -> RAM2PREFETCHEN_R {
99        RAM2PREFETCHEN_R::new(((self.bits >> 18) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Bit 1 - RAM WAIT STATE Enable"]
104    #[inline(always)]
105    pub fn ramwsen(&mut self) -> RAMWSEN_W {
106        RAMWSEN_W::new(self)
107    }
108    #[doc = "Bit 2 - RAM Prefetch Enable"]
109    #[inline(always)]
110    pub fn ramprefetchen(&mut self) -> RAMPREFETCHEN_W {
111        RAMPREFETCHEN_W::new(self)
112    }
113    #[doc = "Bit 9 - RAM1 WAIT STATE Enable"]
114    #[inline(always)]
115    pub fn ram1wsen(&mut self) -> RAM1WSEN_W {
116        RAM1WSEN_W::new(self)
117    }
118    #[doc = "Bit 10 - RAM1 Prefetch Enable"]
119    #[inline(always)]
120    pub fn ram1prefetchen(&mut self) -> RAM1PREFETCHEN_W {
121        RAM1PREFETCHEN_W::new(self)
122    }
123    #[doc = "Bit 16 - RAM2 CACHE Enable"]
124    #[inline(always)]
125    pub fn ram2cacheen(&mut self) -> RAM2CACHEEN_W {
126        RAM2CACHEEN_W::new(self)
127    }
128    #[doc = "Bit 17 - RAM2 WAIT STATE Enable"]
129    #[inline(always)]
130    pub fn ram2wsen(&mut self) -> RAM2WSEN_W {
131        RAM2WSEN_W::new(self)
132    }
133    #[doc = "Bit 18 - RAM2 Prefetch Enable"]
134    #[inline(always)]
135    pub fn ram2prefetchen(&mut self) -> RAM2PREFETCHEN_W {
136        RAM2PREFETCHEN_W::new(self)
137    }
138    #[doc = "Writes raw bits to the register."]
139    #[inline(always)]
140    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
141        self.0.bits(bits);
142        self
143    }
144}
145#[doc = "RAM Control Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ramctrl](index.html) module"]
146pub struct RAMCTRL_SPEC;
147impl crate::RegisterSpec for RAMCTRL_SPEC {
148    type Ux = u32;
149}
150#[doc = "`read()` method returns [ramctrl::R](R) reader structure"]
151impl crate::Readable for RAMCTRL_SPEC {
152    type Reader = R;
153}
154#[doc = "`write(|w| ..)` method takes [ramctrl::W](W) writer structure"]
155impl crate::Writable for RAMCTRL_SPEC {
156    type Writer = W;
157}
158#[doc = "`reset()` method sets RAMCTRL to value 0"]
159impl crate::Resettable for RAMCTRL_SPEC {
160    #[inline(always)]
161    fn reset_value() -> Self::Ux {
162        0
163    }
164}
efm32gg11b840_pac/msc/ramctrl.rs

efm32gg11b840_pac/msc/
ramctrl.rs
