efm32gg11b840_pac/usb/
diep1_ctl.rs

1#[doc = "Register `DIEP1_CTL` reader"]
2pub struct R(crate::R<DIEP1_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEP1_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEP1_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEP1_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEP1_CTL` writer"]
17pub struct W(crate::W<DIEP1_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEP1_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEP1_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEP1_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPS` reader - Maximum Packet Size"]
38pub type MPS_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `MPS` writer - Maximum Packet Size"]
40pub type MPS_W<'a> = crate::FieldWriter<'a, u32, DIEP1_CTL_SPEC, u16, u16, 11, 0>;
41#[doc = "Field `USBACTEP` reader - USB Active Endpoint"]
42pub type USBACTEP_R = crate::BitReader<bool>;
43#[doc = "Field `USBACTEP` writer - USB Active Endpoint"]
44pub type USBACTEP_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 15>;
45#[doc = "Field `DPIDEOF` reader - Endpoint Data PID / Even or Odd Frame"]
46pub type DPIDEOF_R = crate::BitReader<bool>;
47#[doc = "Field `NAKSTS` reader - NAK Status"]
48pub type NAKSTS_R = crate::BitReader<bool>;
49#[doc = "Endpoint Type\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum EPTYPE_A {
53    #[doc = "0: Control Endpoint."]
54    CONTROL = 0,
55    #[doc = "1: Isochronous Endpoint."]
56    ISO = 1,
57    #[doc = "2: Bulk Endpoint."]
58    BULK = 2,
59    #[doc = "3: Interrupt Endpoint."]
60    INT = 3,
61}
62impl From<EPTYPE_A> for u8 {
63    #[inline(always)]
64    fn from(variant: EPTYPE_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `EPTYPE` reader - Endpoint Type"]
69pub type EPTYPE_R = crate::FieldReader<u8, EPTYPE_A>;
70impl EPTYPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> EPTYPE_A {
74        match self.bits {
75            0 => EPTYPE_A::CONTROL,
76            1 => EPTYPE_A::ISO,
77            2 => EPTYPE_A::BULK,
78            3 => EPTYPE_A::INT,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `CONTROL`"]
83    #[inline(always)]
84    pub fn is_control(&self) -> bool {
85        *self == EPTYPE_A::CONTROL
86    }
87    #[doc = "Checks if the value of the field is `ISO`"]
88    #[inline(always)]
89    pub fn is_iso(&self) -> bool {
90        *self == EPTYPE_A::ISO
91    }
92    #[doc = "Checks if the value of the field is `BULK`"]
93    #[inline(always)]
94    pub fn is_bulk(&self) -> bool {
95        *self == EPTYPE_A::BULK
96    }
97    #[doc = "Checks if the value of the field is `INT`"]
98    #[inline(always)]
99    pub fn is_int(&self) -> bool {
100        *self == EPTYPE_A::INT
101    }
102}
103#[doc = "Field `EPTYPE` writer - Endpoint Type"]
104pub type EPTYPE_W<'a> = crate::FieldWriterSafe<'a, u32, DIEP1_CTL_SPEC, u8, EPTYPE_A, 2, 18>;
105impl<'a> EPTYPE_W<'a> {
106    #[doc = "Control Endpoint."]
107    #[inline(always)]
108    pub fn control(self) -> &'a mut W {
109        self.variant(EPTYPE_A::CONTROL)
110    }
111    #[doc = "Isochronous Endpoint."]
112    #[inline(always)]
113    pub fn iso(self) -> &'a mut W {
114        self.variant(EPTYPE_A::ISO)
115    }
116    #[doc = "Bulk Endpoint."]
117    #[inline(always)]
118    pub fn bulk(self) -> &'a mut W {
119        self.variant(EPTYPE_A::BULK)
120    }
121    #[doc = "Interrupt Endpoint."]
122    #[inline(always)]
123    pub fn int(self) -> &'a mut W {
124        self.variant(EPTYPE_A::INT)
125    }
126}
127#[doc = "Field `STALL` reader - Handshake"]
128pub type STALL_R = crate::BitReader<bool>;
129#[doc = "Field `STALL` writer - Handshake"]
130pub type STALL_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 21>;
131#[doc = "Field `TXFNUM` reader - TxFIFO Number"]
132pub type TXFNUM_R = crate::FieldReader<u8, u8>;
133#[doc = "Field `TXFNUM` writer - TxFIFO Number"]
134pub type TXFNUM_W<'a> = crate::FieldWriter<'a, u32, DIEP1_CTL_SPEC, u8, u8, 4, 22>;
135#[doc = "Field `CNAK` writer - Clear NAK"]
136pub type CNAK_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 26>;
137#[doc = "Field `SNAK` writer - Set NAK"]
138pub type SNAK_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 27>;
139#[doc = "Field `SETD0PIDEF` writer - Set DATA0 PID / Even Frame"]
140pub type SETD0PIDEF_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 28>;
141#[doc = "Field `SETD1PIDOF` writer - Set DATA1 PID / Odd Frame"]
142pub type SETD1PIDOF_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 29>;
143#[doc = "Field `EPDIS` reader - Endpoint Disable"]
144pub type EPDIS_R = crate::BitReader<bool>;
145#[doc = "Field `EPDIS` writer - Endpoint Disable"]
146pub type EPDIS_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 30>;
147#[doc = "Field `EPENA` reader - Endpoint Enable"]
148pub type EPENA_R = crate::BitReader<bool>;
149#[doc = "Field `EPENA` writer - Endpoint Enable"]
150pub type EPENA_W<'a> = crate::BitWriter<'a, u32, DIEP1_CTL_SPEC, bool, 31>;
151impl R {
152    #[doc = "Bits 0:10 - Maximum Packet Size"]
153    #[inline(always)]
154    pub fn mps(&self) -> MPS_R {
155        MPS_R::new((self.bits & 0x07ff) as u16)
156    }
157    #[doc = "Bit 15 - USB Active Endpoint"]
158    #[inline(always)]
159    pub fn usbactep(&self) -> USBACTEP_R {
160        USBACTEP_R::new(((self.bits >> 15) & 1) != 0)
161    }
162    #[doc = "Bit 16 - Endpoint Data PID / Even or Odd Frame"]
163    #[inline(always)]
164    pub fn dpideof(&self) -> DPIDEOF_R {
165        DPIDEOF_R::new(((self.bits >> 16) & 1) != 0)
166    }
167    #[doc = "Bit 17 - NAK Status"]
168    #[inline(always)]
169    pub fn naksts(&self) -> NAKSTS_R {
170        NAKSTS_R::new(((self.bits >> 17) & 1) != 0)
171    }
172    #[doc = "Bits 18:19 - Endpoint Type"]
173    #[inline(always)]
174    pub fn eptype(&self) -> EPTYPE_R {
175        EPTYPE_R::new(((self.bits >> 18) & 3) as u8)
176    }
177    #[doc = "Bit 21 - Handshake"]
178    #[inline(always)]
179    pub fn stall(&self) -> STALL_R {
180        STALL_R::new(((self.bits >> 21) & 1) != 0)
181    }
182    #[doc = "Bits 22:25 - TxFIFO Number"]
183    #[inline(always)]
184    pub fn txfnum(&self) -> TXFNUM_R {
185        TXFNUM_R::new(((self.bits >> 22) & 0x0f) as u8)
186    }
187    #[doc = "Bit 30 - Endpoint Disable"]
188    #[inline(always)]
189    pub fn epdis(&self) -> EPDIS_R {
190        EPDIS_R::new(((self.bits >> 30) & 1) != 0)
191    }
192    #[doc = "Bit 31 - Endpoint Enable"]
193    #[inline(always)]
194    pub fn epena(&self) -> EPENA_R {
195        EPENA_R::new(((self.bits >> 31) & 1) != 0)
196    }
197}
198impl W {
199    #[doc = "Bits 0:10 - Maximum Packet Size"]
200    #[inline(always)]
201    pub fn mps(&mut self) -> MPS_W {
202        MPS_W::new(self)
203    }
204    #[doc = "Bit 15 - USB Active Endpoint"]
205    #[inline(always)]
206    pub fn usbactep(&mut self) -> USBACTEP_W {
207        USBACTEP_W::new(self)
208    }
209    #[doc = "Bits 18:19 - Endpoint Type"]
210    #[inline(always)]
211    pub fn eptype(&mut self) -> EPTYPE_W {
212        EPTYPE_W::new(self)
213    }
214    #[doc = "Bit 21 - Handshake"]
215    #[inline(always)]
216    pub fn stall(&mut self) -> STALL_W {
217        STALL_W::new(self)
218    }
219    #[doc = "Bits 22:25 - TxFIFO Number"]
220    #[inline(always)]
221    pub fn txfnum(&mut self) -> TXFNUM_W {
222        TXFNUM_W::new(self)
223    }
224    #[doc = "Bit 26 - Clear NAK"]
225    #[inline(always)]
226    pub fn cnak(&mut self) -> CNAK_W {
227        CNAK_W::new(self)
228    }
229    #[doc = "Bit 27 - Set NAK"]
230    #[inline(always)]
231    pub fn snak(&mut self) -> SNAK_W {
232        SNAK_W::new(self)
233    }
234    #[doc = "Bit 28 - Set DATA0 PID / Even Frame"]
235    #[inline(always)]
236    pub fn setd0pidef(&mut self) -> SETD0PIDEF_W {
237        SETD0PIDEF_W::new(self)
238    }
239    #[doc = "Bit 29 - Set DATA1 PID / Odd Frame"]
240    #[inline(always)]
241    pub fn setd1pidof(&mut self) -> SETD1PIDOF_W {
242        SETD1PIDOF_W::new(self)
243    }
244    #[doc = "Bit 30 - Endpoint Disable"]
245    #[inline(always)]
246    pub fn epdis(&mut self) -> EPDIS_W {
247        EPDIS_W::new(self)
248    }
249    #[doc = "Bit 31 - Endpoint Enable"]
250    #[inline(always)]
251    pub fn epena(&mut self) -> EPENA_W {
252        EPENA_W::new(self)
253    }
254    #[doc = "Writes raw bits to the register."]
255    #[inline(always)]
256    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
257        self.0.bits(bits);
258        self
259    }
260}
261#[doc = "Device Control IN Endpoint x+1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_ctl](index.html) module"]
262pub struct DIEP1_CTL_SPEC;
263impl crate::RegisterSpec for DIEP1_CTL_SPEC {
264    type Ux = u32;
265}
266#[doc = "`read()` method returns [diep1_ctl::R](R) reader structure"]
267impl crate::Readable for DIEP1_CTL_SPEC {
268    type Reader = R;
269}
270#[doc = "`write(|w| ..)` method takes [diep1_ctl::W](W) writer structure"]
271impl crate::Writable for DIEP1_CTL_SPEC {
272    type Writer = W;
273}
274#[doc = "`reset()` method sets DIEP1_CTL to value 0"]
275impl crate::Resettable for DIEP1_CTL_SPEC {
276    #[inline(always)]
277    fn reset_value() -> Self::Ux {
278        0
279    }
280}
efm32gg11b840_pac/usb/diep1_ctl.rs

efm32gg11b840_pac/usb/
diep1_ctl.rs
