1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - System Control Register"]
5 pub ctrl: CTRL,
6 #[doc = "0x04 - System Status Register"]
7 pub status: STATUS,
8 #[doc = "0x08 - Interrupt Flag Register"]
9 pub if_: IF,
10 #[doc = "0x0c - Interrupt Flag Set Register"]
11 pub ifs: IFS,
12 #[doc = "0x10 - Interrupt Flag Clear Register"]
13 pub ifc: IFC,
14 #[doc = "0x14 - Interrupt Enable Register"]
15 pub ien: IEN,
16 #[doc = "0x18 - I/O Routing Register"]
17 pub route: ROUTE,
18 _reserved7: [u8; 16usize],
19 #[doc = "0x2c - Charger Detect Configuration Register"]
20 pub cdconf: CDCONF,
21 #[doc = "0x30 - Command Register"]
22 pub cmd: CMD,
23 #[doc = "0x34 - Data TRIM 1 Values for USB DP and DM"]
24 pub dattrim1: DATTRIM1,
25 _reserved10: [u8; 4usize],
26 #[doc = "0x3c - USB LEM Control Register"]
27 pub lemctrl: LEMCTRL,
28 _reserved11: [u8; 909248usize],
29 #[doc = "0xde000 - OTG Control and Status Register"]
30 pub gotgctl: GOTGCTL,
31 #[doc = "0xde004 - OTG Interrupt Register"]
32 pub gotgint: GOTGINT,
33 #[doc = "0xde008 - AHB Configuration Register"]
34 pub gahbcfg: GAHBCFG,
35 #[doc = "0xde00c - USB Configuration Register"]
36 pub gusbcfg: GUSBCFG,
37 #[doc = "0xde010 - Reset Register"]
38 pub grstctl: GRSTCTL,
39 #[doc = "0xde014 - Interrupt Register"]
40 pub gintsts: GINTSTS,
41 #[doc = "0xde018 - Interrupt Mask Register"]
42 pub gintmsk: GINTMSK,
43 #[doc = "0xde01c - Receive Status Debug Read Register"]
44 pub grxstsr: GRXSTSR,
45 #[doc = "0xde020 - Receive Status Read /Pop Register"]
46 pub grxstsp: GRXSTSP,
47 #[doc = "0xde024 - Receive FIFO Size Register"]
48 pub grxfsiz: GRXFSIZ,
49 #[doc = "0xde028 - Non-periodic Transmit FIFO Size Register"]
50 pub gnptxfsiz: GNPTXFSIZ,
51 #[doc = "0xde02c - Non-periodic Transmit FIFO/Queue Status Register"]
52 pub gnptxsts: GNPTXSTS,
53 _reserved23: [u8; 16usize],
54 #[doc = "0xde040 - Synopsys ID Register"]
55 pub gsnpsid: GSNPSID,
56 _reserved24: [u8; 24usize],
57 #[doc = "0xde05c - Global DFIFO Configuration Register"]
58 pub gdfifocfg: GDFIFOCFG,
59 _reserved25: [u8; 160usize],
60 #[doc = "0xde100 - Host Periodic Transmit FIFO Size Register"]
61 pub hptxfsiz: HPTXFSIZ,
62 #[doc = "0xde104 - Device IN Endpoint Transmit FIFO Size Register 1"]
63 pub dieptxf1: DIEPTXF1,
64 #[doc = "0xde108 - Device IN Endpoint Transmit FIFO Size Register 2"]
65 pub dieptxf2: DIEPTXF2,
66 #[doc = "0xde10c - Device IN Endpoint Transmit FIFO Size Register 3"]
67 pub dieptxf3: DIEPTXF3,
68 #[doc = "0xde110 - Device IN Endpoint Transmit FIFO Size Register 4"]
69 pub dieptxf4: DIEPTXF4,
70 #[doc = "0xde114 - Device IN Endpoint Transmit FIFO Size Register 5"]
71 pub dieptxf5: DIEPTXF5,
72 #[doc = "0xde118 - Device IN Endpoint Transmit FIFO Size Register 6"]
73 pub dieptxf6: DIEPTXF6,
74 _reserved32: [u8; 740usize],
75 #[doc = "0xde400 - Host Configuration Register"]
76 pub hcfg: HCFG,
77 #[doc = "0xde404 - Host Frame Interval Register"]
78 pub hfir: HFIR,
79 #[doc = "0xde408 - Host Frame Number/Frame Time Remaining Register"]
80 pub hfnum: HFNUM,
81 _reserved35: [u8; 4usize],
82 #[doc = "0xde410 - Host Periodic Transmit FIFO/Queue Status Register"]
83 pub hptxsts: HPTXSTS,
84 #[doc = "0xde414 - Host All Channels Interrupt Register"]
85 pub haint: HAINT,
86 #[doc = "0xde418 - Host All Channels Interrupt Mask Register"]
87 pub haintmsk: HAINTMSK,
88 _reserved38: [u8; 36usize],
89 #[doc = "0xde440 - Host Port Control and Status Register"]
90 pub hprt: HPRT,
91 _reserved39: [u8; 188usize],
92 #[doc = "0xde500 - Host Channel 0 Characteristics Register"]
93 pub hc0_char: HC0_CHAR,
94 #[doc = "0xde504 - Host Channel 0 Split Control Register"]
95 pub hc0_splt: HC0_SPLT,
96 #[doc = "0xde508 - Host Channel 0 Interrupt Register"]
97 pub hc0_int: HC0_INT,
98 #[doc = "0xde50c - Host Channel 0 Interrupt Mask Register"]
99 pub hc0_intmsk: HC0_INTMSK,
100 #[doc = "0xde510 - Host Channel 0 Transfer Size Register"]
101 pub hc0_tsiz: HC0_TSIZ,
102 #[doc = "0xde514 - Host Channel 0 DMA Address Register"]
103 pub hc0_dmaaddr: HC0_DMAADDR,
104 _reserved45: [u8; 8usize],
105 #[doc = "0xde520 - Host Channel 0 Characteristics Register"]
106 pub hc1_char: HC1_CHAR,
107 #[doc = "0xde524 - Host Channel 0 Split Control Register"]
108 pub hc1_splt: HC1_SPLT,
109 #[doc = "0xde528 - Host Channel 0 Interrupt Register"]
110 pub hc1_int: HC1_INT,
111 #[doc = "0xde52c - Host Channel 0 Interrupt Mask Register"]
112 pub hc1_intmsk: HC1_INTMSK,
113 #[doc = "0xde530 - Host Channel 0 Transfer Size Register"]
114 pub hc1_tsiz: HC1_TSIZ,
115 #[doc = "0xde534 - Host Channel 0 DMA Address Register"]
116 pub hc1_dmaaddr: HC1_DMAADDR,
117 _reserved51: [u8; 8usize],
118 #[doc = "0xde540 - Host Channel 0 Characteristics Register"]
119 pub hc2_char: HC2_CHAR,
120 #[doc = "0xde544 - Host Channel 0 Split Control Register"]
121 pub hc2_splt: HC2_SPLT,
122 #[doc = "0xde548 - Host Channel 0 Interrupt Register"]
123 pub hc2_int: HC2_INT,
124 #[doc = "0xde54c - Host Channel 0 Interrupt Mask Register"]
125 pub hc2_intmsk: HC2_INTMSK,
126 #[doc = "0xde550 - Host Channel 0 Transfer Size Register"]
127 pub hc2_tsiz: HC2_TSIZ,
128 #[doc = "0xde554 - Host Channel 0 DMA Address Register"]
129 pub hc2_dmaaddr: HC2_DMAADDR,
130 _reserved57: [u8; 8usize],
131 #[doc = "0xde560 - Host Channel 0 Characteristics Register"]
132 pub hc3_char: HC3_CHAR,
133 #[doc = "0xde564 - Host Channel 0 Split Control Register"]
134 pub hc3_splt: HC3_SPLT,
135 #[doc = "0xde568 - Host Channel 0 Interrupt Register"]
136 pub hc3_int: HC3_INT,
137 #[doc = "0xde56c - Host Channel 0 Interrupt Mask Register"]
138 pub hc3_intmsk: HC3_INTMSK,
139 #[doc = "0xde570 - Host Channel 0 Transfer Size Register"]
140 pub hc3_tsiz: HC3_TSIZ,
141 #[doc = "0xde574 - Host Channel 0 DMA Address Register"]
142 pub hc3_dmaaddr: HC3_DMAADDR,
143 _reserved63: [u8; 8usize],
144 #[doc = "0xde580 - Host Channel 0 Characteristics Register"]
145 pub hc4_char: HC4_CHAR,
146 #[doc = "0xde584 - Host Channel 0 Split Control Register"]
147 pub hc4_splt: HC4_SPLT,
148 #[doc = "0xde588 - Host Channel 0 Interrupt Register"]
149 pub hc4_int: HC4_INT,
150 #[doc = "0xde58c - Host Channel 0 Interrupt Mask Register"]
151 pub hc4_intmsk: HC4_INTMSK,
152 #[doc = "0xde590 - Host Channel 0 Transfer Size Register"]
153 pub hc4_tsiz: HC4_TSIZ,
154 #[doc = "0xde594 - Host Channel 0 DMA Address Register"]
155 pub hc4_dmaaddr: HC4_DMAADDR,
156 _reserved69: [u8; 8usize],
157 #[doc = "0xde5a0 - Host Channel 0 Characteristics Register"]
158 pub hc5_char: HC5_CHAR,
159 #[doc = "0xde5a4 - Host Channel 0 Split Control Register"]
160 pub hc5_splt: HC5_SPLT,
161 #[doc = "0xde5a8 - Host Channel 0 Interrupt Register"]
162 pub hc5_int: HC5_INT,
163 #[doc = "0xde5ac - Host Channel 0 Interrupt Mask Register"]
164 pub hc5_intmsk: HC5_INTMSK,
165 #[doc = "0xde5b0 - Host Channel 0 Transfer Size Register"]
166 pub hc5_tsiz: HC5_TSIZ,
167 #[doc = "0xde5b4 - Host Channel 0 DMA Address Register"]
168 pub hc5_dmaaddr: HC5_DMAADDR,
169 _reserved75: [u8; 8usize],
170 #[doc = "0xde5c0 - Host Channel 0 Characteristics Register"]
171 pub hc6_char: HC6_CHAR,
172 #[doc = "0xde5c4 - Host Channel 0 Split Control Register"]
173 pub hc6_splt: HC6_SPLT,
174 #[doc = "0xde5c8 - Host Channel 0 Interrupt Register"]
175 pub hc6_int: HC6_INT,
176 #[doc = "0xde5cc - Host Channel 0 Interrupt Mask Register"]
177 pub hc6_intmsk: HC6_INTMSK,
178 #[doc = "0xde5d0 - Host Channel 0 Transfer Size Register"]
179 pub hc6_tsiz: HC6_TSIZ,
180 #[doc = "0xde5d4 - Host Channel 0 DMA Address Register"]
181 pub hc6_dmaaddr: HC6_DMAADDR,
182 _reserved81: [u8; 8usize],
183 #[doc = "0xde5e0 - Host Channel 0 Characteristics Register"]
184 pub hc7_char: HC7_CHAR,
185 #[doc = "0xde5e4 - Host Channel 0 Split Control Register"]
186 pub hc7_splt: HC7_SPLT,
187 #[doc = "0xde5e8 - Host Channel 0 Interrupt Register"]
188 pub hc7_int: HC7_INT,
189 #[doc = "0xde5ec - Host Channel 0 Interrupt Mask Register"]
190 pub hc7_intmsk: HC7_INTMSK,
191 #[doc = "0xde5f0 - Host Channel 0 Transfer Size Register"]
192 pub hc7_tsiz: HC7_TSIZ,
193 #[doc = "0xde5f4 - Host Channel 0 DMA Address Register"]
194 pub hc7_dmaaddr: HC7_DMAADDR,
195 _reserved87: [u8; 8usize],
196 #[doc = "0xde600 - Host Channel 0 Characteristics Register"]
197 pub hc8_char: HC8_CHAR,
198 #[doc = "0xde604 - Host Channel 0 Split Control Register"]
199 pub hc8_splt: HC8_SPLT,
200 #[doc = "0xde608 - Host Channel 0 Interrupt Register"]
201 pub hc8_int: HC8_INT,
202 #[doc = "0xde60c - Host Channel 0 Interrupt Mask Register"]
203 pub hc8_intmsk: HC8_INTMSK,
204 #[doc = "0xde610 - Host Channel 0 Transfer Size Register"]
205 pub hc8_tsiz: HC8_TSIZ,
206 #[doc = "0xde614 - Host Channel 0 DMA Address Register"]
207 pub hc8_dmaaddr: HC8_DMAADDR,
208 _reserved93: [u8; 8usize],
209 #[doc = "0xde620 - Host Channel 0 Characteristics Register"]
210 pub hc9_char: HC9_CHAR,
211 #[doc = "0xde624 - Host Channel 0 Split Control Register"]
212 pub hc9_splt: HC9_SPLT,
213 #[doc = "0xde628 - Host Channel 0 Interrupt Register"]
214 pub hc9_int: HC9_INT,
215 #[doc = "0xde62c - Host Channel 0 Interrupt Mask Register"]
216 pub hc9_intmsk: HC9_INTMSK,
217 #[doc = "0xde630 - Host Channel 0 Transfer Size Register"]
218 pub hc9_tsiz: HC9_TSIZ,
219 #[doc = "0xde634 - Host Channel 0 DMA Address Register"]
220 pub hc9_dmaaddr: HC9_DMAADDR,
221 _reserved99: [u8; 8usize],
222 #[doc = "0xde640 - Host Channel 0 Characteristics Register"]
223 pub hc10_char: HC10_CHAR,
224 #[doc = "0xde644 - Host Channel 0 Split Control Register"]
225 pub hc10_splt: HC10_SPLT,
226 #[doc = "0xde648 - Host Channel 0 Interrupt Register"]
227 pub hc10_int: HC10_INT,
228 #[doc = "0xde64c - Host Channel 0 Interrupt Mask Register"]
229 pub hc10_intmsk: HC10_INTMSK,
230 #[doc = "0xde650 - Host Channel 0 Transfer Size Register"]
231 pub hc10_tsiz: HC10_TSIZ,
232 #[doc = "0xde654 - Host Channel 0 DMA Address Register"]
233 pub hc10_dmaaddr: HC10_DMAADDR,
234 _reserved105: [u8; 8usize],
235 #[doc = "0xde660 - Host Channel 0 Characteristics Register"]
236 pub hc11_char: HC11_CHAR,
237 #[doc = "0xde664 - Host Channel 0 Split Control Register"]
238 pub hc11_splt: HC11_SPLT,
239 #[doc = "0xde668 - Host Channel 0 Interrupt Register"]
240 pub hc11_int: HC11_INT,
241 #[doc = "0xde66c - Host Channel 0 Interrupt Mask Register"]
242 pub hc11_intmsk: HC11_INTMSK,
243 #[doc = "0xde670 - Host Channel 0 Transfer Size Register"]
244 pub hc11_tsiz: HC11_TSIZ,
245 #[doc = "0xde674 - Host Channel 0 DMA Address Register"]
246 pub hc11_dmaaddr: HC11_DMAADDR,
247 _reserved111: [u8; 8usize],
248 #[doc = "0xde680 - Host Channel 0 Characteristics Register"]
249 pub hc12_char: HC12_CHAR,
250 #[doc = "0xde684 - Host Channel 0 Split Control Register"]
251 pub hc12_splt: HC12_SPLT,
252 #[doc = "0xde688 - Host Channel 0 Interrupt Register"]
253 pub hc12_int: HC12_INT,
254 #[doc = "0xde68c - Host Channel 0 Interrupt Mask Register"]
255 pub hc12_intmsk: HC12_INTMSK,
256 #[doc = "0xde690 - Host Channel 0 Transfer Size Register"]
257 pub hc12_tsiz: HC12_TSIZ,
258 #[doc = "0xde694 - Host Channel 0 DMA Address Register"]
259 pub hc12_dmaaddr: HC12_DMAADDR,
260 _reserved117: [u8; 8usize],
261 #[doc = "0xde6a0 - Host Channel 0 Characteristics Register"]
262 pub hc13_char: HC13_CHAR,
263 #[doc = "0xde6a4 - Host Channel 0 Split Control Register"]
264 pub hc13_splt: HC13_SPLT,
265 #[doc = "0xde6a8 - Host Channel 0 Interrupt Register"]
266 pub hc13_int: HC13_INT,
267 #[doc = "0xde6ac - Host Channel 0 Interrupt Mask Register"]
268 pub hc13_intmsk: HC13_INTMSK,
269 #[doc = "0xde6b0 - Host Channel 0 Transfer Size Register"]
270 pub hc13_tsiz: HC13_TSIZ,
271 #[doc = "0xde6b4 - Host Channel 0 DMA Address Register"]
272 pub hc13_dmaaddr: HC13_DMAADDR,
273 _reserved123: [u8; 328usize],
274 #[doc = "0xde800 - Device Configuration Register"]
275 pub dcfg: DCFG,
276 #[doc = "0xde804 - Device Control Register"]
277 pub dctl: DCTL,
278 #[doc = "0xde808 - Device Status Register"]
279 pub dsts: DSTS,
280 _reserved126: [u8; 4usize],
281 #[doc = "0xde810 - Device IN Endpoint Common Interrupt Mask Register"]
282 pub diepmsk: DIEPMSK,
283 #[doc = "0xde814 - Device OUT Endpoint Common Interrupt Mask Register"]
284 pub doepmsk: DOEPMSK,
285 #[doc = "0xde818 - Device All Endpoints Interrupt Register"]
286 pub daint: DAINT,
287 #[doc = "0xde81c - Device All Endpoints Interrupt Mask Register"]
288 pub daintmsk: DAINTMSK,
289 _reserved130: [u8; 8usize],
290 #[doc = "0xde828 - Device VBUS Discharge Time Register"]
291 pub dvbusdis: DVBUSDIS,
292 #[doc = "0xde82c - Device VBUS Pulsing Time Register"]
293 pub dvbuspulse: DVBUSPULSE,
294 #[doc = "0xde830 - Device Threshold Control Register"]
295 pub dthrctl: DTHRCTL,
296 #[doc = "0xde834 - Device IN Endpoint FIFO Empty Interrupt Mask Register"]
297 pub diepempmsk: DIEPEMPMSK,
298 _reserved134: [u8; 200usize],
299 #[doc = "0xde900 - Device Control IN Endpoint 0 Control Register"]
300 pub diep0ctl: DIEP0CTL,
301 _reserved135: [u8; 4usize],
302 #[doc = "0xde908 - Device IN Endpoint 0 Interrupt Register"]
303 pub diep0int: DIEP0INT,
304 _reserved136: [u8; 4usize],
305 #[doc = "0xde910 - Device IN Endpoint 0 Transfer Size Register"]
306 pub diep0tsiz: DIEP0TSIZ,
307 #[doc = "0xde914 - Device IN Endpoint 0 DMA Address Register"]
308 pub diep0dmaaddr: DIEP0DMAADDR,
309 #[doc = "0xde918 - Device IN Endpoint Transmit FIFO Status Register 0"]
310 pub diep0txfsts: DIEP0TXFSTS,
311 _reserved139: [u8; 4usize],
312 #[doc = "0xde920 - Device Control IN Endpoint 1 Control Register"]
313 pub diep0_ctl: DIEP0_CTL,
314 _reserved140: [u8; 4usize],
315 #[doc = "0xde928 - Device IN Endpoint 1 Interrupt Register"]
316 pub diep0_int: DIEP0_INT,
317 _reserved141: [u8; 4usize],
318 #[doc = "0xde930 - Device IN Endpoint 1 Transfer Size Register"]
319 pub diep0_tsiz: DIEP0_TSIZ,
320 #[doc = "0xde934 - Device IN Endpoint 1 DMA Address Register"]
321 pub diep0_dmaaddr: DIEP0_DMAADDR,
322 #[doc = "0xde938 - Device IN Endpoint Transmit FIFO Status Register 1"]
323 pub diep0_dtxfsts: DIEP0_DTXFSTS,
324 _reserved144: [u8; 4usize],
325 #[doc = "0xde940 - Device Control IN Endpoint 1 Control Register"]
326 pub diep1_ctl: DIEP1_CTL,
327 _reserved145: [u8; 4usize],
328 #[doc = "0xde948 - Device IN Endpoint 1 Interrupt Register"]
329 pub diep1_int: DIEP1_INT,
330 _reserved146: [u8; 4usize],
331 #[doc = "0xde950 - Device IN Endpoint 1 Transfer Size Register"]
332 pub diep1_tsiz: DIEP1_TSIZ,
333 #[doc = "0xde954 - Device IN Endpoint 1 DMA Address Register"]
334 pub diep1_dmaaddr: DIEP1_DMAADDR,
335 #[doc = "0xde958 - Device IN Endpoint Transmit FIFO Status Register 1"]
336 pub diep1_dtxfsts: DIEP1_DTXFSTS,
337 _reserved149: [u8; 4usize],
338 #[doc = "0xde960 - Device Control IN Endpoint 1 Control Register"]
339 pub diep2_ctl: DIEP2_CTL,
340 _reserved150: [u8; 4usize],
341 #[doc = "0xde968 - Device IN Endpoint 1 Interrupt Register"]
342 pub diep2_int: DIEP2_INT,
343 _reserved151: [u8; 4usize],
344 #[doc = "0xde970 - Device IN Endpoint 1 Transfer Size Register"]
345 pub diep2_tsiz: DIEP2_TSIZ,
346 #[doc = "0xde974 - Device IN Endpoint 1 DMA Address Register"]
347 pub diep2_dmaaddr: DIEP2_DMAADDR,
348 #[doc = "0xde978 - Device IN Endpoint Transmit FIFO Status Register 1"]
349 pub diep2_dtxfsts: DIEP2_DTXFSTS,
350 _reserved154: [u8; 4usize],
351 #[doc = "0xde980 - Device Control IN Endpoint 1 Control Register"]
352 pub diep3_ctl: DIEP3_CTL,
353 _reserved155: [u8; 4usize],
354 #[doc = "0xde988 - Device IN Endpoint 1 Interrupt Register"]
355 pub diep3_int: DIEP3_INT,
356 _reserved156: [u8; 4usize],
357 #[doc = "0xde990 - Device IN Endpoint 1 Transfer Size Register"]
358 pub diep3_tsiz: DIEP3_TSIZ,
359 #[doc = "0xde994 - Device IN Endpoint 1 DMA Address Register"]
360 pub diep3_dmaaddr: DIEP3_DMAADDR,
361 #[doc = "0xde998 - Device IN Endpoint Transmit FIFO Status Register 1"]
362 pub diep3_dtxfsts: DIEP3_DTXFSTS,
363 _reserved159: [u8; 4usize],
364 #[doc = "0xde9a0 - Device Control IN Endpoint 1 Control Register"]
365 pub diep4_ctl: DIEP4_CTL,
366 _reserved160: [u8; 4usize],
367 #[doc = "0xde9a8 - Device IN Endpoint 1 Interrupt Register"]
368 pub diep4_int: DIEP4_INT,
369 _reserved161: [u8; 4usize],
370 #[doc = "0xde9b0 - Device IN Endpoint 1 Transfer Size Register"]
371 pub diep4_tsiz: DIEP4_TSIZ,
372 #[doc = "0xde9b4 - Device IN Endpoint 1 DMA Address Register"]
373 pub diep4_dmaaddr: DIEP4_DMAADDR,
374 #[doc = "0xde9b8 - Device IN Endpoint Transmit FIFO Status Register 1"]
375 pub diep4_dtxfsts: DIEP4_DTXFSTS,
376 _reserved164: [u8; 4usize],
377 #[doc = "0xde9c0 - Device Control IN Endpoint 1 Control Register"]
378 pub diep5_ctl: DIEP5_CTL,
379 _reserved165: [u8; 4usize],
380 #[doc = "0xde9c8 - Device IN Endpoint 1 Interrupt Register"]
381 pub diep5_int: DIEP5_INT,
382 _reserved166: [u8; 4usize],
383 #[doc = "0xde9d0 - Device IN Endpoint 1 Transfer Size Register"]
384 pub diep5_tsiz: DIEP5_TSIZ,
385 #[doc = "0xde9d4 - Device IN Endpoint 1 DMA Address Register"]
386 pub diep5_dmaaddr: DIEP5_DMAADDR,
387 #[doc = "0xde9d8 - Device IN Endpoint Transmit FIFO Status Register 1"]
388 pub diep5_dtxfsts: DIEP5_DTXFSTS,
389 _reserved169: [u8; 292usize],
390 #[doc = "0xdeb00 - Device Control OUT Endpoint 0 Control Register"]
391 pub doep0ctl: DOEP0CTL,
392 _reserved170: [u8; 4usize],
393 #[doc = "0xdeb08 - Device OUT Endpoint 0 Interrupt Register"]
394 pub doep0int: DOEP0INT,
395 _reserved171: [u8; 4usize],
396 #[doc = "0xdeb10 - Device OUT Endpoint 0 Transfer Size Register"]
397 pub doep0tsiz: DOEP0TSIZ,
398 #[doc = "0xdeb14 - Device OUT Endpoint 0 DMA Address Register"]
399 pub doep0dmaaddr: DOEP0DMAADDR,
400 _reserved173: [u8; 8usize],
401 #[doc = "0xdeb20 - Device Control OUT Endpoint 1 Control Register"]
402 pub doep0_ctl: DOEP0_CTL,
403 _reserved174: [u8; 4usize],
404 #[doc = "0xdeb28 - Device OUT Endpoint 1 Interrupt Register"]
405 pub doep0_int: DOEP0_INT,
406 _reserved175: [u8; 4usize],
407 #[doc = "0xdeb30 - Device OUT Endpoint 1 Transfer Size Register"]
408 pub doep0_tsiz: DOEP0_TSIZ,
409 #[doc = "0xdeb34 - Device OUT Endpoint 1 DMA Address Register"]
410 pub doep0_dmaaddr: DOEP0_DMAADDR,
411 _reserved177: [u8; 8usize],
412 #[doc = "0xdeb40 - Device Control OUT Endpoint 1 Control Register"]
413 pub doep1_ctl: DOEP1_CTL,
414 _reserved178: [u8; 4usize],
415 #[doc = "0xdeb48 - Device OUT Endpoint 1 Interrupt Register"]
416 pub doep1_int: DOEP1_INT,
417 _reserved179: [u8; 4usize],
418 #[doc = "0xdeb50 - Device OUT Endpoint 1 Transfer Size Register"]
419 pub doep1_tsiz: DOEP1_TSIZ,
420 #[doc = "0xdeb54 - Device OUT Endpoint 1 DMA Address Register"]
421 pub doep1_dmaaddr: DOEP1_DMAADDR,
422 _reserved181: [u8; 8usize],
423 #[doc = "0xdeb60 - Device Control OUT Endpoint 1 Control Register"]
424 pub doep2_ctl: DOEP2_CTL,
425 _reserved182: [u8; 4usize],
426 #[doc = "0xdeb68 - Device OUT Endpoint 1 Interrupt Register"]
427 pub doep2_int: DOEP2_INT,
428 _reserved183: [u8; 4usize],
429 #[doc = "0xdeb70 - Device OUT Endpoint 1 Transfer Size Register"]
430 pub doep2_tsiz: DOEP2_TSIZ,
431 #[doc = "0xdeb74 - Device OUT Endpoint 1 DMA Address Register"]
432 pub doep2_dmaaddr: DOEP2_DMAADDR,
433 _reserved185: [u8; 8usize],
434 #[doc = "0xdeb80 - Device Control OUT Endpoint 1 Control Register"]
435 pub doep3_ctl: DOEP3_CTL,
436 _reserved186: [u8; 4usize],
437 #[doc = "0xdeb88 - Device OUT Endpoint 1 Interrupt Register"]
438 pub doep3_int: DOEP3_INT,
439 _reserved187: [u8; 4usize],
440 #[doc = "0xdeb90 - Device OUT Endpoint 1 Transfer Size Register"]
441 pub doep3_tsiz: DOEP3_TSIZ,
442 #[doc = "0xdeb94 - Device OUT Endpoint 1 DMA Address Register"]
443 pub doep3_dmaaddr: DOEP3_DMAADDR,
444 _reserved189: [u8; 8usize],
445 #[doc = "0xdeba0 - Device Control OUT Endpoint 1 Control Register"]
446 pub doep4_ctl: DOEP4_CTL,
447 _reserved190: [u8; 4usize],
448 #[doc = "0xdeba8 - Device OUT Endpoint 1 Interrupt Register"]
449 pub doep4_int: DOEP4_INT,
450 _reserved191: [u8; 4usize],
451 #[doc = "0xdebb0 - Device OUT Endpoint 1 Transfer Size Register"]
452 pub doep4_tsiz: DOEP4_TSIZ,
453 #[doc = "0xdebb4 - Device OUT Endpoint 1 DMA Address Register"]
454 pub doep4_dmaaddr: DOEP4_DMAADDR,
455 _reserved193: [u8; 8usize],
456 #[doc = "0xdebc0 - Device Control OUT Endpoint 1 Control Register"]
457 pub doep5_ctl: DOEP5_CTL,
458 _reserved194: [u8; 4usize],
459 #[doc = "0xdebc8 - Device OUT Endpoint 1 Interrupt Register"]
460 pub doep5_int: DOEP5_INT,
461 _reserved195: [u8; 4usize],
462 #[doc = "0xdebd0 - Device OUT Endpoint 1 Transfer Size Register"]
463 pub doep5_tsiz: DOEP5_TSIZ,
464 #[doc = "0xdebd4 - Device OUT Endpoint 1 DMA Address Register"]
465 pub doep5_dmaaddr: DOEP5_DMAADDR,
466 _reserved197: [u8; 552usize],
467 #[doc = "0xdee00 - Power and Clock Gating Control Register"]
468 pub pcgcctl: PCGCCTL,
469}
470#[doc = "System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](ctrl) module"]
471pub type CTRL = crate::Reg<u32, _CTRL>;
472#[allow(missing_docs)]
473#[doc(hidden)]
474pub struct _CTRL;
475#[doc = "`read()` method returns [ctrl::R](ctrl::R) reader structure"]
476impl crate::Readable for CTRL {}
477#[doc = "`write(|w| ..)` method takes [ctrl::W](ctrl::W) writer structure"]
478impl crate::Writable for CTRL {}
479#[doc = "System Control Register"]
480pub mod ctrl;
481#[doc = "System Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](status) module"]
482pub type STATUS = crate::Reg<u32, _STATUS>;
483#[allow(missing_docs)]
484#[doc(hidden)]
485pub struct _STATUS;
486#[doc = "`read()` method returns [status::R](status::R) reader structure"]
487impl crate::Readable for STATUS {}
488#[doc = "System Status Register"]
489pub mod status;
490#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [if_](if_) module"]
491pub type IF = crate::Reg<u32, _IF>;
492#[allow(missing_docs)]
493#[doc(hidden)]
494pub struct _IF;
495#[doc = "`read()` method returns [if_::R](if_::R) reader structure"]
496impl crate::Readable for IF {}
497#[doc = "Interrupt Flag Register"]
498pub mod if_;
499#[doc = "Interrupt Flag Set Register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifs](ifs) module"]
500pub type IFS = crate::Reg<u32, _IFS>;
501#[allow(missing_docs)]
502#[doc(hidden)]
503pub struct _IFS;
504#[doc = "`write(|w| ..)` method takes [ifs::W](ifs::W) writer structure"]
505impl crate::Writable for IFS {}
506#[doc = "Interrupt Flag Set Register"]
507pub mod ifs;
508#[doc = "Interrupt Flag Clear Register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifc](ifc) module"]
509pub type IFC = crate::Reg<u32, _IFC>;
510#[allow(missing_docs)]
511#[doc(hidden)]
512pub struct _IFC;
513#[doc = "`write(|w| ..)` method takes [ifc::W](ifc::W) writer structure"]
514impl crate::Writable for IFC {}
515#[doc = "Interrupt Flag Clear Register"]
516pub mod ifc;
517#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](ien) module"]
518pub type IEN = crate::Reg<u32, _IEN>;
519#[allow(missing_docs)]
520#[doc(hidden)]
521pub struct _IEN;
522#[doc = "`read()` method returns [ien::R](ien::R) reader structure"]
523impl crate::Readable for IEN {}
524#[doc = "`write(|w| ..)` method takes [ien::W](ien::W) writer structure"]
525impl crate::Writable for IEN {}
526#[doc = "Interrupt Enable Register"]
527pub mod ien;
528#[doc = "I/O Routing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [route](route) module"]
529pub type ROUTE = crate::Reg<u32, _ROUTE>;
530#[allow(missing_docs)]
531#[doc(hidden)]
532pub struct _ROUTE;
533#[doc = "`read()` method returns [route::R](route::R) reader structure"]
534impl crate::Readable for ROUTE {}
535#[doc = "`write(|w| ..)` method takes [route::W](route::W) writer structure"]
536impl crate::Writable for ROUTE {}
537#[doc = "I/O Routing Register"]
538pub mod route;
539#[doc = "Charger Detect Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdconf](cdconf) module"]
540pub type CDCONF = crate::Reg<u32, _CDCONF>;
541#[allow(missing_docs)]
542#[doc(hidden)]
543pub struct _CDCONF;
544#[doc = "`read()` method returns [cdconf::R](cdconf::R) reader structure"]
545impl crate::Readable for CDCONF {}
546#[doc = "`write(|w| ..)` method takes [cdconf::W](cdconf::W) writer structure"]
547impl crate::Writable for CDCONF {}
548#[doc = "Charger Detect Configuration Register"]
549pub mod cdconf;
550#[doc = "Command Register\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmd](cmd) module"]
551pub type CMD = crate::Reg<u32, _CMD>;
552#[allow(missing_docs)]
553#[doc(hidden)]
554pub struct _CMD;
555#[doc = "`write(|w| ..)` method takes [cmd::W](cmd::W) writer structure"]
556impl crate::Writable for CMD {}
557#[doc = "Command Register"]
558pub mod cmd;
559#[doc = "Data TRIM 1 Values for USB DP and DM\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dattrim1](dattrim1) module"]
560pub type DATTRIM1 = crate::Reg<u32, _DATTRIM1>;
561#[allow(missing_docs)]
562#[doc(hidden)]
563pub struct _DATTRIM1;
564#[doc = "`read()` method returns [dattrim1::R](dattrim1::R) reader structure"]
565impl crate::Readable for DATTRIM1 {}
566#[doc = "`write(|w| ..)` method takes [dattrim1::W](dattrim1::W) writer structure"]
567impl crate::Writable for DATTRIM1 {}
568#[doc = "Data TRIM 1 Values for USB DP and DM"]
569pub mod dattrim1;
570#[doc = "USB LEM Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lemctrl](lemctrl) module"]
571pub type LEMCTRL = crate::Reg<u32, _LEMCTRL>;
572#[allow(missing_docs)]
573#[doc(hidden)]
574pub struct _LEMCTRL;
575#[doc = "`read()` method returns [lemctrl::R](lemctrl::R) reader structure"]
576impl crate::Readable for LEMCTRL {}
577#[doc = "`write(|w| ..)` method takes [lemctrl::W](lemctrl::W) writer structure"]
578impl crate::Writable for LEMCTRL {}
579#[doc = "USB LEM Control Register"]
580pub mod lemctrl;
581#[doc = "OTG Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgctl](gotgctl) module"]
582pub type GOTGCTL = crate::Reg<u32, _GOTGCTL>;
583#[allow(missing_docs)]
584#[doc(hidden)]
585pub struct _GOTGCTL;
586#[doc = "`read()` method returns [gotgctl::R](gotgctl::R) reader structure"]
587impl crate::Readable for GOTGCTL {}
588#[doc = "`write(|w| ..)` method takes [gotgctl::W](gotgctl::W) writer structure"]
589impl crate::Writable for GOTGCTL {}
590#[doc = "OTG Control and Status Register"]
591pub mod gotgctl;
592#[doc = "OTG Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gotgint](gotgint) module"]
593pub type GOTGINT = crate::Reg<u32, _GOTGINT>;
594#[allow(missing_docs)]
595#[doc(hidden)]
596pub struct _GOTGINT;
597#[doc = "`read()` method returns [gotgint::R](gotgint::R) reader structure"]
598impl crate::Readable for GOTGINT {}
599#[doc = "`write(|w| ..)` method takes [gotgint::W](gotgint::W) writer structure"]
600impl crate::Writable for GOTGINT {}
601#[doc = "OTG Interrupt Register"]
602pub mod gotgint;
603#[doc = "AHB Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gahbcfg](gahbcfg) module"]
604pub type GAHBCFG = crate::Reg<u32, _GAHBCFG>;
605#[allow(missing_docs)]
606#[doc(hidden)]
607pub struct _GAHBCFG;
608#[doc = "`read()` method returns [gahbcfg::R](gahbcfg::R) reader structure"]
609impl crate::Readable for GAHBCFG {}
610#[doc = "`write(|w| ..)` method takes [gahbcfg::W](gahbcfg::W) writer structure"]
611impl crate::Writable for GAHBCFG {}
612#[doc = "AHB Configuration Register"]
613pub mod gahbcfg;
614#[doc = "USB Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gusbcfg](gusbcfg) module"]
615pub type GUSBCFG = crate::Reg<u32, _GUSBCFG>;
616#[allow(missing_docs)]
617#[doc(hidden)]
618pub struct _GUSBCFG;
619#[doc = "`read()` method returns [gusbcfg::R](gusbcfg::R) reader structure"]
620impl crate::Readable for GUSBCFG {}
621#[doc = "`write(|w| ..)` method takes [gusbcfg::W](gusbcfg::W) writer structure"]
622impl crate::Writable for GUSBCFG {}
623#[doc = "USB Configuration Register"]
624pub mod gusbcfg;
625#[doc = "Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grstctl](grstctl) module"]
626pub type GRSTCTL = crate::Reg<u32, _GRSTCTL>;
627#[allow(missing_docs)]
628#[doc(hidden)]
629pub struct _GRSTCTL;
630#[doc = "`read()` method returns [grstctl::R](grstctl::R) reader structure"]
631impl crate::Readable for GRSTCTL {}
632#[doc = "`write(|w| ..)` method takes [grstctl::W](grstctl::W) writer structure"]
633impl crate::Writable for GRSTCTL {}
634#[doc = "Reset Register"]
635pub mod grstctl;
636#[doc = "Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintsts](gintsts) module"]
637pub type GINTSTS = crate::Reg<u32, _GINTSTS>;
638#[allow(missing_docs)]
639#[doc(hidden)]
640pub struct _GINTSTS;
641#[doc = "`read()` method returns [gintsts::R](gintsts::R) reader structure"]
642impl crate::Readable for GINTSTS {}
643#[doc = "`write(|w| ..)` method takes [gintsts::W](gintsts::W) writer structure"]
644impl crate::Writable for GINTSTS {}
645#[doc = "Interrupt Register"]
646pub mod gintsts;
647#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gintmsk](gintmsk) module"]
648pub type GINTMSK = crate::Reg<u32, _GINTMSK>;
649#[allow(missing_docs)]
650#[doc(hidden)]
651pub struct _GINTMSK;
652#[doc = "`read()` method returns [gintmsk::R](gintmsk::R) reader structure"]
653impl crate::Readable for GINTMSK {}
654#[doc = "`write(|w| ..)` method takes [gintmsk::W](gintmsk::W) writer structure"]
655impl crate::Writable for GINTMSK {}
656#[doc = "Interrupt Mask Register"]
657pub mod gintmsk;
658#[doc = "Receive Status Debug Read Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsr](grxstsr) module"]
659pub type GRXSTSR = crate::Reg<u32, _GRXSTSR>;
660#[allow(missing_docs)]
661#[doc(hidden)]
662pub struct _GRXSTSR;
663#[doc = "`read()` method returns [grxstsr::R](grxstsr::R) reader structure"]
664impl crate::Readable for GRXSTSR {}
665#[doc = "Receive Status Debug Read Register"]
666pub mod grxstsr;
667#[doc = "Receive Status Read /Pop Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxstsp](grxstsp) module"]
668pub type GRXSTSP = crate::Reg<u32, _GRXSTSP>;
669#[allow(missing_docs)]
670#[doc(hidden)]
671pub struct _GRXSTSP;
672#[doc = "`read()` method returns [grxstsp::R](grxstsp::R) reader structure"]
673impl crate::Readable for GRXSTSP {}
674#[doc = "Receive Status Read /Pop Register"]
675pub mod grxstsp;
676#[doc = "Receive FIFO Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grxfsiz](grxfsiz) module"]
677pub type GRXFSIZ = crate::Reg<u32, _GRXFSIZ>;
678#[allow(missing_docs)]
679#[doc(hidden)]
680pub struct _GRXFSIZ;
681#[doc = "`read()` method returns [grxfsiz::R](grxfsiz::R) reader structure"]
682impl crate::Readable for GRXFSIZ {}
683#[doc = "`write(|w| ..)` method takes [grxfsiz::W](grxfsiz::W) writer structure"]
684impl crate::Writable for GRXFSIZ {}
685#[doc = "Receive FIFO Size Register"]
686pub mod grxfsiz;
687#[doc = "Non-periodic Transmit FIFO Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxfsiz](gnptxfsiz) module"]
688pub type GNPTXFSIZ = crate::Reg<u32, _GNPTXFSIZ>;
689#[allow(missing_docs)]
690#[doc(hidden)]
691pub struct _GNPTXFSIZ;
692#[doc = "`read()` method returns [gnptxfsiz::R](gnptxfsiz::R) reader structure"]
693impl crate::Readable for GNPTXFSIZ {}
694#[doc = "`write(|w| ..)` method takes [gnptxfsiz::W](gnptxfsiz::W) writer structure"]
695impl crate::Writable for GNPTXFSIZ {}
696#[doc = "Non-periodic Transmit FIFO Size Register"]
697pub mod gnptxfsiz;
698#[doc = "Non-periodic Transmit FIFO/Queue Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gnptxsts](gnptxsts) module"]
699pub type GNPTXSTS = crate::Reg<u32, _GNPTXSTS>;
700#[allow(missing_docs)]
701#[doc(hidden)]
702pub struct _GNPTXSTS;
703#[doc = "`read()` method returns [gnptxsts::R](gnptxsts::R) reader structure"]
704impl crate::Readable for GNPTXSTS {}
705#[doc = "Non-periodic Transmit FIFO/Queue Status Register"]
706pub mod gnptxsts;
707#[doc = "Synopsys ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gsnpsid](gsnpsid) module"]
708pub type GSNPSID = crate::Reg<u32, _GSNPSID>;
709#[allow(missing_docs)]
710#[doc(hidden)]
711pub struct _GSNPSID;
712#[doc = "`read()` method returns [gsnpsid::R](gsnpsid::R) reader structure"]
713impl crate::Readable for GSNPSID {}
714#[doc = "Synopsys ID Register"]
715pub mod gsnpsid;
716#[doc = "Global DFIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gdfifocfg](gdfifocfg) module"]
717pub type GDFIFOCFG = crate::Reg<u32, _GDFIFOCFG>;
718#[allow(missing_docs)]
719#[doc(hidden)]
720pub struct _GDFIFOCFG;
721#[doc = "`read()` method returns [gdfifocfg::R](gdfifocfg::R) reader structure"]
722impl crate::Readable for GDFIFOCFG {}
723#[doc = "`write(|w| ..)` method takes [gdfifocfg::W](gdfifocfg::W) writer structure"]
724impl crate::Writable for GDFIFOCFG {}
725#[doc = "Global DFIFO Configuration Register"]
726pub mod gdfifocfg;
727#[doc = "Host Periodic Transmit FIFO Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxfsiz](hptxfsiz) module"]
728pub type HPTXFSIZ = crate::Reg<u32, _HPTXFSIZ>;
729#[allow(missing_docs)]
730#[doc(hidden)]
731pub struct _HPTXFSIZ;
732#[doc = "`read()` method returns [hptxfsiz::R](hptxfsiz::R) reader structure"]
733impl crate::Readable for HPTXFSIZ {}
734#[doc = "`write(|w| ..)` method takes [hptxfsiz::W](hptxfsiz::W) writer structure"]
735impl crate::Writable for HPTXFSIZ {}
736#[doc = "Host Periodic Transmit FIFO Size Register"]
737pub mod hptxfsiz;
738#[doc = "Device IN Endpoint Transmit FIFO Size Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf1](dieptxf1) module"]
739pub type DIEPTXF1 = crate::Reg<u32, _DIEPTXF1>;
740#[allow(missing_docs)]
741#[doc(hidden)]
742pub struct _DIEPTXF1;
743#[doc = "`read()` method returns [dieptxf1::R](dieptxf1::R) reader structure"]
744impl crate::Readable for DIEPTXF1 {}
745#[doc = "`write(|w| ..)` method takes [dieptxf1::W](dieptxf1::W) writer structure"]
746impl crate::Writable for DIEPTXF1 {}
747#[doc = "Device IN Endpoint Transmit FIFO Size Register 1"]
748pub mod dieptxf1;
749#[doc = "Device IN Endpoint Transmit FIFO Size Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf2](dieptxf2) module"]
750pub type DIEPTXF2 = crate::Reg<u32, _DIEPTXF2>;
751#[allow(missing_docs)]
752#[doc(hidden)]
753pub struct _DIEPTXF2;
754#[doc = "`read()` method returns [dieptxf2::R](dieptxf2::R) reader structure"]
755impl crate::Readable for DIEPTXF2 {}
756#[doc = "`write(|w| ..)` method takes [dieptxf2::W](dieptxf2::W) writer structure"]
757impl crate::Writable for DIEPTXF2 {}
758#[doc = "Device IN Endpoint Transmit FIFO Size Register 2"]
759pub mod dieptxf2;
760#[doc = "Device IN Endpoint Transmit FIFO Size Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf3](dieptxf3) module"]
761pub type DIEPTXF3 = crate::Reg<u32, _DIEPTXF3>;
762#[allow(missing_docs)]
763#[doc(hidden)]
764pub struct _DIEPTXF3;
765#[doc = "`read()` method returns [dieptxf3::R](dieptxf3::R) reader structure"]
766impl crate::Readable for DIEPTXF3 {}
767#[doc = "`write(|w| ..)` method takes [dieptxf3::W](dieptxf3::W) writer structure"]
768impl crate::Writable for DIEPTXF3 {}
769#[doc = "Device IN Endpoint Transmit FIFO Size Register 3"]
770pub mod dieptxf3;
771#[doc = "Device IN Endpoint Transmit FIFO Size Register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf4](dieptxf4) module"]
772pub type DIEPTXF4 = crate::Reg<u32, _DIEPTXF4>;
773#[allow(missing_docs)]
774#[doc(hidden)]
775pub struct _DIEPTXF4;
776#[doc = "`read()` method returns [dieptxf4::R](dieptxf4::R) reader structure"]
777impl crate::Readable for DIEPTXF4 {}
778#[doc = "`write(|w| ..)` method takes [dieptxf4::W](dieptxf4::W) writer structure"]
779impl crate::Writable for DIEPTXF4 {}
780#[doc = "Device IN Endpoint Transmit FIFO Size Register 4"]
781pub mod dieptxf4;
782#[doc = "Device IN Endpoint Transmit FIFO Size Register 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf5](dieptxf5) module"]
783pub type DIEPTXF5 = crate::Reg<u32, _DIEPTXF5>;
784#[allow(missing_docs)]
785#[doc(hidden)]
786pub struct _DIEPTXF5;
787#[doc = "`read()` method returns [dieptxf5::R](dieptxf5::R) reader structure"]
788impl crate::Readable for DIEPTXF5 {}
789#[doc = "`write(|w| ..)` method takes [dieptxf5::W](dieptxf5::W) writer structure"]
790impl crate::Writable for DIEPTXF5 {}
791#[doc = "Device IN Endpoint Transmit FIFO Size Register 5"]
792pub mod dieptxf5;
793#[doc = "Device IN Endpoint Transmit FIFO Size Register 6\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dieptxf6](dieptxf6) module"]
794pub type DIEPTXF6 = crate::Reg<u32, _DIEPTXF6>;
795#[allow(missing_docs)]
796#[doc(hidden)]
797pub struct _DIEPTXF6;
798#[doc = "`read()` method returns [dieptxf6::R](dieptxf6::R) reader structure"]
799impl crate::Readable for DIEPTXF6 {}
800#[doc = "`write(|w| ..)` method takes [dieptxf6::W](dieptxf6::W) writer structure"]
801impl crate::Writable for DIEPTXF6 {}
802#[doc = "Device IN Endpoint Transmit FIFO Size Register 6"]
803pub mod dieptxf6;
804#[doc = "Host Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](hcfg) module"]
805pub type HCFG = crate::Reg<u32, _HCFG>;
806#[allow(missing_docs)]
807#[doc(hidden)]
808pub struct _HCFG;
809#[doc = "`read()` method returns [hcfg::R](hcfg::R) reader structure"]
810impl crate::Readable for HCFG {}
811#[doc = "`write(|w| ..)` method takes [hcfg::W](hcfg::W) writer structure"]
812impl crate::Writable for HCFG {}
813#[doc = "Host Configuration Register"]
814pub mod hcfg;
815#[doc = "Host Frame Interval Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfir](hfir) module"]
816pub type HFIR = crate::Reg<u32, _HFIR>;
817#[allow(missing_docs)]
818#[doc(hidden)]
819pub struct _HFIR;
820#[doc = "`read()` method returns [hfir::R](hfir::R) reader structure"]
821impl crate::Readable for HFIR {}
822#[doc = "`write(|w| ..)` method takes [hfir::W](hfir::W) writer structure"]
823impl crate::Writable for HFIR {}
824#[doc = "Host Frame Interval Register"]
825pub mod hfir;
826#[doc = "Host Frame Number/Frame Time Remaining Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfnum](hfnum) module"]
827pub type HFNUM = crate::Reg<u32, _HFNUM>;
828#[allow(missing_docs)]
829#[doc(hidden)]
830pub struct _HFNUM;
831#[doc = "`read()` method returns [hfnum::R](hfnum::R) reader structure"]
832impl crate::Readable for HFNUM {}
833#[doc = "Host Frame Number/Frame Time Remaining Register"]
834pub mod hfnum;
835#[doc = "Host Periodic Transmit FIFO/Queue Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hptxsts](hptxsts) module"]
836pub type HPTXSTS = crate::Reg<u32, _HPTXSTS>;
837#[allow(missing_docs)]
838#[doc(hidden)]
839pub struct _HPTXSTS;
840#[doc = "`read()` method returns [hptxsts::R](hptxsts::R) reader structure"]
841impl crate::Readable for HPTXSTS {}
842#[doc = "Host Periodic Transmit FIFO/Queue Status Register"]
843pub mod hptxsts;
844#[doc = "Host All Channels Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haint](haint) module"]
845pub type HAINT = crate::Reg<u32, _HAINT>;
846#[allow(missing_docs)]
847#[doc(hidden)]
848pub struct _HAINT;
849#[doc = "`read()` method returns [haint::R](haint::R) reader structure"]
850impl crate::Readable for HAINT {}
851#[doc = "Host All Channels Interrupt Register"]
852pub mod haint;
853#[doc = "Host All Channels Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [haintmsk](haintmsk) module"]
854pub type HAINTMSK = crate::Reg<u32, _HAINTMSK>;
855#[allow(missing_docs)]
856#[doc(hidden)]
857pub struct _HAINTMSK;
858#[doc = "`read()` method returns [haintmsk::R](haintmsk::R) reader structure"]
859impl crate::Readable for HAINTMSK {}
860#[doc = "`write(|w| ..)` method takes [haintmsk::W](haintmsk::W) writer structure"]
861impl crate::Writable for HAINTMSK {}
862#[doc = "Host All Channels Interrupt Mask Register"]
863pub mod haintmsk;
864#[doc = "Host Port Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](hprt) module"]
865pub type HPRT = crate::Reg<u32, _HPRT>;
866#[allow(missing_docs)]
867#[doc(hidden)]
868pub struct _HPRT;
869#[doc = "`read()` method returns [hprt::R](hprt::R) reader structure"]
870impl crate::Readable for HPRT {}
871#[doc = "`write(|w| ..)` method takes [hprt::W](hprt::W) writer structure"]
872impl crate::Writable for HPRT {}
873#[doc = "Host Port Control and Status Register"]
874pub mod hprt;
875#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_char](hc0_char) module"]
876pub type HC0_CHAR = crate::Reg<u32, _HC0_CHAR>;
877#[allow(missing_docs)]
878#[doc(hidden)]
879pub struct _HC0_CHAR;
880#[doc = "`read()` method returns [hc0_char::R](hc0_char::R) reader structure"]
881impl crate::Readable for HC0_CHAR {}
882#[doc = "`write(|w| ..)` method takes [hc0_char::W](hc0_char::W) writer structure"]
883impl crate::Writable for HC0_CHAR {}
884#[doc = "Host Channel 0 Characteristics Register"]
885pub mod hc0_char;
886#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_splt](hc0_splt) module"]
887pub type HC0_SPLT = crate::Reg<u32, _HC0_SPLT>;
888#[allow(missing_docs)]
889#[doc(hidden)]
890pub struct _HC0_SPLT;
891#[doc = "`read()` method returns [hc0_splt::R](hc0_splt::R) reader structure"]
892impl crate::Readable for HC0_SPLT {}
893#[doc = "`write(|w| ..)` method takes [hc0_splt::W](hc0_splt::W) writer structure"]
894impl crate::Writable for HC0_SPLT {}
895#[doc = "Host Channel 0 Split Control Register"]
896pub mod hc0_splt;
897#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_int](hc0_int) module"]
898pub type HC0_INT = crate::Reg<u32, _HC0_INT>;
899#[allow(missing_docs)]
900#[doc(hidden)]
901pub struct _HC0_INT;
902#[doc = "`read()` method returns [hc0_int::R](hc0_int::R) reader structure"]
903impl crate::Readable for HC0_INT {}
904#[doc = "`write(|w| ..)` method takes [hc0_int::W](hc0_int::W) writer structure"]
905impl crate::Writable for HC0_INT {}
906#[doc = "Host Channel 0 Interrupt Register"]
907pub mod hc0_int;
908#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_intmsk](hc0_intmsk) module"]
909pub type HC0_INTMSK = crate::Reg<u32, _HC0_INTMSK>;
910#[allow(missing_docs)]
911#[doc(hidden)]
912pub struct _HC0_INTMSK;
913#[doc = "`read()` method returns [hc0_intmsk::R](hc0_intmsk::R) reader structure"]
914impl crate::Readable for HC0_INTMSK {}
915#[doc = "`write(|w| ..)` method takes [hc0_intmsk::W](hc0_intmsk::W) writer structure"]
916impl crate::Writable for HC0_INTMSK {}
917#[doc = "Host Channel 0 Interrupt Mask Register"]
918pub mod hc0_intmsk;
919#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_tsiz](hc0_tsiz) module"]
920pub type HC0_TSIZ = crate::Reg<u32, _HC0_TSIZ>;
921#[allow(missing_docs)]
922#[doc(hidden)]
923pub struct _HC0_TSIZ;
924#[doc = "`read()` method returns [hc0_tsiz::R](hc0_tsiz::R) reader structure"]
925impl crate::Readable for HC0_TSIZ {}
926#[doc = "`write(|w| ..)` method takes [hc0_tsiz::W](hc0_tsiz::W) writer structure"]
927impl crate::Writable for HC0_TSIZ {}
928#[doc = "Host Channel 0 Transfer Size Register"]
929pub mod hc0_tsiz;
930#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc0_dmaaddr](hc0_dmaaddr) module"]
931pub type HC0_DMAADDR = crate::Reg<u32, _HC0_DMAADDR>;
932#[allow(missing_docs)]
933#[doc(hidden)]
934pub struct _HC0_DMAADDR;
935#[doc = "`read()` method returns [hc0_dmaaddr::R](hc0_dmaaddr::R) reader structure"]
936impl crate::Readable for HC0_DMAADDR {}
937#[doc = "`write(|w| ..)` method takes [hc0_dmaaddr::W](hc0_dmaaddr::W) writer structure"]
938impl crate::Writable for HC0_DMAADDR {}
939#[doc = "Host Channel 0 DMA Address Register"]
940pub mod hc0_dmaaddr;
941#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_char](hc1_char) module"]
942pub type HC1_CHAR = crate::Reg<u32, _HC1_CHAR>;
943#[allow(missing_docs)]
944#[doc(hidden)]
945pub struct _HC1_CHAR;
946#[doc = "`read()` method returns [hc1_char::R](hc1_char::R) reader structure"]
947impl crate::Readable for HC1_CHAR {}
948#[doc = "`write(|w| ..)` method takes [hc1_char::W](hc1_char::W) writer structure"]
949impl crate::Writable for HC1_CHAR {}
950#[doc = "Host Channel 0 Characteristics Register"]
951pub mod hc1_char;
952#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_splt](hc1_splt) module"]
953pub type HC1_SPLT = crate::Reg<u32, _HC1_SPLT>;
954#[allow(missing_docs)]
955#[doc(hidden)]
956pub struct _HC1_SPLT;
957#[doc = "`read()` method returns [hc1_splt::R](hc1_splt::R) reader structure"]
958impl crate::Readable for HC1_SPLT {}
959#[doc = "`write(|w| ..)` method takes [hc1_splt::W](hc1_splt::W) writer structure"]
960impl crate::Writable for HC1_SPLT {}
961#[doc = "Host Channel 0 Split Control Register"]
962pub mod hc1_splt;
963#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_int](hc1_int) module"]
964pub type HC1_INT = crate::Reg<u32, _HC1_INT>;
965#[allow(missing_docs)]
966#[doc(hidden)]
967pub struct _HC1_INT;
968#[doc = "`read()` method returns [hc1_int::R](hc1_int::R) reader structure"]
969impl crate::Readable for HC1_INT {}
970#[doc = "`write(|w| ..)` method takes [hc1_int::W](hc1_int::W) writer structure"]
971impl crate::Writable for HC1_INT {}
972#[doc = "Host Channel 0 Interrupt Register"]
973pub mod hc1_int;
974#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_intmsk](hc1_intmsk) module"]
975pub type HC1_INTMSK = crate::Reg<u32, _HC1_INTMSK>;
976#[allow(missing_docs)]
977#[doc(hidden)]
978pub struct _HC1_INTMSK;
979#[doc = "`read()` method returns [hc1_intmsk::R](hc1_intmsk::R) reader structure"]
980impl crate::Readable for HC1_INTMSK {}
981#[doc = "`write(|w| ..)` method takes [hc1_intmsk::W](hc1_intmsk::W) writer structure"]
982impl crate::Writable for HC1_INTMSK {}
983#[doc = "Host Channel 0 Interrupt Mask Register"]
984pub mod hc1_intmsk;
985#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_tsiz](hc1_tsiz) module"]
986pub type HC1_TSIZ = crate::Reg<u32, _HC1_TSIZ>;
987#[allow(missing_docs)]
988#[doc(hidden)]
989pub struct _HC1_TSIZ;
990#[doc = "`read()` method returns [hc1_tsiz::R](hc1_tsiz::R) reader structure"]
991impl crate::Readable for HC1_TSIZ {}
992#[doc = "`write(|w| ..)` method takes [hc1_tsiz::W](hc1_tsiz::W) writer structure"]
993impl crate::Writable for HC1_TSIZ {}
994#[doc = "Host Channel 0 Transfer Size Register"]
995pub mod hc1_tsiz;
996#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc1_dmaaddr](hc1_dmaaddr) module"]
997pub type HC1_DMAADDR = crate::Reg<u32, _HC1_DMAADDR>;
998#[allow(missing_docs)]
999#[doc(hidden)]
1000pub struct _HC1_DMAADDR;
1001#[doc = "`read()` method returns [hc1_dmaaddr::R](hc1_dmaaddr::R) reader structure"]
1002impl crate::Readable for HC1_DMAADDR {}
1003#[doc = "`write(|w| ..)` method takes [hc1_dmaaddr::W](hc1_dmaaddr::W) writer structure"]
1004impl crate::Writable for HC1_DMAADDR {}
1005#[doc = "Host Channel 0 DMA Address Register"]
1006pub mod hc1_dmaaddr;
1007#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_char](hc2_char) module"]
1008pub type HC2_CHAR = crate::Reg<u32, _HC2_CHAR>;
1009#[allow(missing_docs)]
1010#[doc(hidden)]
1011pub struct _HC2_CHAR;
1012#[doc = "`read()` method returns [hc2_char::R](hc2_char::R) reader structure"]
1013impl crate::Readable for HC2_CHAR {}
1014#[doc = "`write(|w| ..)` method takes [hc2_char::W](hc2_char::W) writer structure"]
1015impl crate::Writable for HC2_CHAR {}
1016#[doc = "Host Channel 0 Characteristics Register"]
1017pub mod hc2_char;
1018#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_splt](hc2_splt) module"]
1019pub type HC2_SPLT = crate::Reg<u32, _HC2_SPLT>;
1020#[allow(missing_docs)]
1021#[doc(hidden)]
1022pub struct _HC2_SPLT;
1023#[doc = "`read()` method returns [hc2_splt::R](hc2_splt::R) reader structure"]
1024impl crate::Readable for HC2_SPLT {}
1025#[doc = "`write(|w| ..)` method takes [hc2_splt::W](hc2_splt::W) writer structure"]
1026impl crate::Writable for HC2_SPLT {}
1027#[doc = "Host Channel 0 Split Control Register"]
1028pub mod hc2_splt;
1029#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_int](hc2_int) module"]
1030pub type HC2_INT = crate::Reg<u32, _HC2_INT>;
1031#[allow(missing_docs)]
1032#[doc(hidden)]
1033pub struct _HC2_INT;
1034#[doc = "`read()` method returns [hc2_int::R](hc2_int::R) reader structure"]
1035impl crate::Readable for HC2_INT {}
1036#[doc = "`write(|w| ..)` method takes [hc2_int::W](hc2_int::W) writer structure"]
1037impl crate::Writable for HC2_INT {}
1038#[doc = "Host Channel 0 Interrupt Register"]
1039pub mod hc2_int;
1040#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_intmsk](hc2_intmsk) module"]
1041pub type HC2_INTMSK = crate::Reg<u32, _HC2_INTMSK>;
1042#[allow(missing_docs)]
1043#[doc(hidden)]
1044pub struct _HC2_INTMSK;
1045#[doc = "`read()` method returns [hc2_intmsk::R](hc2_intmsk::R) reader structure"]
1046impl crate::Readable for HC2_INTMSK {}
1047#[doc = "`write(|w| ..)` method takes [hc2_intmsk::W](hc2_intmsk::W) writer structure"]
1048impl crate::Writable for HC2_INTMSK {}
1049#[doc = "Host Channel 0 Interrupt Mask Register"]
1050pub mod hc2_intmsk;
1051#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_tsiz](hc2_tsiz) module"]
1052pub type HC2_TSIZ = crate::Reg<u32, _HC2_TSIZ>;
1053#[allow(missing_docs)]
1054#[doc(hidden)]
1055pub struct _HC2_TSIZ;
1056#[doc = "`read()` method returns [hc2_tsiz::R](hc2_tsiz::R) reader structure"]
1057impl crate::Readable for HC2_TSIZ {}
1058#[doc = "`write(|w| ..)` method takes [hc2_tsiz::W](hc2_tsiz::W) writer structure"]
1059impl crate::Writable for HC2_TSIZ {}
1060#[doc = "Host Channel 0 Transfer Size Register"]
1061pub mod hc2_tsiz;
1062#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc2_dmaaddr](hc2_dmaaddr) module"]
1063pub type HC2_DMAADDR = crate::Reg<u32, _HC2_DMAADDR>;
1064#[allow(missing_docs)]
1065#[doc(hidden)]
1066pub struct _HC2_DMAADDR;
1067#[doc = "`read()` method returns [hc2_dmaaddr::R](hc2_dmaaddr::R) reader structure"]
1068impl crate::Readable for HC2_DMAADDR {}
1069#[doc = "`write(|w| ..)` method takes [hc2_dmaaddr::W](hc2_dmaaddr::W) writer structure"]
1070impl crate::Writable for HC2_DMAADDR {}
1071#[doc = "Host Channel 0 DMA Address Register"]
1072pub mod hc2_dmaaddr;
1073#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_char](hc3_char) module"]
1074pub type HC3_CHAR = crate::Reg<u32, _HC3_CHAR>;
1075#[allow(missing_docs)]
1076#[doc(hidden)]
1077pub struct _HC3_CHAR;
1078#[doc = "`read()` method returns [hc3_char::R](hc3_char::R) reader structure"]
1079impl crate::Readable for HC3_CHAR {}
1080#[doc = "`write(|w| ..)` method takes [hc3_char::W](hc3_char::W) writer structure"]
1081impl crate::Writable for HC3_CHAR {}
1082#[doc = "Host Channel 0 Characteristics Register"]
1083pub mod hc3_char;
1084#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_splt](hc3_splt) module"]
1085pub type HC3_SPLT = crate::Reg<u32, _HC3_SPLT>;
1086#[allow(missing_docs)]
1087#[doc(hidden)]
1088pub struct _HC3_SPLT;
1089#[doc = "`read()` method returns [hc3_splt::R](hc3_splt::R) reader structure"]
1090impl crate::Readable for HC3_SPLT {}
1091#[doc = "`write(|w| ..)` method takes [hc3_splt::W](hc3_splt::W) writer structure"]
1092impl crate::Writable for HC3_SPLT {}
1093#[doc = "Host Channel 0 Split Control Register"]
1094pub mod hc3_splt;
1095#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_int](hc3_int) module"]
1096pub type HC3_INT = crate::Reg<u32, _HC3_INT>;
1097#[allow(missing_docs)]
1098#[doc(hidden)]
1099pub struct _HC3_INT;
1100#[doc = "`read()` method returns [hc3_int::R](hc3_int::R) reader structure"]
1101impl crate::Readable for HC3_INT {}
1102#[doc = "`write(|w| ..)` method takes [hc3_int::W](hc3_int::W) writer structure"]
1103impl crate::Writable for HC3_INT {}
1104#[doc = "Host Channel 0 Interrupt Register"]
1105pub mod hc3_int;
1106#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_intmsk](hc3_intmsk) module"]
1107pub type HC3_INTMSK = crate::Reg<u32, _HC3_INTMSK>;
1108#[allow(missing_docs)]
1109#[doc(hidden)]
1110pub struct _HC3_INTMSK;
1111#[doc = "`read()` method returns [hc3_intmsk::R](hc3_intmsk::R) reader structure"]
1112impl crate::Readable for HC3_INTMSK {}
1113#[doc = "`write(|w| ..)` method takes [hc3_intmsk::W](hc3_intmsk::W) writer structure"]
1114impl crate::Writable for HC3_INTMSK {}
1115#[doc = "Host Channel 0 Interrupt Mask Register"]
1116pub mod hc3_intmsk;
1117#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_tsiz](hc3_tsiz) module"]
1118pub type HC3_TSIZ = crate::Reg<u32, _HC3_TSIZ>;
1119#[allow(missing_docs)]
1120#[doc(hidden)]
1121pub struct _HC3_TSIZ;
1122#[doc = "`read()` method returns [hc3_tsiz::R](hc3_tsiz::R) reader structure"]
1123impl crate::Readable for HC3_TSIZ {}
1124#[doc = "`write(|w| ..)` method takes [hc3_tsiz::W](hc3_tsiz::W) writer structure"]
1125impl crate::Writable for HC3_TSIZ {}
1126#[doc = "Host Channel 0 Transfer Size Register"]
1127pub mod hc3_tsiz;
1128#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc3_dmaaddr](hc3_dmaaddr) module"]
1129pub type HC3_DMAADDR = crate::Reg<u32, _HC3_DMAADDR>;
1130#[allow(missing_docs)]
1131#[doc(hidden)]
1132pub struct _HC3_DMAADDR;
1133#[doc = "`read()` method returns [hc3_dmaaddr::R](hc3_dmaaddr::R) reader structure"]
1134impl crate::Readable for HC3_DMAADDR {}
1135#[doc = "`write(|w| ..)` method takes [hc3_dmaaddr::W](hc3_dmaaddr::W) writer structure"]
1136impl crate::Writable for HC3_DMAADDR {}
1137#[doc = "Host Channel 0 DMA Address Register"]
1138pub mod hc3_dmaaddr;
1139#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_char](hc4_char) module"]
1140pub type HC4_CHAR = crate::Reg<u32, _HC4_CHAR>;
1141#[allow(missing_docs)]
1142#[doc(hidden)]
1143pub struct _HC4_CHAR;
1144#[doc = "`read()` method returns [hc4_char::R](hc4_char::R) reader structure"]
1145impl crate::Readable for HC4_CHAR {}
1146#[doc = "`write(|w| ..)` method takes [hc4_char::W](hc4_char::W) writer structure"]
1147impl crate::Writable for HC4_CHAR {}
1148#[doc = "Host Channel 0 Characteristics Register"]
1149pub mod hc4_char;
1150#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_splt](hc4_splt) module"]
1151pub type HC4_SPLT = crate::Reg<u32, _HC4_SPLT>;
1152#[allow(missing_docs)]
1153#[doc(hidden)]
1154pub struct _HC4_SPLT;
1155#[doc = "`read()` method returns [hc4_splt::R](hc4_splt::R) reader structure"]
1156impl crate::Readable for HC4_SPLT {}
1157#[doc = "`write(|w| ..)` method takes [hc4_splt::W](hc4_splt::W) writer structure"]
1158impl crate::Writable for HC4_SPLT {}
1159#[doc = "Host Channel 0 Split Control Register"]
1160pub mod hc4_splt;
1161#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_int](hc4_int) module"]
1162pub type HC4_INT = crate::Reg<u32, _HC4_INT>;
1163#[allow(missing_docs)]
1164#[doc(hidden)]
1165pub struct _HC4_INT;
1166#[doc = "`read()` method returns [hc4_int::R](hc4_int::R) reader structure"]
1167impl crate::Readable for HC4_INT {}
1168#[doc = "`write(|w| ..)` method takes [hc4_int::W](hc4_int::W) writer structure"]
1169impl crate::Writable for HC4_INT {}
1170#[doc = "Host Channel 0 Interrupt Register"]
1171pub mod hc4_int;
1172#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_intmsk](hc4_intmsk) module"]
1173pub type HC4_INTMSK = crate::Reg<u32, _HC4_INTMSK>;
1174#[allow(missing_docs)]
1175#[doc(hidden)]
1176pub struct _HC4_INTMSK;
1177#[doc = "`read()` method returns [hc4_intmsk::R](hc4_intmsk::R) reader structure"]
1178impl crate::Readable for HC4_INTMSK {}
1179#[doc = "`write(|w| ..)` method takes [hc4_intmsk::W](hc4_intmsk::W) writer structure"]
1180impl crate::Writable for HC4_INTMSK {}
1181#[doc = "Host Channel 0 Interrupt Mask Register"]
1182pub mod hc4_intmsk;
1183#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_tsiz](hc4_tsiz) module"]
1184pub type HC4_TSIZ = crate::Reg<u32, _HC4_TSIZ>;
1185#[allow(missing_docs)]
1186#[doc(hidden)]
1187pub struct _HC4_TSIZ;
1188#[doc = "`read()` method returns [hc4_tsiz::R](hc4_tsiz::R) reader structure"]
1189impl crate::Readable for HC4_TSIZ {}
1190#[doc = "`write(|w| ..)` method takes [hc4_tsiz::W](hc4_tsiz::W) writer structure"]
1191impl crate::Writable for HC4_TSIZ {}
1192#[doc = "Host Channel 0 Transfer Size Register"]
1193pub mod hc4_tsiz;
1194#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc4_dmaaddr](hc4_dmaaddr) module"]
1195pub type HC4_DMAADDR = crate::Reg<u32, _HC4_DMAADDR>;
1196#[allow(missing_docs)]
1197#[doc(hidden)]
1198pub struct _HC4_DMAADDR;
1199#[doc = "`read()` method returns [hc4_dmaaddr::R](hc4_dmaaddr::R) reader structure"]
1200impl crate::Readable for HC4_DMAADDR {}
1201#[doc = "`write(|w| ..)` method takes [hc4_dmaaddr::W](hc4_dmaaddr::W) writer structure"]
1202impl crate::Writable for HC4_DMAADDR {}
1203#[doc = "Host Channel 0 DMA Address Register"]
1204pub mod hc4_dmaaddr;
1205#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_char](hc5_char) module"]
1206pub type HC5_CHAR = crate::Reg<u32, _HC5_CHAR>;
1207#[allow(missing_docs)]
1208#[doc(hidden)]
1209pub struct _HC5_CHAR;
1210#[doc = "`read()` method returns [hc5_char::R](hc5_char::R) reader structure"]
1211impl crate::Readable for HC5_CHAR {}
1212#[doc = "`write(|w| ..)` method takes [hc5_char::W](hc5_char::W) writer structure"]
1213impl crate::Writable for HC5_CHAR {}
1214#[doc = "Host Channel 0 Characteristics Register"]
1215pub mod hc5_char;
1216#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_splt](hc5_splt) module"]
1217pub type HC5_SPLT = crate::Reg<u32, _HC5_SPLT>;
1218#[allow(missing_docs)]
1219#[doc(hidden)]
1220pub struct _HC5_SPLT;
1221#[doc = "`read()` method returns [hc5_splt::R](hc5_splt::R) reader structure"]
1222impl crate::Readable for HC5_SPLT {}
1223#[doc = "`write(|w| ..)` method takes [hc5_splt::W](hc5_splt::W) writer structure"]
1224impl crate::Writable for HC5_SPLT {}
1225#[doc = "Host Channel 0 Split Control Register"]
1226pub mod hc5_splt;
1227#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_int](hc5_int) module"]
1228pub type HC5_INT = crate::Reg<u32, _HC5_INT>;
1229#[allow(missing_docs)]
1230#[doc(hidden)]
1231pub struct _HC5_INT;
1232#[doc = "`read()` method returns [hc5_int::R](hc5_int::R) reader structure"]
1233impl crate::Readable for HC5_INT {}
1234#[doc = "`write(|w| ..)` method takes [hc5_int::W](hc5_int::W) writer structure"]
1235impl crate::Writable for HC5_INT {}
1236#[doc = "Host Channel 0 Interrupt Register"]
1237pub mod hc5_int;
1238#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_intmsk](hc5_intmsk) module"]
1239pub type HC5_INTMSK = crate::Reg<u32, _HC5_INTMSK>;
1240#[allow(missing_docs)]
1241#[doc(hidden)]
1242pub struct _HC5_INTMSK;
1243#[doc = "`read()` method returns [hc5_intmsk::R](hc5_intmsk::R) reader structure"]
1244impl crate::Readable for HC5_INTMSK {}
1245#[doc = "`write(|w| ..)` method takes [hc5_intmsk::W](hc5_intmsk::W) writer structure"]
1246impl crate::Writable for HC5_INTMSK {}
1247#[doc = "Host Channel 0 Interrupt Mask Register"]
1248pub mod hc5_intmsk;
1249#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_tsiz](hc5_tsiz) module"]
1250pub type HC5_TSIZ = crate::Reg<u32, _HC5_TSIZ>;
1251#[allow(missing_docs)]
1252#[doc(hidden)]
1253pub struct _HC5_TSIZ;
1254#[doc = "`read()` method returns [hc5_tsiz::R](hc5_tsiz::R) reader structure"]
1255impl crate::Readable for HC5_TSIZ {}
1256#[doc = "`write(|w| ..)` method takes [hc5_tsiz::W](hc5_tsiz::W) writer structure"]
1257impl crate::Writable for HC5_TSIZ {}
1258#[doc = "Host Channel 0 Transfer Size Register"]
1259pub mod hc5_tsiz;
1260#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc5_dmaaddr](hc5_dmaaddr) module"]
1261pub type HC5_DMAADDR = crate::Reg<u32, _HC5_DMAADDR>;
1262#[allow(missing_docs)]
1263#[doc(hidden)]
1264pub struct _HC5_DMAADDR;
1265#[doc = "`read()` method returns [hc5_dmaaddr::R](hc5_dmaaddr::R) reader structure"]
1266impl crate::Readable for HC5_DMAADDR {}
1267#[doc = "`write(|w| ..)` method takes [hc5_dmaaddr::W](hc5_dmaaddr::W) writer structure"]
1268impl crate::Writable for HC5_DMAADDR {}
1269#[doc = "Host Channel 0 DMA Address Register"]
1270pub mod hc5_dmaaddr;
1271#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_char](hc6_char) module"]
1272pub type HC6_CHAR = crate::Reg<u32, _HC6_CHAR>;
1273#[allow(missing_docs)]
1274#[doc(hidden)]
1275pub struct _HC6_CHAR;
1276#[doc = "`read()` method returns [hc6_char::R](hc6_char::R) reader structure"]
1277impl crate::Readable for HC6_CHAR {}
1278#[doc = "`write(|w| ..)` method takes [hc6_char::W](hc6_char::W) writer structure"]
1279impl crate::Writable for HC6_CHAR {}
1280#[doc = "Host Channel 0 Characteristics Register"]
1281pub mod hc6_char;
1282#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_splt](hc6_splt) module"]
1283pub type HC6_SPLT = crate::Reg<u32, _HC6_SPLT>;
1284#[allow(missing_docs)]
1285#[doc(hidden)]
1286pub struct _HC6_SPLT;
1287#[doc = "`read()` method returns [hc6_splt::R](hc6_splt::R) reader structure"]
1288impl crate::Readable for HC6_SPLT {}
1289#[doc = "`write(|w| ..)` method takes [hc6_splt::W](hc6_splt::W) writer structure"]
1290impl crate::Writable for HC6_SPLT {}
1291#[doc = "Host Channel 0 Split Control Register"]
1292pub mod hc6_splt;
1293#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_int](hc6_int) module"]
1294pub type HC6_INT = crate::Reg<u32, _HC6_INT>;
1295#[allow(missing_docs)]
1296#[doc(hidden)]
1297pub struct _HC6_INT;
1298#[doc = "`read()` method returns [hc6_int::R](hc6_int::R) reader structure"]
1299impl crate::Readable for HC6_INT {}
1300#[doc = "`write(|w| ..)` method takes [hc6_int::W](hc6_int::W) writer structure"]
1301impl crate::Writable for HC6_INT {}
1302#[doc = "Host Channel 0 Interrupt Register"]
1303pub mod hc6_int;
1304#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_intmsk](hc6_intmsk) module"]
1305pub type HC6_INTMSK = crate::Reg<u32, _HC6_INTMSK>;
1306#[allow(missing_docs)]
1307#[doc(hidden)]
1308pub struct _HC6_INTMSK;
1309#[doc = "`read()` method returns [hc6_intmsk::R](hc6_intmsk::R) reader structure"]
1310impl crate::Readable for HC6_INTMSK {}
1311#[doc = "`write(|w| ..)` method takes [hc6_intmsk::W](hc6_intmsk::W) writer structure"]
1312impl crate::Writable for HC6_INTMSK {}
1313#[doc = "Host Channel 0 Interrupt Mask Register"]
1314pub mod hc6_intmsk;
1315#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_tsiz](hc6_tsiz) module"]
1316pub type HC6_TSIZ = crate::Reg<u32, _HC6_TSIZ>;
1317#[allow(missing_docs)]
1318#[doc(hidden)]
1319pub struct _HC6_TSIZ;
1320#[doc = "`read()` method returns [hc6_tsiz::R](hc6_tsiz::R) reader structure"]
1321impl crate::Readable for HC6_TSIZ {}
1322#[doc = "`write(|w| ..)` method takes [hc6_tsiz::W](hc6_tsiz::W) writer structure"]
1323impl crate::Writable for HC6_TSIZ {}
1324#[doc = "Host Channel 0 Transfer Size Register"]
1325pub mod hc6_tsiz;
1326#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_dmaaddr](hc6_dmaaddr) module"]
1327pub type HC6_DMAADDR = crate::Reg<u32, _HC6_DMAADDR>;
1328#[allow(missing_docs)]
1329#[doc(hidden)]
1330pub struct _HC6_DMAADDR;
1331#[doc = "`read()` method returns [hc6_dmaaddr::R](hc6_dmaaddr::R) reader structure"]
1332impl crate::Readable for HC6_DMAADDR {}
1333#[doc = "`write(|w| ..)` method takes [hc6_dmaaddr::W](hc6_dmaaddr::W) writer structure"]
1334impl crate::Writable for HC6_DMAADDR {}
1335#[doc = "Host Channel 0 DMA Address Register"]
1336pub mod hc6_dmaaddr;
1337#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_char](hc7_char) module"]
1338pub type HC7_CHAR = crate::Reg<u32, _HC7_CHAR>;
1339#[allow(missing_docs)]
1340#[doc(hidden)]
1341pub struct _HC7_CHAR;
1342#[doc = "`read()` method returns [hc7_char::R](hc7_char::R) reader structure"]
1343impl crate::Readable for HC7_CHAR {}
1344#[doc = "`write(|w| ..)` method takes [hc7_char::W](hc7_char::W) writer structure"]
1345impl crate::Writable for HC7_CHAR {}
1346#[doc = "Host Channel 0 Characteristics Register"]
1347pub mod hc7_char;
1348#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_splt](hc7_splt) module"]
1349pub type HC7_SPLT = crate::Reg<u32, _HC7_SPLT>;
1350#[allow(missing_docs)]
1351#[doc(hidden)]
1352pub struct _HC7_SPLT;
1353#[doc = "`read()` method returns [hc7_splt::R](hc7_splt::R) reader structure"]
1354impl crate::Readable for HC7_SPLT {}
1355#[doc = "`write(|w| ..)` method takes [hc7_splt::W](hc7_splt::W) writer structure"]
1356impl crate::Writable for HC7_SPLT {}
1357#[doc = "Host Channel 0 Split Control Register"]
1358pub mod hc7_splt;
1359#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_int](hc7_int) module"]
1360pub type HC7_INT = crate::Reg<u32, _HC7_INT>;
1361#[allow(missing_docs)]
1362#[doc(hidden)]
1363pub struct _HC7_INT;
1364#[doc = "`read()` method returns [hc7_int::R](hc7_int::R) reader structure"]
1365impl crate::Readable for HC7_INT {}
1366#[doc = "`write(|w| ..)` method takes [hc7_int::W](hc7_int::W) writer structure"]
1367impl crate::Writable for HC7_INT {}
1368#[doc = "Host Channel 0 Interrupt Register"]
1369pub mod hc7_int;
1370#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_intmsk](hc7_intmsk) module"]
1371pub type HC7_INTMSK = crate::Reg<u32, _HC7_INTMSK>;
1372#[allow(missing_docs)]
1373#[doc(hidden)]
1374pub struct _HC7_INTMSK;
1375#[doc = "`read()` method returns [hc7_intmsk::R](hc7_intmsk::R) reader structure"]
1376impl crate::Readable for HC7_INTMSK {}
1377#[doc = "`write(|w| ..)` method takes [hc7_intmsk::W](hc7_intmsk::W) writer structure"]
1378impl crate::Writable for HC7_INTMSK {}
1379#[doc = "Host Channel 0 Interrupt Mask Register"]
1380pub mod hc7_intmsk;
1381#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_tsiz](hc7_tsiz) module"]
1382pub type HC7_TSIZ = crate::Reg<u32, _HC7_TSIZ>;
1383#[allow(missing_docs)]
1384#[doc(hidden)]
1385pub struct _HC7_TSIZ;
1386#[doc = "`read()` method returns [hc7_tsiz::R](hc7_tsiz::R) reader structure"]
1387impl crate::Readable for HC7_TSIZ {}
1388#[doc = "`write(|w| ..)` method takes [hc7_tsiz::W](hc7_tsiz::W) writer structure"]
1389impl crate::Writable for HC7_TSIZ {}
1390#[doc = "Host Channel 0 Transfer Size Register"]
1391pub mod hc7_tsiz;
1392#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc7_dmaaddr](hc7_dmaaddr) module"]
1393pub type HC7_DMAADDR = crate::Reg<u32, _HC7_DMAADDR>;
1394#[allow(missing_docs)]
1395#[doc(hidden)]
1396pub struct _HC7_DMAADDR;
1397#[doc = "`read()` method returns [hc7_dmaaddr::R](hc7_dmaaddr::R) reader structure"]
1398impl crate::Readable for HC7_DMAADDR {}
1399#[doc = "`write(|w| ..)` method takes [hc7_dmaaddr::W](hc7_dmaaddr::W) writer structure"]
1400impl crate::Writable for HC7_DMAADDR {}
1401#[doc = "Host Channel 0 DMA Address Register"]
1402pub mod hc7_dmaaddr;
1403#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_char](hc8_char) module"]
1404pub type HC8_CHAR = crate::Reg<u32, _HC8_CHAR>;
1405#[allow(missing_docs)]
1406#[doc(hidden)]
1407pub struct _HC8_CHAR;
1408#[doc = "`read()` method returns [hc8_char::R](hc8_char::R) reader structure"]
1409impl crate::Readable for HC8_CHAR {}
1410#[doc = "`write(|w| ..)` method takes [hc8_char::W](hc8_char::W) writer structure"]
1411impl crate::Writable for HC8_CHAR {}
1412#[doc = "Host Channel 0 Characteristics Register"]
1413pub mod hc8_char;
1414#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_splt](hc8_splt) module"]
1415pub type HC8_SPLT = crate::Reg<u32, _HC8_SPLT>;
1416#[allow(missing_docs)]
1417#[doc(hidden)]
1418pub struct _HC8_SPLT;
1419#[doc = "`read()` method returns [hc8_splt::R](hc8_splt::R) reader structure"]
1420impl crate::Readable for HC8_SPLT {}
1421#[doc = "`write(|w| ..)` method takes [hc8_splt::W](hc8_splt::W) writer structure"]
1422impl crate::Writable for HC8_SPLT {}
1423#[doc = "Host Channel 0 Split Control Register"]
1424pub mod hc8_splt;
1425#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_int](hc8_int) module"]
1426pub type HC8_INT = crate::Reg<u32, _HC8_INT>;
1427#[allow(missing_docs)]
1428#[doc(hidden)]
1429pub struct _HC8_INT;
1430#[doc = "`read()` method returns [hc8_int::R](hc8_int::R) reader structure"]
1431impl crate::Readable for HC8_INT {}
1432#[doc = "`write(|w| ..)` method takes [hc8_int::W](hc8_int::W) writer structure"]
1433impl crate::Writable for HC8_INT {}
1434#[doc = "Host Channel 0 Interrupt Register"]
1435pub mod hc8_int;
1436#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_intmsk](hc8_intmsk) module"]
1437pub type HC8_INTMSK = crate::Reg<u32, _HC8_INTMSK>;
1438#[allow(missing_docs)]
1439#[doc(hidden)]
1440pub struct _HC8_INTMSK;
1441#[doc = "`read()` method returns [hc8_intmsk::R](hc8_intmsk::R) reader structure"]
1442impl crate::Readable for HC8_INTMSK {}
1443#[doc = "`write(|w| ..)` method takes [hc8_intmsk::W](hc8_intmsk::W) writer structure"]
1444impl crate::Writable for HC8_INTMSK {}
1445#[doc = "Host Channel 0 Interrupt Mask Register"]
1446pub mod hc8_intmsk;
1447#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_tsiz](hc8_tsiz) module"]
1448pub type HC8_TSIZ = crate::Reg<u32, _HC8_TSIZ>;
1449#[allow(missing_docs)]
1450#[doc(hidden)]
1451pub struct _HC8_TSIZ;
1452#[doc = "`read()` method returns [hc8_tsiz::R](hc8_tsiz::R) reader structure"]
1453impl crate::Readable for HC8_TSIZ {}
1454#[doc = "`write(|w| ..)` method takes [hc8_tsiz::W](hc8_tsiz::W) writer structure"]
1455impl crate::Writable for HC8_TSIZ {}
1456#[doc = "Host Channel 0 Transfer Size Register"]
1457pub mod hc8_tsiz;
1458#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_dmaaddr](hc8_dmaaddr) module"]
1459pub type HC8_DMAADDR = crate::Reg<u32, _HC8_DMAADDR>;
1460#[allow(missing_docs)]
1461#[doc(hidden)]
1462pub struct _HC8_DMAADDR;
1463#[doc = "`read()` method returns [hc8_dmaaddr::R](hc8_dmaaddr::R) reader structure"]
1464impl crate::Readable for HC8_DMAADDR {}
1465#[doc = "`write(|w| ..)` method takes [hc8_dmaaddr::W](hc8_dmaaddr::W) writer structure"]
1466impl crate::Writable for HC8_DMAADDR {}
1467#[doc = "Host Channel 0 DMA Address Register"]
1468pub mod hc8_dmaaddr;
1469#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_char](hc9_char) module"]
1470pub type HC9_CHAR = crate::Reg<u32, _HC9_CHAR>;
1471#[allow(missing_docs)]
1472#[doc(hidden)]
1473pub struct _HC9_CHAR;
1474#[doc = "`read()` method returns [hc9_char::R](hc9_char::R) reader structure"]
1475impl crate::Readable for HC9_CHAR {}
1476#[doc = "`write(|w| ..)` method takes [hc9_char::W](hc9_char::W) writer structure"]
1477impl crate::Writable for HC9_CHAR {}
1478#[doc = "Host Channel 0 Characteristics Register"]
1479pub mod hc9_char;
1480#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_splt](hc9_splt) module"]
1481pub type HC9_SPLT = crate::Reg<u32, _HC9_SPLT>;
1482#[allow(missing_docs)]
1483#[doc(hidden)]
1484pub struct _HC9_SPLT;
1485#[doc = "`read()` method returns [hc9_splt::R](hc9_splt::R) reader structure"]
1486impl crate::Readable for HC9_SPLT {}
1487#[doc = "`write(|w| ..)` method takes [hc9_splt::W](hc9_splt::W) writer structure"]
1488impl crate::Writable for HC9_SPLT {}
1489#[doc = "Host Channel 0 Split Control Register"]
1490pub mod hc9_splt;
1491#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_int](hc9_int) module"]
1492pub type HC9_INT = crate::Reg<u32, _HC9_INT>;
1493#[allow(missing_docs)]
1494#[doc(hidden)]
1495pub struct _HC9_INT;
1496#[doc = "`read()` method returns [hc9_int::R](hc9_int::R) reader structure"]
1497impl crate::Readable for HC9_INT {}
1498#[doc = "`write(|w| ..)` method takes [hc9_int::W](hc9_int::W) writer structure"]
1499impl crate::Writable for HC9_INT {}
1500#[doc = "Host Channel 0 Interrupt Register"]
1501pub mod hc9_int;
1502#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_intmsk](hc9_intmsk) module"]
1503pub type HC9_INTMSK = crate::Reg<u32, _HC9_INTMSK>;
1504#[allow(missing_docs)]
1505#[doc(hidden)]
1506pub struct _HC9_INTMSK;
1507#[doc = "`read()` method returns [hc9_intmsk::R](hc9_intmsk::R) reader structure"]
1508impl crate::Readable for HC9_INTMSK {}
1509#[doc = "`write(|w| ..)` method takes [hc9_intmsk::W](hc9_intmsk::W) writer structure"]
1510impl crate::Writable for HC9_INTMSK {}
1511#[doc = "Host Channel 0 Interrupt Mask Register"]
1512pub mod hc9_intmsk;
1513#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_tsiz](hc9_tsiz) module"]
1514pub type HC9_TSIZ = crate::Reg<u32, _HC9_TSIZ>;
1515#[allow(missing_docs)]
1516#[doc(hidden)]
1517pub struct _HC9_TSIZ;
1518#[doc = "`read()` method returns [hc9_tsiz::R](hc9_tsiz::R) reader structure"]
1519impl crate::Readable for HC9_TSIZ {}
1520#[doc = "`write(|w| ..)` method takes [hc9_tsiz::W](hc9_tsiz::W) writer structure"]
1521impl crate::Writable for HC9_TSIZ {}
1522#[doc = "Host Channel 0 Transfer Size Register"]
1523pub mod hc9_tsiz;
1524#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc9_dmaaddr](hc9_dmaaddr) module"]
1525pub type HC9_DMAADDR = crate::Reg<u32, _HC9_DMAADDR>;
1526#[allow(missing_docs)]
1527#[doc(hidden)]
1528pub struct _HC9_DMAADDR;
1529#[doc = "`read()` method returns [hc9_dmaaddr::R](hc9_dmaaddr::R) reader structure"]
1530impl crate::Readable for HC9_DMAADDR {}
1531#[doc = "`write(|w| ..)` method takes [hc9_dmaaddr::W](hc9_dmaaddr::W) writer structure"]
1532impl crate::Writable for HC9_DMAADDR {}
1533#[doc = "Host Channel 0 DMA Address Register"]
1534pub mod hc9_dmaaddr;
1535#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_char](hc10_char) module"]
1536pub type HC10_CHAR = crate::Reg<u32, _HC10_CHAR>;
1537#[allow(missing_docs)]
1538#[doc(hidden)]
1539pub struct _HC10_CHAR;
1540#[doc = "`read()` method returns [hc10_char::R](hc10_char::R) reader structure"]
1541impl crate::Readable for HC10_CHAR {}
1542#[doc = "`write(|w| ..)` method takes [hc10_char::W](hc10_char::W) writer structure"]
1543impl crate::Writable for HC10_CHAR {}
1544#[doc = "Host Channel 0 Characteristics Register"]
1545pub mod hc10_char;
1546#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_splt](hc10_splt) module"]
1547pub type HC10_SPLT = crate::Reg<u32, _HC10_SPLT>;
1548#[allow(missing_docs)]
1549#[doc(hidden)]
1550pub struct _HC10_SPLT;
1551#[doc = "`read()` method returns [hc10_splt::R](hc10_splt::R) reader structure"]
1552impl crate::Readable for HC10_SPLT {}
1553#[doc = "`write(|w| ..)` method takes [hc10_splt::W](hc10_splt::W) writer structure"]
1554impl crate::Writable for HC10_SPLT {}
1555#[doc = "Host Channel 0 Split Control Register"]
1556pub mod hc10_splt;
1557#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_int](hc10_int) module"]
1558pub type HC10_INT = crate::Reg<u32, _HC10_INT>;
1559#[allow(missing_docs)]
1560#[doc(hidden)]
1561pub struct _HC10_INT;
1562#[doc = "`read()` method returns [hc10_int::R](hc10_int::R) reader structure"]
1563impl crate::Readable for HC10_INT {}
1564#[doc = "`write(|w| ..)` method takes [hc10_int::W](hc10_int::W) writer structure"]
1565impl crate::Writable for HC10_INT {}
1566#[doc = "Host Channel 0 Interrupt Register"]
1567pub mod hc10_int;
1568#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_intmsk](hc10_intmsk) module"]
1569pub type HC10_INTMSK = crate::Reg<u32, _HC10_INTMSK>;
1570#[allow(missing_docs)]
1571#[doc(hidden)]
1572pub struct _HC10_INTMSK;
1573#[doc = "`read()` method returns [hc10_intmsk::R](hc10_intmsk::R) reader structure"]
1574impl crate::Readable for HC10_INTMSK {}
1575#[doc = "`write(|w| ..)` method takes [hc10_intmsk::W](hc10_intmsk::W) writer structure"]
1576impl crate::Writable for HC10_INTMSK {}
1577#[doc = "Host Channel 0 Interrupt Mask Register"]
1578pub mod hc10_intmsk;
1579#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_tsiz](hc10_tsiz) module"]
1580pub type HC10_TSIZ = crate::Reg<u32, _HC10_TSIZ>;
1581#[allow(missing_docs)]
1582#[doc(hidden)]
1583pub struct _HC10_TSIZ;
1584#[doc = "`read()` method returns [hc10_tsiz::R](hc10_tsiz::R) reader structure"]
1585impl crate::Readable for HC10_TSIZ {}
1586#[doc = "`write(|w| ..)` method takes [hc10_tsiz::W](hc10_tsiz::W) writer structure"]
1587impl crate::Writable for HC10_TSIZ {}
1588#[doc = "Host Channel 0 Transfer Size Register"]
1589pub mod hc10_tsiz;
1590#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc10_dmaaddr](hc10_dmaaddr) module"]
1591pub type HC10_DMAADDR = crate::Reg<u32, _HC10_DMAADDR>;
1592#[allow(missing_docs)]
1593#[doc(hidden)]
1594pub struct _HC10_DMAADDR;
1595#[doc = "`read()` method returns [hc10_dmaaddr::R](hc10_dmaaddr::R) reader structure"]
1596impl crate::Readable for HC10_DMAADDR {}
1597#[doc = "`write(|w| ..)` method takes [hc10_dmaaddr::W](hc10_dmaaddr::W) writer structure"]
1598impl crate::Writable for HC10_DMAADDR {}
1599#[doc = "Host Channel 0 DMA Address Register"]
1600pub mod hc10_dmaaddr;
1601#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_char](hc11_char) module"]
1602pub type HC11_CHAR = crate::Reg<u32, _HC11_CHAR>;
1603#[allow(missing_docs)]
1604#[doc(hidden)]
1605pub struct _HC11_CHAR;
1606#[doc = "`read()` method returns [hc11_char::R](hc11_char::R) reader structure"]
1607impl crate::Readable for HC11_CHAR {}
1608#[doc = "`write(|w| ..)` method takes [hc11_char::W](hc11_char::W) writer structure"]
1609impl crate::Writable for HC11_CHAR {}
1610#[doc = "Host Channel 0 Characteristics Register"]
1611pub mod hc11_char;
1612#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_splt](hc11_splt) module"]
1613pub type HC11_SPLT = crate::Reg<u32, _HC11_SPLT>;
1614#[allow(missing_docs)]
1615#[doc(hidden)]
1616pub struct _HC11_SPLT;
1617#[doc = "`read()` method returns [hc11_splt::R](hc11_splt::R) reader structure"]
1618impl crate::Readable for HC11_SPLT {}
1619#[doc = "`write(|w| ..)` method takes [hc11_splt::W](hc11_splt::W) writer structure"]
1620impl crate::Writable for HC11_SPLT {}
1621#[doc = "Host Channel 0 Split Control Register"]
1622pub mod hc11_splt;
1623#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_int](hc11_int) module"]
1624pub type HC11_INT = crate::Reg<u32, _HC11_INT>;
1625#[allow(missing_docs)]
1626#[doc(hidden)]
1627pub struct _HC11_INT;
1628#[doc = "`read()` method returns [hc11_int::R](hc11_int::R) reader structure"]
1629impl crate::Readable for HC11_INT {}
1630#[doc = "`write(|w| ..)` method takes [hc11_int::W](hc11_int::W) writer structure"]
1631impl crate::Writable for HC11_INT {}
1632#[doc = "Host Channel 0 Interrupt Register"]
1633pub mod hc11_int;
1634#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_intmsk](hc11_intmsk) module"]
1635pub type HC11_INTMSK = crate::Reg<u32, _HC11_INTMSK>;
1636#[allow(missing_docs)]
1637#[doc(hidden)]
1638pub struct _HC11_INTMSK;
1639#[doc = "`read()` method returns [hc11_intmsk::R](hc11_intmsk::R) reader structure"]
1640impl crate::Readable for HC11_INTMSK {}
1641#[doc = "`write(|w| ..)` method takes [hc11_intmsk::W](hc11_intmsk::W) writer structure"]
1642impl crate::Writable for HC11_INTMSK {}
1643#[doc = "Host Channel 0 Interrupt Mask Register"]
1644pub mod hc11_intmsk;
1645#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_tsiz](hc11_tsiz) module"]
1646pub type HC11_TSIZ = crate::Reg<u32, _HC11_TSIZ>;
1647#[allow(missing_docs)]
1648#[doc(hidden)]
1649pub struct _HC11_TSIZ;
1650#[doc = "`read()` method returns [hc11_tsiz::R](hc11_tsiz::R) reader structure"]
1651impl crate::Readable for HC11_TSIZ {}
1652#[doc = "`write(|w| ..)` method takes [hc11_tsiz::W](hc11_tsiz::W) writer structure"]
1653impl crate::Writable for HC11_TSIZ {}
1654#[doc = "Host Channel 0 Transfer Size Register"]
1655pub mod hc11_tsiz;
1656#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc11_dmaaddr](hc11_dmaaddr) module"]
1657pub type HC11_DMAADDR = crate::Reg<u32, _HC11_DMAADDR>;
1658#[allow(missing_docs)]
1659#[doc(hidden)]
1660pub struct _HC11_DMAADDR;
1661#[doc = "`read()` method returns [hc11_dmaaddr::R](hc11_dmaaddr::R) reader structure"]
1662impl crate::Readable for HC11_DMAADDR {}
1663#[doc = "`write(|w| ..)` method takes [hc11_dmaaddr::W](hc11_dmaaddr::W) writer structure"]
1664impl crate::Writable for HC11_DMAADDR {}
1665#[doc = "Host Channel 0 DMA Address Register"]
1666pub mod hc11_dmaaddr;
1667#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_char](hc12_char) module"]
1668pub type HC12_CHAR = crate::Reg<u32, _HC12_CHAR>;
1669#[allow(missing_docs)]
1670#[doc(hidden)]
1671pub struct _HC12_CHAR;
1672#[doc = "`read()` method returns [hc12_char::R](hc12_char::R) reader structure"]
1673impl crate::Readable for HC12_CHAR {}
1674#[doc = "`write(|w| ..)` method takes [hc12_char::W](hc12_char::W) writer structure"]
1675impl crate::Writable for HC12_CHAR {}
1676#[doc = "Host Channel 0 Characteristics Register"]
1677pub mod hc12_char;
1678#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_splt](hc12_splt) module"]
1679pub type HC12_SPLT = crate::Reg<u32, _HC12_SPLT>;
1680#[allow(missing_docs)]
1681#[doc(hidden)]
1682pub struct _HC12_SPLT;
1683#[doc = "`read()` method returns [hc12_splt::R](hc12_splt::R) reader structure"]
1684impl crate::Readable for HC12_SPLT {}
1685#[doc = "`write(|w| ..)` method takes [hc12_splt::W](hc12_splt::W) writer structure"]
1686impl crate::Writable for HC12_SPLT {}
1687#[doc = "Host Channel 0 Split Control Register"]
1688pub mod hc12_splt;
1689#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_int](hc12_int) module"]
1690pub type HC12_INT = crate::Reg<u32, _HC12_INT>;
1691#[allow(missing_docs)]
1692#[doc(hidden)]
1693pub struct _HC12_INT;
1694#[doc = "`read()` method returns [hc12_int::R](hc12_int::R) reader structure"]
1695impl crate::Readable for HC12_INT {}
1696#[doc = "`write(|w| ..)` method takes [hc12_int::W](hc12_int::W) writer structure"]
1697impl crate::Writable for HC12_INT {}
1698#[doc = "Host Channel 0 Interrupt Register"]
1699pub mod hc12_int;
1700#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_intmsk](hc12_intmsk) module"]
1701pub type HC12_INTMSK = crate::Reg<u32, _HC12_INTMSK>;
1702#[allow(missing_docs)]
1703#[doc(hidden)]
1704pub struct _HC12_INTMSK;
1705#[doc = "`read()` method returns [hc12_intmsk::R](hc12_intmsk::R) reader structure"]
1706impl crate::Readable for HC12_INTMSK {}
1707#[doc = "`write(|w| ..)` method takes [hc12_intmsk::W](hc12_intmsk::W) writer structure"]
1708impl crate::Writable for HC12_INTMSK {}
1709#[doc = "Host Channel 0 Interrupt Mask Register"]
1710pub mod hc12_intmsk;
1711#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_tsiz](hc12_tsiz) module"]
1712pub type HC12_TSIZ = crate::Reg<u32, _HC12_TSIZ>;
1713#[allow(missing_docs)]
1714#[doc(hidden)]
1715pub struct _HC12_TSIZ;
1716#[doc = "`read()` method returns [hc12_tsiz::R](hc12_tsiz::R) reader structure"]
1717impl crate::Readable for HC12_TSIZ {}
1718#[doc = "`write(|w| ..)` method takes [hc12_tsiz::W](hc12_tsiz::W) writer structure"]
1719impl crate::Writable for HC12_TSIZ {}
1720#[doc = "Host Channel 0 Transfer Size Register"]
1721pub mod hc12_tsiz;
1722#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_dmaaddr](hc12_dmaaddr) module"]
1723pub type HC12_DMAADDR = crate::Reg<u32, _HC12_DMAADDR>;
1724#[allow(missing_docs)]
1725#[doc(hidden)]
1726pub struct _HC12_DMAADDR;
1727#[doc = "`read()` method returns [hc12_dmaaddr::R](hc12_dmaaddr::R) reader structure"]
1728impl crate::Readable for HC12_DMAADDR {}
1729#[doc = "`write(|w| ..)` method takes [hc12_dmaaddr::W](hc12_dmaaddr::W) writer structure"]
1730impl crate::Writable for HC12_DMAADDR {}
1731#[doc = "Host Channel 0 DMA Address Register"]
1732pub mod hc12_dmaaddr;
1733#[doc = "Host Channel 0 Characteristics Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_char](hc13_char) module"]
1734pub type HC13_CHAR = crate::Reg<u32, _HC13_CHAR>;
1735#[allow(missing_docs)]
1736#[doc(hidden)]
1737pub struct _HC13_CHAR;
1738#[doc = "`read()` method returns [hc13_char::R](hc13_char::R) reader structure"]
1739impl crate::Readable for HC13_CHAR {}
1740#[doc = "`write(|w| ..)` method takes [hc13_char::W](hc13_char::W) writer structure"]
1741impl crate::Writable for HC13_CHAR {}
1742#[doc = "Host Channel 0 Characteristics Register"]
1743pub mod hc13_char;
1744#[doc = "Host Channel 0 Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_splt](hc13_splt) module"]
1745pub type HC13_SPLT = crate::Reg<u32, _HC13_SPLT>;
1746#[allow(missing_docs)]
1747#[doc(hidden)]
1748pub struct _HC13_SPLT;
1749#[doc = "`read()` method returns [hc13_splt::R](hc13_splt::R) reader structure"]
1750impl crate::Readable for HC13_SPLT {}
1751#[doc = "`write(|w| ..)` method takes [hc13_splt::W](hc13_splt::W) writer structure"]
1752impl crate::Writable for HC13_SPLT {}
1753#[doc = "Host Channel 0 Split Control Register"]
1754pub mod hc13_splt;
1755#[doc = "Host Channel 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_int](hc13_int) module"]
1756pub type HC13_INT = crate::Reg<u32, _HC13_INT>;
1757#[allow(missing_docs)]
1758#[doc(hidden)]
1759pub struct _HC13_INT;
1760#[doc = "`read()` method returns [hc13_int::R](hc13_int::R) reader structure"]
1761impl crate::Readable for HC13_INT {}
1762#[doc = "`write(|w| ..)` method takes [hc13_int::W](hc13_int::W) writer structure"]
1763impl crate::Writable for HC13_INT {}
1764#[doc = "Host Channel 0 Interrupt Register"]
1765pub mod hc13_int;
1766#[doc = "Host Channel 0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_intmsk](hc13_intmsk) module"]
1767pub type HC13_INTMSK = crate::Reg<u32, _HC13_INTMSK>;
1768#[allow(missing_docs)]
1769#[doc(hidden)]
1770pub struct _HC13_INTMSK;
1771#[doc = "`read()` method returns [hc13_intmsk::R](hc13_intmsk::R) reader structure"]
1772impl crate::Readable for HC13_INTMSK {}
1773#[doc = "`write(|w| ..)` method takes [hc13_intmsk::W](hc13_intmsk::W) writer structure"]
1774impl crate::Writable for HC13_INTMSK {}
1775#[doc = "Host Channel 0 Interrupt Mask Register"]
1776pub mod hc13_intmsk;
1777#[doc = "Host Channel 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_tsiz](hc13_tsiz) module"]
1778pub type HC13_TSIZ = crate::Reg<u32, _HC13_TSIZ>;
1779#[allow(missing_docs)]
1780#[doc(hidden)]
1781pub struct _HC13_TSIZ;
1782#[doc = "`read()` method returns [hc13_tsiz::R](hc13_tsiz::R) reader structure"]
1783impl crate::Readable for HC13_TSIZ {}
1784#[doc = "`write(|w| ..)` method takes [hc13_tsiz::W](hc13_tsiz::W) writer structure"]
1785impl crate::Writable for HC13_TSIZ {}
1786#[doc = "Host Channel 0 Transfer Size Register"]
1787pub mod hc13_tsiz;
1788#[doc = "Host Channel 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc13_dmaaddr](hc13_dmaaddr) module"]
1789pub type HC13_DMAADDR = crate::Reg<u32, _HC13_DMAADDR>;
1790#[allow(missing_docs)]
1791#[doc(hidden)]
1792pub struct _HC13_DMAADDR;
1793#[doc = "`read()` method returns [hc13_dmaaddr::R](hc13_dmaaddr::R) reader structure"]
1794impl crate::Readable for HC13_DMAADDR {}
1795#[doc = "`write(|w| ..)` method takes [hc13_dmaaddr::W](hc13_dmaaddr::W) writer structure"]
1796impl crate::Writable for HC13_DMAADDR {}
1797#[doc = "Host Channel 0 DMA Address Register"]
1798pub mod hc13_dmaaddr;
1799#[doc = "Device Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](dcfg) module"]
1800pub type DCFG = crate::Reg<u32, _DCFG>;
1801#[allow(missing_docs)]
1802#[doc(hidden)]
1803pub struct _DCFG;
1804#[doc = "`read()` method returns [dcfg::R](dcfg::R) reader structure"]
1805impl crate::Readable for DCFG {}
1806#[doc = "`write(|w| ..)` method takes [dcfg::W](dcfg::W) writer structure"]
1807impl crate::Writable for DCFG {}
1808#[doc = "Device Configuration Register"]
1809pub mod dcfg;
1810#[doc = "Device Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dctl](dctl) module"]
1811pub type DCTL = crate::Reg<u32, _DCTL>;
1812#[allow(missing_docs)]
1813#[doc(hidden)]
1814pub struct _DCTL;
1815#[doc = "`read()` method returns [dctl::R](dctl::R) reader structure"]
1816impl crate::Readable for DCTL {}
1817#[doc = "`write(|w| ..)` method takes [dctl::W](dctl::W) writer structure"]
1818impl crate::Writable for DCTL {}
1819#[doc = "Device Control Register"]
1820pub mod dctl;
1821#[doc = "Device Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dsts](dsts) module"]
1822pub type DSTS = crate::Reg<u32, _DSTS>;
1823#[allow(missing_docs)]
1824#[doc(hidden)]
1825pub struct _DSTS;
1826#[doc = "`read()` method returns [dsts::R](dsts::R) reader structure"]
1827impl crate::Readable for DSTS {}
1828#[doc = "Device Status Register"]
1829pub mod dsts;
1830#[doc = "Device IN Endpoint Common Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepmsk](diepmsk) module"]
1831pub type DIEPMSK = crate::Reg<u32, _DIEPMSK>;
1832#[allow(missing_docs)]
1833#[doc(hidden)]
1834pub struct _DIEPMSK;
1835#[doc = "`read()` method returns [diepmsk::R](diepmsk::R) reader structure"]
1836impl crate::Readable for DIEPMSK {}
1837#[doc = "`write(|w| ..)` method takes [diepmsk::W](diepmsk::W) writer structure"]
1838impl crate::Writable for DIEPMSK {}
1839#[doc = "Device IN Endpoint Common Interrupt Mask Register"]
1840pub mod diepmsk;
1841#[doc = "Device OUT Endpoint Common Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doepmsk](doepmsk) module"]
1842pub type DOEPMSK = crate::Reg<u32, _DOEPMSK>;
1843#[allow(missing_docs)]
1844#[doc(hidden)]
1845pub struct _DOEPMSK;
1846#[doc = "`read()` method returns [doepmsk::R](doepmsk::R) reader structure"]
1847impl crate::Readable for DOEPMSK {}
1848#[doc = "`write(|w| ..)` method takes [doepmsk::W](doepmsk::W) writer structure"]
1849impl crate::Writable for DOEPMSK {}
1850#[doc = "Device OUT Endpoint Common Interrupt Mask Register"]
1851pub mod doepmsk;
1852#[doc = "Device All Endpoints Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daint](daint) module"]
1853pub type DAINT = crate::Reg<u32, _DAINT>;
1854#[allow(missing_docs)]
1855#[doc(hidden)]
1856pub struct _DAINT;
1857#[doc = "`read()` method returns [daint::R](daint::R) reader structure"]
1858impl crate::Readable for DAINT {}
1859#[doc = "Device All Endpoints Interrupt Register"]
1860pub mod daint;
1861#[doc = "Device All Endpoints Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daintmsk](daintmsk) module"]
1862pub type DAINTMSK = crate::Reg<u32, _DAINTMSK>;
1863#[allow(missing_docs)]
1864#[doc(hidden)]
1865pub struct _DAINTMSK;
1866#[doc = "`read()` method returns [daintmsk::R](daintmsk::R) reader structure"]
1867impl crate::Readable for DAINTMSK {}
1868#[doc = "`write(|w| ..)` method takes [daintmsk::W](daintmsk::W) writer structure"]
1869impl crate::Writable for DAINTMSK {}
1870#[doc = "Device All Endpoints Interrupt Mask Register"]
1871pub mod daintmsk;
1872#[doc = "Device VBUS Discharge Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbusdis](dvbusdis) module"]
1873pub type DVBUSDIS = crate::Reg<u32, _DVBUSDIS>;
1874#[allow(missing_docs)]
1875#[doc(hidden)]
1876pub struct _DVBUSDIS;
1877#[doc = "`read()` method returns [dvbusdis::R](dvbusdis::R) reader structure"]
1878impl crate::Readable for DVBUSDIS {}
1879#[doc = "`write(|w| ..)` method takes [dvbusdis::W](dvbusdis::W) writer structure"]
1880impl crate::Writable for DVBUSDIS {}
1881#[doc = "Device VBUS Discharge Time Register"]
1882pub mod dvbusdis;
1883#[doc = "Device VBUS Pulsing Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvbuspulse](dvbuspulse) module"]
1884pub type DVBUSPULSE = crate::Reg<u32, _DVBUSPULSE>;
1885#[allow(missing_docs)]
1886#[doc(hidden)]
1887pub struct _DVBUSPULSE;
1888#[doc = "`read()` method returns [dvbuspulse::R](dvbuspulse::R) reader structure"]
1889impl crate::Readable for DVBUSPULSE {}
1890#[doc = "`write(|w| ..)` method takes [dvbuspulse::W](dvbuspulse::W) writer structure"]
1891impl crate::Writable for DVBUSPULSE {}
1892#[doc = "Device VBUS Pulsing Time Register"]
1893pub mod dvbuspulse;
1894#[doc = "Device Threshold Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dthrctl](dthrctl) module"]
1895pub type DTHRCTL = crate::Reg<u32, _DTHRCTL>;
1896#[allow(missing_docs)]
1897#[doc(hidden)]
1898pub struct _DTHRCTL;
1899#[doc = "`read()` method returns [dthrctl::R](dthrctl::R) reader structure"]
1900impl crate::Readable for DTHRCTL {}
1901#[doc = "`write(|w| ..)` method takes [dthrctl::W](dthrctl::W) writer structure"]
1902impl crate::Writable for DTHRCTL {}
1903#[doc = "Device Threshold Control Register"]
1904pub mod dthrctl;
1905#[doc = "Device IN Endpoint FIFO Empty Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diepempmsk](diepempmsk) module"]
1906pub type DIEPEMPMSK = crate::Reg<u32, _DIEPEMPMSK>;
1907#[allow(missing_docs)]
1908#[doc(hidden)]
1909pub struct _DIEPEMPMSK;
1910#[doc = "`read()` method returns [diepempmsk::R](diepempmsk::R) reader structure"]
1911impl crate::Readable for DIEPEMPMSK {}
1912#[doc = "`write(|w| ..)` method takes [diepempmsk::W](diepempmsk::W) writer structure"]
1913impl crate::Writable for DIEPEMPMSK {}
1914#[doc = "Device IN Endpoint FIFO Empty Interrupt Mask Register"]
1915pub mod diepempmsk;
1916#[doc = "Device Control IN Endpoint 0 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0ctl](diep0ctl) module"]
1917pub type DIEP0CTL = crate::Reg<u32, _DIEP0CTL>;
1918#[allow(missing_docs)]
1919#[doc(hidden)]
1920pub struct _DIEP0CTL;
1921#[doc = "`read()` method returns [diep0ctl::R](diep0ctl::R) reader structure"]
1922impl crate::Readable for DIEP0CTL {}
1923#[doc = "`write(|w| ..)` method takes [diep0ctl::W](diep0ctl::W) writer structure"]
1924impl crate::Writable for DIEP0CTL {}
1925#[doc = "Device Control IN Endpoint 0 Control Register"]
1926pub mod diep0ctl;
1927#[doc = "Device IN Endpoint 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0int](diep0int) module"]
1928pub type DIEP0INT = crate::Reg<u32, _DIEP0INT>;
1929#[allow(missing_docs)]
1930#[doc(hidden)]
1931pub struct _DIEP0INT;
1932#[doc = "`read()` method returns [diep0int::R](diep0int::R) reader structure"]
1933impl crate::Readable for DIEP0INT {}
1934#[doc = "`write(|w| ..)` method takes [diep0int::W](diep0int::W) writer structure"]
1935impl crate::Writable for DIEP0INT {}
1936#[doc = "Device IN Endpoint 0 Interrupt Register"]
1937pub mod diep0int;
1938#[doc = "Device IN Endpoint 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0tsiz](diep0tsiz) module"]
1939pub type DIEP0TSIZ = crate::Reg<u32, _DIEP0TSIZ>;
1940#[allow(missing_docs)]
1941#[doc(hidden)]
1942pub struct _DIEP0TSIZ;
1943#[doc = "`read()` method returns [diep0tsiz::R](diep0tsiz::R) reader structure"]
1944impl crate::Readable for DIEP0TSIZ {}
1945#[doc = "`write(|w| ..)` method takes [diep0tsiz::W](diep0tsiz::W) writer structure"]
1946impl crate::Writable for DIEP0TSIZ {}
1947#[doc = "Device IN Endpoint 0 Transfer Size Register"]
1948pub mod diep0tsiz;
1949#[doc = "Device IN Endpoint 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0dmaaddr](diep0dmaaddr) module"]
1950pub type DIEP0DMAADDR = crate::Reg<u32, _DIEP0DMAADDR>;
1951#[allow(missing_docs)]
1952#[doc(hidden)]
1953pub struct _DIEP0DMAADDR;
1954#[doc = "`read()` method returns [diep0dmaaddr::R](diep0dmaaddr::R) reader structure"]
1955impl crate::Readable for DIEP0DMAADDR {}
1956#[doc = "`write(|w| ..)` method takes [diep0dmaaddr::W](diep0dmaaddr::W) writer structure"]
1957impl crate::Writable for DIEP0DMAADDR {}
1958#[doc = "Device IN Endpoint 0 DMA Address Register"]
1959pub mod diep0dmaaddr;
1960#[doc = "Device IN Endpoint Transmit FIFO Status Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0txfsts](diep0txfsts) module"]
1961pub type DIEP0TXFSTS = crate::Reg<u32, _DIEP0TXFSTS>;
1962#[allow(missing_docs)]
1963#[doc(hidden)]
1964pub struct _DIEP0TXFSTS;
1965#[doc = "`read()` method returns [diep0txfsts::R](diep0txfsts::R) reader structure"]
1966impl crate::Readable for DIEP0TXFSTS {}
1967#[doc = "Device IN Endpoint Transmit FIFO Status Register 0"]
1968pub mod diep0txfsts;
1969#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_ctl](diep0_ctl) module"]
1970pub type DIEP0_CTL = crate::Reg<u32, _DIEP0_CTL>;
1971#[allow(missing_docs)]
1972#[doc(hidden)]
1973pub struct _DIEP0_CTL;
1974#[doc = "`read()` method returns [diep0_ctl::R](diep0_ctl::R) reader structure"]
1975impl crate::Readable for DIEP0_CTL {}
1976#[doc = "`write(|w| ..)` method takes [diep0_ctl::W](diep0_ctl::W) writer structure"]
1977impl crate::Writable for DIEP0_CTL {}
1978#[doc = "Device Control IN Endpoint 1 Control Register"]
1979pub mod diep0_ctl;
1980#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_int](diep0_int) module"]
1981pub type DIEP0_INT = crate::Reg<u32, _DIEP0_INT>;
1982#[allow(missing_docs)]
1983#[doc(hidden)]
1984pub struct _DIEP0_INT;
1985#[doc = "`read()` method returns [diep0_int::R](diep0_int::R) reader structure"]
1986impl crate::Readable for DIEP0_INT {}
1987#[doc = "`write(|w| ..)` method takes [diep0_int::W](diep0_int::W) writer structure"]
1988impl crate::Writable for DIEP0_INT {}
1989#[doc = "Device IN Endpoint 1 Interrupt Register"]
1990pub mod diep0_int;
1991#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_tsiz](diep0_tsiz) module"]
1992pub type DIEP0_TSIZ = crate::Reg<u32, _DIEP0_TSIZ>;
1993#[allow(missing_docs)]
1994#[doc(hidden)]
1995pub struct _DIEP0_TSIZ;
1996#[doc = "`read()` method returns [diep0_tsiz::R](diep0_tsiz::R) reader structure"]
1997impl crate::Readable for DIEP0_TSIZ {}
1998#[doc = "`write(|w| ..)` method takes [diep0_tsiz::W](diep0_tsiz::W) writer structure"]
1999impl crate::Writable for DIEP0_TSIZ {}
2000#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2001pub mod diep0_tsiz;
2002#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_dmaaddr](diep0_dmaaddr) module"]
2003pub type DIEP0_DMAADDR = crate::Reg<u32, _DIEP0_DMAADDR>;
2004#[allow(missing_docs)]
2005#[doc(hidden)]
2006pub struct _DIEP0_DMAADDR;
2007#[doc = "`read()` method returns [diep0_dmaaddr::R](diep0_dmaaddr::R) reader structure"]
2008impl crate::Readable for DIEP0_DMAADDR {}
2009#[doc = "`write(|w| ..)` method takes [diep0_dmaaddr::W](diep0_dmaaddr::W) writer structure"]
2010impl crate::Writable for DIEP0_DMAADDR {}
2011#[doc = "Device IN Endpoint 1 DMA Address Register"]
2012pub mod diep0_dmaaddr;
2013#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_dtxfsts](diep0_dtxfsts) module"]
2014pub type DIEP0_DTXFSTS = crate::Reg<u32, _DIEP0_DTXFSTS>;
2015#[allow(missing_docs)]
2016#[doc(hidden)]
2017pub struct _DIEP0_DTXFSTS;
2018#[doc = "`read()` method returns [diep0_dtxfsts::R](diep0_dtxfsts::R) reader structure"]
2019impl crate::Readable for DIEP0_DTXFSTS {}
2020#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2021pub mod diep0_dtxfsts;
2022#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_ctl](diep1_ctl) module"]
2023pub type DIEP1_CTL = crate::Reg<u32, _DIEP1_CTL>;
2024#[allow(missing_docs)]
2025#[doc(hidden)]
2026pub struct _DIEP1_CTL;
2027#[doc = "`read()` method returns [diep1_ctl::R](diep1_ctl::R) reader structure"]
2028impl crate::Readable for DIEP1_CTL {}
2029#[doc = "`write(|w| ..)` method takes [diep1_ctl::W](diep1_ctl::W) writer structure"]
2030impl crate::Writable for DIEP1_CTL {}
2031#[doc = "Device Control IN Endpoint 1 Control Register"]
2032pub mod diep1_ctl;
2033#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_int](diep1_int) module"]
2034pub type DIEP1_INT = crate::Reg<u32, _DIEP1_INT>;
2035#[allow(missing_docs)]
2036#[doc(hidden)]
2037pub struct _DIEP1_INT;
2038#[doc = "`read()` method returns [diep1_int::R](diep1_int::R) reader structure"]
2039impl crate::Readable for DIEP1_INT {}
2040#[doc = "`write(|w| ..)` method takes [diep1_int::W](diep1_int::W) writer structure"]
2041impl crate::Writable for DIEP1_INT {}
2042#[doc = "Device IN Endpoint 1 Interrupt Register"]
2043pub mod diep1_int;
2044#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_tsiz](diep1_tsiz) module"]
2045pub type DIEP1_TSIZ = crate::Reg<u32, _DIEP1_TSIZ>;
2046#[allow(missing_docs)]
2047#[doc(hidden)]
2048pub struct _DIEP1_TSIZ;
2049#[doc = "`read()` method returns [diep1_tsiz::R](diep1_tsiz::R) reader structure"]
2050impl crate::Readable for DIEP1_TSIZ {}
2051#[doc = "`write(|w| ..)` method takes [diep1_tsiz::W](diep1_tsiz::W) writer structure"]
2052impl crate::Writable for DIEP1_TSIZ {}
2053#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2054pub mod diep1_tsiz;
2055#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_dmaaddr](diep1_dmaaddr) module"]
2056pub type DIEP1_DMAADDR = crate::Reg<u32, _DIEP1_DMAADDR>;
2057#[allow(missing_docs)]
2058#[doc(hidden)]
2059pub struct _DIEP1_DMAADDR;
2060#[doc = "`read()` method returns [diep1_dmaaddr::R](diep1_dmaaddr::R) reader structure"]
2061impl crate::Readable for DIEP1_DMAADDR {}
2062#[doc = "`write(|w| ..)` method takes [diep1_dmaaddr::W](diep1_dmaaddr::W) writer structure"]
2063impl crate::Writable for DIEP1_DMAADDR {}
2064#[doc = "Device IN Endpoint 1 DMA Address Register"]
2065pub mod diep1_dmaaddr;
2066#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep1_dtxfsts](diep1_dtxfsts) module"]
2067pub type DIEP1_DTXFSTS = crate::Reg<u32, _DIEP1_DTXFSTS>;
2068#[allow(missing_docs)]
2069#[doc(hidden)]
2070pub struct _DIEP1_DTXFSTS;
2071#[doc = "`read()` method returns [diep1_dtxfsts::R](diep1_dtxfsts::R) reader structure"]
2072impl crate::Readable for DIEP1_DTXFSTS {}
2073#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2074pub mod diep1_dtxfsts;
2075#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep2_ctl](diep2_ctl) module"]
2076pub type DIEP2_CTL = crate::Reg<u32, _DIEP2_CTL>;
2077#[allow(missing_docs)]
2078#[doc(hidden)]
2079pub struct _DIEP2_CTL;
2080#[doc = "`read()` method returns [diep2_ctl::R](diep2_ctl::R) reader structure"]
2081impl crate::Readable for DIEP2_CTL {}
2082#[doc = "`write(|w| ..)` method takes [diep2_ctl::W](diep2_ctl::W) writer structure"]
2083impl crate::Writable for DIEP2_CTL {}
2084#[doc = "Device Control IN Endpoint 1 Control Register"]
2085pub mod diep2_ctl;
2086#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep2_int](diep2_int) module"]
2087pub type DIEP2_INT = crate::Reg<u32, _DIEP2_INT>;
2088#[allow(missing_docs)]
2089#[doc(hidden)]
2090pub struct _DIEP2_INT;
2091#[doc = "`read()` method returns [diep2_int::R](diep2_int::R) reader structure"]
2092impl crate::Readable for DIEP2_INT {}
2093#[doc = "`write(|w| ..)` method takes [diep2_int::W](diep2_int::W) writer structure"]
2094impl crate::Writable for DIEP2_INT {}
2095#[doc = "Device IN Endpoint 1 Interrupt Register"]
2096pub mod diep2_int;
2097#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep2_tsiz](diep2_tsiz) module"]
2098pub type DIEP2_TSIZ = crate::Reg<u32, _DIEP2_TSIZ>;
2099#[allow(missing_docs)]
2100#[doc(hidden)]
2101pub struct _DIEP2_TSIZ;
2102#[doc = "`read()` method returns [diep2_tsiz::R](diep2_tsiz::R) reader structure"]
2103impl crate::Readable for DIEP2_TSIZ {}
2104#[doc = "`write(|w| ..)` method takes [diep2_tsiz::W](diep2_tsiz::W) writer structure"]
2105impl crate::Writable for DIEP2_TSIZ {}
2106#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2107pub mod diep2_tsiz;
2108#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep2_dmaaddr](diep2_dmaaddr) module"]
2109pub type DIEP2_DMAADDR = crate::Reg<u32, _DIEP2_DMAADDR>;
2110#[allow(missing_docs)]
2111#[doc(hidden)]
2112pub struct _DIEP2_DMAADDR;
2113#[doc = "`read()` method returns [diep2_dmaaddr::R](diep2_dmaaddr::R) reader structure"]
2114impl crate::Readable for DIEP2_DMAADDR {}
2115#[doc = "`write(|w| ..)` method takes [diep2_dmaaddr::W](diep2_dmaaddr::W) writer structure"]
2116impl crate::Writable for DIEP2_DMAADDR {}
2117#[doc = "Device IN Endpoint 1 DMA Address Register"]
2118pub mod diep2_dmaaddr;
2119#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep2_dtxfsts](diep2_dtxfsts) module"]
2120pub type DIEP2_DTXFSTS = crate::Reg<u32, _DIEP2_DTXFSTS>;
2121#[allow(missing_docs)]
2122#[doc(hidden)]
2123pub struct _DIEP2_DTXFSTS;
2124#[doc = "`read()` method returns [diep2_dtxfsts::R](diep2_dtxfsts::R) reader structure"]
2125impl crate::Readable for DIEP2_DTXFSTS {}
2126#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2127pub mod diep2_dtxfsts;
2128#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_ctl](diep3_ctl) module"]
2129pub type DIEP3_CTL = crate::Reg<u32, _DIEP3_CTL>;
2130#[allow(missing_docs)]
2131#[doc(hidden)]
2132pub struct _DIEP3_CTL;
2133#[doc = "`read()` method returns [diep3_ctl::R](diep3_ctl::R) reader structure"]
2134impl crate::Readable for DIEP3_CTL {}
2135#[doc = "`write(|w| ..)` method takes [diep3_ctl::W](diep3_ctl::W) writer structure"]
2136impl crate::Writable for DIEP3_CTL {}
2137#[doc = "Device Control IN Endpoint 1 Control Register"]
2138pub mod diep3_ctl;
2139#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_int](diep3_int) module"]
2140pub type DIEP3_INT = crate::Reg<u32, _DIEP3_INT>;
2141#[allow(missing_docs)]
2142#[doc(hidden)]
2143pub struct _DIEP3_INT;
2144#[doc = "`read()` method returns [diep3_int::R](diep3_int::R) reader structure"]
2145impl crate::Readable for DIEP3_INT {}
2146#[doc = "`write(|w| ..)` method takes [diep3_int::W](diep3_int::W) writer structure"]
2147impl crate::Writable for DIEP3_INT {}
2148#[doc = "Device IN Endpoint 1 Interrupt Register"]
2149pub mod diep3_int;
2150#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_tsiz](diep3_tsiz) module"]
2151pub type DIEP3_TSIZ = crate::Reg<u32, _DIEP3_TSIZ>;
2152#[allow(missing_docs)]
2153#[doc(hidden)]
2154pub struct _DIEP3_TSIZ;
2155#[doc = "`read()` method returns [diep3_tsiz::R](diep3_tsiz::R) reader structure"]
2156impl crate::Readable for DIEP3_TSIZ {}
2157#[doc = "`write(|w| ..)` method takes [diep3_tsiz::W](diep3_tsiz::W) writer structure"]
2158impl crate::Writable for DIEP3_TSIZ {}
2159#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2160pub mod diep3_tsiz;
2161#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_dmaaddr](diep3_dmaaddr) module"]
2162pub type DIEP3_DMAADDR = crate::Reg<u32, _DIEP3_DMAADDR>;
2163#[allow(missing_docs)]
2164#[doc(hidden)]
2165pub struct _DIEP3_DMAADDR;
2166#[doc = "`read()` method returns [diep3_dmaaddr::R](diep3_dmaaddr::R) reader structure"]
2167impl crate::Readable for DIEP3_DMAADDR {}
2168#[doc = "`write(|w| ..)` method takes [diep3_dmaaddr::W](diep3_dmaaddr::W) writer structure"]
2169impl crate::Writable for DIEP3_DMAADDR {}
2170#[doc = "Device IN Endpoint 1 DMA Address Register"]
2171pub mod diep3_dmaaddr;
2172#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep3_dtxfsts](diep3_dtxfsts) module"]
2173pub type DIEP3_DTXFSTS = crate::Reg<u32, _DIEP3_DTXFSTS>;
2174#[allow(missing_docs)]
2175#[doc(hidden)]
2176pub struct _DIEP3_DTXFSTS;
2177#[doc = "`read()` method returns [diep3_dtxfsts::R](diep3_dtxfsts::R) reader structure"]
2178impl crate::Readable for DIEP3_DTXFSTS {}
2179#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2180pub mod diep3_dtxfsts;
2181#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep4_ctl](diep4_ctl) module"]
2182pub type DIEP4_CTL = crate::Reg<u32, _DIEP4_CTL>;
2183#[allow(missing_docs)]
2184#[doc(hidden)]
2185pub struct _DIEP4_CTL;
2186#[doc = "`read()` method returns [diep4_ctl::R](diep4_ctl::R) reader structure"]
2187impl crate::Readable for DIEP4_CTL {}
2188#[doc = "`write(|w| ..)` method takes [diep4_ctl::W](diep4_ctl::W) writer structure"]
2189impl crate::Writable for DIEP4_CTL {}
2190#[doc = "Device Control IN Endpoint 1 Control Register"]
2191pub mod diep4_ctl;
2192#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep4_int](diep4_int) module"]
2193pub type DIEP4_INT = crate::Reg<u32, _DIEP4_INT>;
2194#[allow(missing_docs)]
2195#[doc(hidden)]
2196pub struct _DIEP4_INT;
2197#[doc = "`read()` method returns [diep4_int::R](diep4_int::R) reader structure"]
2198impl crate::Readable for DIEP4_INT {}
2199#[doc = "`write(|w| ..)` method takes [diep4_int::W](diep4_int::W) writer structure"]
2200impl crate::Writable for DIEP4_INT {}
2201#[doc = "Device IN Endpoint 1 Interrupt Register"]
2202pub mod diep4_int;
2203#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep4_tsiz](diep4_tsiz) module"]
2204pub type DIEP4_TSIZ = crate::Reg<u32, _DIEP4_TSIZ>;
2205#[allow(missing_docs)]
2206#[doc(hidden)]
2207pub struct _DIEP4_TSIZ;
2208#[doc = "`read()` method returns [diep4_tsiz::R](diep4_tsiz::R) reader structure"]
2209impl crate::Readable for DIEP4_TSIZ {}
2210#[doc = "`write(|w| ..)` method takes [diep4_tsiz::W](diep4_tsiz::W) writer structure"]
2211impl crate::Writable for DIEP4_TSIZ {}
2212#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2213pub mod diep4_tsiz;
2214#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep4_dmaaddr](diep4_dmaaddr) module"]
2215pub type DIEP4_DMAADDR = crate::Reg<u32, _DIEP4_DMAADDR>;
2216#[allow(missing_docs)]
2217#[doc(hidden)]
2218pub struct _DIEP4_DMAADDR;
2219#[doc = "`read()` method returns [diep4_dmaaddr::R](diep4_dmaaddr::R) reader structure"]
2220impl crate::Readable for DIEP4_DMAADDR {}
2221#[doc = "`write(|w| ..)` method takes [diep4_dmaaddr::W](diep4_dmaaddr::W) writer structure"]
2222impl crate::Writable for DIEP4_DMAADDR {}
2223#[doc = "Device IN Endpoint 1 DMA Address Register"]
2224pub mod diep4_dmaaddr;
2225#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep4_dtxfsts](diep4_dtxfsts) module"]
2226pub type DIEP4_DTXFSTS = crate::Reg<u32, _DIEP4_DTXFSTS>;
2227#[allow(missing_docs)]
2228#[doc(hidden)]
2229pub struct _DIEP4_DTXFSTS;
2230#[doc = "`read()` method returns [diep4_dtxfsts::R](diep4_dtxfsts::R) reader structure"]
2231impl crate::Readable for DIEP4_DTXFSTS {}
2232#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2233pub mod diep4_dtxfsts;
2234#[doc = "Device Control IN Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_ctl](diep5_ctl) module"]
2235pub type DIEP5_CTL = crate::Reg<u32, _DIEP5_CTL>;
2236#[allow(missing_docs)]
2237#[doc(hidden)]
2238pub struct _DIEP5_CTL;
2239#[doc = "`read()` method returns [diep5_ctl::R](diep5_ctl::R) reader structure"]
2240impl crate::Readable for DIEP5_CTL {}
2241#[doc = "`write(|w| ..)` method takes [diep5_ctl::W](diep5_ctl::W) writer structure"]
2242impl crate::Writable for DIEP5_CTL {}
2243#[doc = "Device Control IN Endpoint 1 Control Register"]
2244pub mod diep5_ctl;
2245#[doc = "Device IN Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_int](diep5_int) module"]
2246pub type DIEP5_INT = crate::Reg<u32, _DIEP5_INT>;
2247#[allow(missing_docs)]
2248#[doc(hidden)]
2249pub struct _DIEP5_INT;
2250#[doc = "`read()` method returns [diep5_int::R](diep5_int::R) reader structure"]
2251impl crate::Readable for DIEP5_INT {}
2252#[doc = "`write(|w| ..)` method takes [diep5_int::W](diep5_int::W) writer structure"]
2253impl crate::Writable for DIEP5_INT {}
2254#[doc = "Device IN Endpoint 1 Interrupt Register"]
2255pub mod diep5_int;
2256#[doc = "Device IN Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_tsiz](diep5_tsiz) module"]
2257pub type DIEP5_TSIZ = crate::Reg<u32, _DIEP5_TSIZ>;
2258#[allow(missing_docs)]
2259#[doc(hidden)]
2260pub struct _DIEP5_TSIZ;
2261#[doc = "`read()` method returns [diep5_tsiz::R](diep5_tsiz::R) reader structure"]
2262impl crate::Readable for DIEP5_TSIZ {}
2263#[doc = "`write(|w| ..)` method takes [diep5_tsiz::W](diep5_tsiz::W) writer structure"]
2264impl crate::Writable for DIEP5_TSIZ {}
2265#[doc = "Device IN Endpoint 1 Transfer Size Register"]
2266pub mod diep5_tsiz;
2267#[doc = "Device IN Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_dmaaddr](diep5_dmaaddr) module"]
2268pub type DIEP5_DMAADDR = crate::Reg<u32, _DIEP5_DMAADDR>;
2269#[allow(missing_docs)]
2270#[doc(hidden)]
2271pub struct _DIEP5_DMAADDR;
2272#[doc = "`read()` method returns [diep5_dmaaddr::R](diep5_dmaaddr::R) reader structure"]
2273impl crate::Readable for DIEP5_DMAADDR {}
2274#[doc = "`write(|w| ..)` method takes [diep5_dmaaddr::W](diep5_dmaaddr::W) writer structure"]
2275impl crate::Writable for DIEP5_DMAADDR {}
2276#[doc = "Device IN Endpoint 1 DMA Address Register"]
2277pub mod diep5_dmaaddr;
2278#[doc = "Device IN Endpoint Transmit FIFO Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_dtxfsts](diep5_dtxfsts) module"]
2279pub type DIEP5_DTXFSTS = crate::Reg<u32, _DIEP5_DTXFSTS>;
2280#[allow(missing_docs)]
2281#[doc(hidden)]
2282pub struct _DIEP5_DTXFSTS;
2283#[doc = "`read()` method returns [diep5_dtxfsts::R](diep5_dtxfsts::R) reader structure"]
2284impl crate::Readable for DIEP5_DTXFSTS {}
2285#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
2286pub mod diep5_dtxfsts;
2287#[doc = "Device Control OUT Endpoint 0 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0ctl](doep0ctl) module"]
2288pub type DOEP0CTL = crate::Reg<u32, _DOEP0CTL>;
2289#[allow(missing_docs)]
2290#[doc(hidden)]
2291pub struct _DOEP0CTL;
2292#[doc = "`read()` method returns [doep0ctl::R](doep0ctl::R) reader structure"]
2293impl crate::Readable for DOEP0CTL {}
2294#[doc = "`write(|w| ..)` method takes [doep0ctl::W](doep0ctl::W) writer structure"]
2295impl crate::Writable for DOEP0CTL {}
2296#[doc = "Device Control OUT Endpoint 0 Control Register"]
2297pub mod doep0ctl;
2298#[doc = "Device OUT Endpoint 0 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0int](doep0int) module"]
2299pub type DOEP0INT = crate::Reg<u32, _DOEP0INT>;
2300#[allow(missing_docs)]
2301#[doc(hidden)]
2302pub struct _DOEP0INT;
2303#[doc = "`read()` method returns [doep0int::R](doep0int::R) reader structure"]
2304impl crate::Readable for DOEP0INT {}
2305#[doc = "`write(|w| ..)` method takes [doep0int::W](doep0int::W) writer structure"]
2306impl crate::Writable for DOEP0INT {}
2307#[doc = "Device OUT Endpoint 0 Interrupt Register"]
2308pub mod doep0int;
2309#[doc = "Device OUT Endpoint 0 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0tsiz](doep0tsiz) module"]
2310pub type DOEP0TSIZ = crate::Reg<u32, _DOEP0TSIZ>;
2311#[allow(missing_docs)]
2312#[doc(hidden)]
2313pub struct _DOEP0TSIZ;
2314#[doc = "`read()` method returns [doep0tsiz::R](doep0tsiz::R) reader structure"]
2315impl crate::Readable for DOEP0TSIZ {}
2316#[doc = "`write(|w| ..)` method takes [doep0tsiz::W](doep0tsiz::W) writer structure"]
2317impl crate::Writable for DOEP0TSIZ {}
2318#[doc = "Device OUT Endpoint 0 Transfer Size Register"]
2319pub mod doep0tsiz;
2320#[doc = "Device OUT Endpoint 0 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0dmaaddr](doep0dmaaddr) module"]
2321pub type DOEP0DMAADDR = crate::Reg<u32, _DOEP0DMAADDR>;
2322#[allow(missing_docs)]
2323#[doc(hidden)]
2324pub struct _DOEP0DMAADDR;
2325#[doc = "`read()` method returns [doep0dmaaddr::R](doep0dmaaddr::R) reader structure"]
2326impl crate::Readable for DOEP0DMAADDR {}
2327#[doc = "`write(|w| ..)` method takes [doep0dmaaddr::W](doep0dmaaddr::W) writer structure"]
2328impl crate::Writable for DOEP0DMAADDR {}
2329#[doc = "Device OUT Endpoint 0 DMA Address Register"]
2330pub mod doep0dmaaddr;
2331#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0_ctl](doep0_ctl) module"]
2332pub type DOEP0_CTL = crate::Reg<u32, _DOEP0_CTL>;
2333#[allow(missing_docs)]
2334#[doc(hidden)]
2335pub struct _DOEP0_CTL;
2336#[doc = "`read()` method returns [doep0_ctl::R](doep0_ctl::R) reader structure"]
2337impl crate::Readable for DOEP0_CTL {}
2338#[doc = "`write(|w| ..)` method takes [doep0_ctl::W](doep0_ctl::W) writer structure"]
2339impl crate::Writable for DOEP0_CTL {}
2340#[doc = "Device Control OUT Endpoint 1 Control Register"]
2341pub mod doep0_ctl;
2342#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0_int](doep0_int) module"]
2343pub type DOEP0_INT = crate::Reg<u32, _DOEP0_INT>;
2344#[allow(missing_docs)]
2345#[doc(hidden)]
2346pub struct _DOEP0_INT;
2347#[doc = "`read()` method returns [doep0_int::R](doep0_int::R) reader structure"]
2348impl crate::Readable for DOEP0_INT {}
2349#[doc = "`write(|w| ..)` method takes [doep0_int::W](doep0_int::W) writer structure"]
2350impl crate::Writable for DOEP0_INT {}
2351#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2352pub mod doep0_int;
2353#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0_tsiz](doep0_tsiz) module"]
2354pub type DOEP0_TSIZ = crate::Reg<u32, _DOEP0_TSIZ>;
2355#[allow(missing_docs)]
2356#[doc(hidden)]
2357pub struct _DOEP0_TSIZ;
2358#[doc = "`read()` method returns [doep0_tsiz::R](doep0_tsiz::R) reader structure"]
2359impl crate::Readable for DOEP0_TSIZ {}
2360#[doc = "`write(|w| ..)` method takes [doep0_tsiz::W](doep0_tsiz::W) writer structure"]
2361impl crate::Writable for DOEP0_TSIZ {}
2362#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2363pub mod doep0_tsiz;
2364#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep0_dmaaddr](doep0_dmaaddr) module"]
2365pub type DOEP0_DMAADDR = crate::Reg<u32, _DOEP0_DMAADDR>;
2366#[allow(missing_docs)]
2367#[doc(hidden)]
2368pub struct _DOEP0_DMAADDR;
2369#[doc = "`read()` method returns [doep0_dmaaddr::R](doep0_dmaaddr::R) reader structure"]
2370impl crate::Readable for DOEP0_DMAADDR {}
2371#[doc = "`write(|w| ..)` method takes [doep0_dmaaddr::W](doep0_dmaaddr::W) writer structure"]
2372impl crate::Writable for DOEP0_DMAADDR {}
2373#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2374pub mod doep0_dmaaddr;
2375#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep1_ctl](doep1_ctl) module"]
2376pub type DOEP1_CTL = crate::Reg<u32, _DOEP1_CTL>;
2377#[allow(missing_docs)]
2378#[doc(hidden)]
2379pub struct _DOEP1_CTL;
2380#[doc = "`read()` method returns [doep1_ctl::R](doep1_ctl::R) reader structure"]
2381impl crate::Readable for DOEP1_CTL {}
2382#[doc = "`write(|w| ..)` method takes [doep1_ctl::W](doep1_ctl::W) writer structure"]
2383impl crate::Writable for DOEP1_CTL {}
2384#[doc = "Device Control OUT Endpoint 1 Control Register"]
2385pub mod doep1_ctl;
2386#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep1_int](doep1_int) module"]
2387pub type DOEP1_INT = crate::Reg<u32, _DOEP1_INT>;
2388#[allow(missing_docs)]
2389#[doc(hidden)]
2390pub struct _DOEP1_INT;
2391#[doc = "`read()` method returns [doep1_int::R](doep1_int::R) reader structure"]
2392impl crate::Readable for DOEP1_INT {}
2393#[doc = "`write(|w| ..)` method takes [doep1_int::W](doep1_int::W) writer structure"]
2394impl crate::Writable for DOEP1_INT {}
2395#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2396pub mod doep1_int;
2397#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep1_tsiz](doep1_tsiz) module"]
2398pub type DOEP1_TSIZ = crate::Reg<u32, _DOEP1_TSIZ>;
2399#[allow(missing_docs)]
2400#[doc(hidden)]
2401pub struct _DOEP1_TSIZ;
2402#[doc = "`read()` method returns [doep1_tsiz::R](doep1_tsiz::R) reader structure"]
2403impl crate::Readable for DOEP1_TSIZ {}
2404#[doc = "`write(|w| ..)` method takes [doep1_tsiz::W](doep1_tsiz::W) writer structure"]
2405impl crate::Writable for DOEP1_TSIZ {}
2406#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2407pub mod doep1_tsiz;
2408#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep1_dmaaddr](doep1_dmaaddr) module"]
2409pub type DOEP1_DMAADDR = crate::Reg<u32, _DOEP1_DMAADDR>;
2410#[allow(missing_docs)]
2411#[doc(hidden)]
2412pub struct _DOEP1_DMAADDR;
2413#[doc = "`read()` method returns [doep1_dmaaddr::R](doep1_dmaaddr::R) reader structure"]
2414impl crate::Readable for DOEP1_DMAADDR {}
2415#[doc = "`write(|w| ..)` method takes [doep1_dmaaddr::W](doep1_dmaaddr::W) writer structure"]
2416impl crate::Writable for DOEP1_DMAADDR {}
2417#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2418pub mod doep1_dmaaddr;
2419#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep2_ctl](doep2_ctl) module"]
2420pub type DOEP2_CTL = crate::Reg<u32, _DOEP2_CTL>;
2421#[allow(missing_docs)]
2422#[doc(hidden)]
2423pub struct _DOEP2_CTL;
2424#[doc = "`read()` method returns [doep2_ctl::R](doep2_ctl::R) reader structure"]
2425impl crate::Readable for DOEP2_CTL {}
2426#[doc = "`write(|w| ..)` method takes [doep2_ctl::W](doep2_ctl::W) writer structure"]
2427impl crate::Writable for DOEP2_CTL {}
2428#[doc = "Device Control OUT Endpoint 1 Control Register"]
2429pub mod doep2_ctl;
2430#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep2_int](doep2_int) module"]
2431pub type DOEP2_INT = crate::Reg<u32, _DOEP2_INT>;
2432#[allow(missing_docs)]
2433#[doc(hidden)]
2434pub struct _DOEP2_INT;
2435#[doc = "`read()` method returns [doep2_int::R](doep2_int::R) reader structure"]
2436impl crate::Readable for DOEP2_INT {}
2437#[doc = "`write(|w| ..)` method takes [doep2_int::W](doep2_int::W) writer structure"]
2438impl crate::Writable for DOEP2_INT {}
2439#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2440pub mod doep2_int;
2441#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep2_tsiz](doep2_tsiz) module"]
2442pub type DOEP2_TSIZ = crate::Reg<u32, _DOEP2_TSIZ>;
2443#[allow(missing_docs)]
2444#[doc(hidden)]
2445pub struct _DOEP2_TSIZ;
2446#[doc = "`read()` method returns [doep2_tsiz::R](doep2_tsiz::R) reader structure"]
2447impl crate::Readable for DOEP2_TSIZ {}
2448#[doc = "`write(|w| ..)` method takes [doep2_tsiz::W](doep2_tsiz::W) writer structure"]
2449impl crate::Writable for DOEP2_TSIZ {}
2450#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2451pub mod doep2_tsiz;
2452#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep2_dmaaddr](doep2_dmaaddr) module"]
2453pub type DOEP2_DMAADDR = crate::Reg<u32, _DOEP2_DMAADDR>;
2454#[allow(missing_docs)]
2455#[doc(hidden)]
2456pub struct _DOEP2_DMAADDR;
2457#[doc = "`read()` method returns [doep2_dmaaddr::R](doep2_dmaaddr::R) reader structure"]
2458impl crate::Readable for DOEP2_DMAADDR {}
2459#[doc = "`write(|w| ..)` method takes [doep2_dmaaddr::W](doep2_dmaaddr::W) writer structure"]
2460impl crate::Writable for DOEP2_DMAADDR {}
2461#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2462pub mod doep2_dmaaddr;
2463#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep3_ctl](doep3_ctl) module"]
2464pub type DOEP3_CTL = crate::Reg<u32, _DOEP3_CTL>;
2465#[allow(missing_docs)]
2466#[doc(hidden)]
2467pub struct _DOEP3_CTL;
2468#[doc = "`read()` method returns [doep3_ctl::R](doep3_ctl::R) reader structure"]
2469impl crate::Readable for DOEP3_CTL {}
2470#[doc = "`write(|w| ..)` method takes [doep3_ctl::W](doep3_ctl::W) writer structure"]
2471impl crate::Writable for DOEP3_CTL {}
2472#[doc = "Device Control OUT Endpoint 1 Control Register"]
2473pub mod doep3_ctl;
2474#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep3_int](doep3_int) module"]
2475pub type DOEP3_INT = crate::Reg<u32, _DOEP3_INT>;
2476#[allow(missing_docs)]
2477#[doc(hidden)]
2478pub struct _DOEP3_INT;
2479#[doc = "`read()` method returns [doep3_int::R](doep3_int::R) reader structure"]
2480impl crate::Readable for DOEP3_INT {}
2481#[doc = "`write(|w| ..)` method takes [doep3_int::W](doep3_int::W) writer structure"]
2482impl crate::Writable for DOEP3_INT {}
2483#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2484pub mod doep3_int;
2485#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep3_tsiz](doep3_tsiz) module"]
2486pub type DOEP3_TSIZ = crate::Reg<u32, _DOEP3_TSIZ>;
2487#[allow(missing_docs)]
2488#[doc(hidden)]
2489pub struct _DOEP3_TSIZ;
2490#[doc = "`read()` method returns [doep3_tsiz::R](doep3_tsiz::R) reader structure"]
2491impl crate::Readable for DOEP3_TSIZ {}
2492#[doc = "`write(|w| ..)` method takes [doep3_tsiz::W](doep3_tsiz::W) writer structure"]
2493impl crate::Writable for DOEP3_TSIZ {}
2494#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2495pub mod doep3_tsiz;
2496#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep3_dmaaddr](doep3_dmaaddr) module"]
2497pub type DOEP3_DMAADDR = crate::Reg<u32, _DOEP3_DMAADDR>;
2498#[allow(missing_docs)]
2499#[doc(hidden)]
2500pub struct _DOEP3_DMAADDR;
2501#[doc = "`read()` method returns [doep3_dmaaddr::R](doep3_dmaaddr::R) reader structure"]
2502impl crate::Readable for DOEP3_DMAADDR {}
2503#[doc = "`write(|w| ..)` method takes [doep3_dmaaddr::W](doep3_dmaaddr::W) writer structure"]
2504impl crate::Writable for DOEP3_DMAADDR {}
2505#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2506pub mod doep3_dmaaddr;
2507#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep4_ctl](doep4_ctl) module"]
2508pub type DOEP4_CTL = crate::Reg<u32, _DOEP4_CTL>;
2509#[allow(missing_docs)]
2510#[doc(hidden)]
2511pub struct _DOEP4_CTL;
2512#[doc = "`read()` method returns [doep4_ctl::R](doep4_ctl::R) reader structure"]
2513impl crate::Readable for DOEP4_CTL {}
2514#[doc = "`write(|w| ..)` method takes [doep4_ctl::W](doep4_ctl::W) writer structure"]
2515impl crate::Writable for DOEP4_CTL {}
2516#[doc = "Device Control OUT Endpoint 1 Control Register"]
2517pub mod doep4_ctl;
2518#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep4_int](doep4_int) module"]
2519pub type DOEP4_INT = crate::Reg<u32, _DOEP4_INT>;
2520#[allow(missing_docs)]
2521#[doc(hidden)]
2522pub struct _DOEP4_INT;
2523#[doc = "`read()` method returns [doep4_int::R](doep4_int::R) reader structure"]
2524impl crate::Readable for DOEP4_INT {}
2525#[doc = "`write(|w| ..)` method takes [doep4_int::W](doep4_int::W) writer structure"]
2526impl crate::Writable for DOEP4_INT {}
2527#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2528pub mod doep4_int;
2529#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep4_tsiz](doep4_tsiz) module"]
2530pub type DOEP4_TSIZ = crate::Reg<u32, _DOEP4_TSIZ>;
2531#[allow(missing_docs)]
2532#[doc(hidden)]
2533pub struct _DOEP4_TSIZ;
2534#[doc = "`read()` method returns [doep4_tsiz::R](doep4_tsiz::R) reader structure"]
2535impl crate::Readable for DOEP4_TSIZ {}
2536#[doc = "`write(|w| ..)` method takes [doep4_tsiz::W](doep4_tsiz::W) writer structure"]
2537impl crate::Writable for DOEP4_TSIZ {}
2538#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2539pub mod doep4_tsiz;
2540#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep4_dmaaddr](doep4_dmaaddr) module"]
2541pub type DOEP4_DMAADDR = crate::Reg<u32, _DOEP4_DMAADDR>;
2542#[allow(missing_docs)]
2543#[doc(hidden)]
2544pub struct _DOEP4_DMAADDR;
2545#[doc = "`read()` method returns [doep4_dmaaddr::R](doep4_dmaaddr::R) reader structure"]
2546impl crate::Readable for DOEP4_DMAADDR {}
2547#[doc = "`write(|w| ..)` method takes [doep4_dmaaddr::W](doep4_dmaaddr::W) writer structure"]
2548impl crate::Writable for DOEP4_DMAADDR {}
2549#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2550pub mod doep4_dmaaddr;
2551#[doc = "Device Control OUT Endpoint 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep5_ctl](doep5_ctl) module"]
2552pub type DOEP5_CTL = crate::Reg<u32, _DOEP5_CTL>;
2553#[allow(missing_docs)]
2554#[doc(hidden)]
2555pub struct _DOEP5_CTL;
2556#[doc = "`read()` method returns [doep5_ctl::R](doep5_ctl::R) reader structure"]
2557impl crate::Readable for DOEP5_CTL {}
2558#[doc = "`write(|w| ..)` method takes [doep5_ctl::W](doep5_ctl::W) writer structure"]
2559impl crate::Writable for DOEP5_CTL {}
2560#[doc = "Device Control OUT Endpoint 1 Control Register"]
2561pub mod doep5_ctl;
2562#[doc = "Device OUT Endpoint 1 Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep5_int](doep5_int) module"]
2563pub type DOEP5_INT = crate::Reg<u32, _DOEP5_INT>;
2564#[allow(missing_docs)]
2565#[doc(hidden)]
2566pub struct _DOEP5_INT;
2567#[doc = "`read()` method returns [doep5_int::R](doep5_int::R) reader structure"]
2568impl crate::Readable for DOEP5_INT {}
2569#[doc = "`write(|w| ..)` method takes [doep5_int::W](doep5_int::W) writer structure"]
2570impl crate::Writable for DOEP5_INT {}
2571#[doc = "Device OUT Endpoint 1 Interrupt Register"]
2572pub mod doep5_int;
2573#[doc = "Device OUT Endpoint 1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep5_tsiz](doep5_tsiz) module"]
2574pub type DOEP5_TSIZ = crate::Reg<u32, _DOEP5_TSIZ>;
2575#[allow(missing_docs)]
2576#[doc(hidden)]
2577pub struct _DOEP5_TSIZ;
2578#[doc = "`read()` method returns [doep5_tsiz::R](doep5_tsiz::R) reader structure"]
2579impl crate::Readable for DOEP5_TSIZ {}
2580#[doc = "`write(|w| ..)` method takes [doep5_tsiz::W](doep5_tsiz::W) writer structure"]
2581impl crate::Writable for DOEP5_TSIZ {}
2582#[doc = "Device OUT Endpoint 1 Transfer Size Register"]
2583pub mod doep5_tsiz;
2584#[doc = "Device OUT Endpoint 1 DMA Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [doep5_dmaaddr](doep5_dmaaddr) module"]
2585pub type DOEP5_DMAADDR = crate::Reg<u32, _DOEP5_DMAADDR>;
2586#[allow(missing_docs)]
2587#[doc(hidden)]
2588pub struct _DOEP5_DMAADDR;
2589#[doc = "`read()` method returns [doep5_dmaaddr::R](doep5_dmaaddr::R) reader structure"]
2590impl crate::Readable for DOEP5_DMAADDR {}
2591#[doc = "`write(|w| ..)` method takes [doep5_dmaaddr::W](doep5_dmaaddr::W) writer structure"]
2592impl crate::Writable for DOEP5_DMAADDR {}
2593#[doc = "Device OUT Endpoint 1 DMA Address Register"]
2594pub mod doep5_dmaaddr;
2595#[doc = "Power and Clock Gating Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](pcgcctl) module"]
2596pub type PCGCCTL = crate::Reg<u32, _PCGCCTL>;
2597#[allow(missing_docs)]
2598#[doc(hidden)]
2599pub struct _PCGCCTL;
2600#[doc = "`read()` method returns [pcgcctl::R](pcgcctl::R) reader structure"]
2601impl crate::Readable for PCGCCTL {}
2602#[doc = "`write(|w| ..)` method takes [pcgcctl::W](pcgcctl::W) writer structure"]
2603impl crate::Writable for PCGCCTL {}
2604#[doc = "Power and Clock Gating Control Register"]
2605pub mod pcgcctl;