1#[doc = "Reader of register CH20_CTRL"]
2pub type R = crate::R<u32, super::CH20_CTRL>;
3#[doc = "Writer for register CH20_CTRL"]
4pub type W = crate::W<u32, super::CH20_CTRL>;
5#[doc = "Register CH20_CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CH20_CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `SIGSEL`"]
14pub type SIGSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `SIGSEL`"]
16pub struct SIGSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> SIGSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
24 self.w
25 }
26}
27#[doc = "Source Select\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29#[repr(u8)]
30pub enum SOURCESEL_A {
31 #[doc = "0: No source selected"]
32 NONE = 0,
33 #[doc = "1: Peripheral Reflex System"]
34 PRSL = 1,
35 #[doc = "2: Peripheral Reflex System"]
36 PRS = 2,
37 #[doc = "3: Peripheral Reflex System"]
38 PRSH = 3,
39 #[doc = "4: Analog Comparator 0"]
40 ACMP0 = 4,
41 #[doc = "5: Analog Comparator 1"]
42 ACMP1 = 5,
43 #[doc = "6: Analog to Digital Converter 0"]
44 ADC0 = 6,
45 #[doc = "7: Real-Time Counter"]
46 RTC = 7,
47 #[doc = "8: Real-Time Counter and Calendar"]
48 RTCC = 8,
49 #[doc = "9: General purpose Input/Output"]
50 GPIOL = 9,
51 #[doc = "10: General purpose Input/Output"]
52 GPIOH = 10,
53 #[doc = "11: Low Energy Timer 0"]
54 LETIMER0 = 11,
55 #[doc = "12: Low Energy Timer 1"]
56 LETIMER1 = 12,
57 #[doc = "13: Pulse Counter 0"]
58 PCNT0 = 13,
59 #[doc = "14: Pulse Counter 1"]
60 PCNT1 = 14,
61 #[doc = "15: Pulse Counter 2"]
62 PCNT2 = 15,
63 #[doc = "16: CryoTimer"]
64 CRYOTIMER = 16,
65 #[doc = "17: Clock Management Unit"]
66 CMU = 17,
67 #[doc = "23: Digital to Analog Converter 0"]
68 VDAC0 = 23,
69 #[doc = "24: Low Energy Sensor Interface"]
70 LESENSEL = 24,
71 #[doc = "25: Low Energy Sensor Interface"]
72 LESENSEH = 25,
73 #[doc = "26: Low Energy Sensor Interface"]
74 LESENSED = 26,
75 #[doc = "27: Low Energy Sensor Interface"]
76 LESENSE = 27,
77 #[doc = "28: Analog Comparator 1"]
78 ACMP2 = 28,
79 #[doc = "29: Analog Comparator 3"]
80 ACMP3 = 29,
81 #[doc = "30: Analog to Digital Converter 0"]
82 ADC1 = 30,
83 #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
84 USART0 = 48,
85 #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
86 USART1 = 49,
87 #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
88 USART2 = 50,
89 #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
90 USART3 = 51,
91 #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
92 USART4 = 52,
93 #[doc = "53: Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
94 USART5 = 53,
95 #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
96 UART0 = 54,
97 #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
98 UART1 = 55,
99 #[doc = "60: Timer 0"]
100 TIMER0 = 60,
101 #[doc = "61: Timer 1"]
102 TIMER1 = 61,
103 #[doc = "62: Timer 2"]
104 TIMER2 = 62,
105 #[doc = "64: Universal Serial Bus Interface"]
106 USB = 64,
107 #[doc = "67: `1000011`"]
108 CM4 = 67,
109 #[doc = "80: Timer 3"]
110 TIMER3 = 80,
111 #[doc = "82: Wide Timer 0"]
112 WTIMER0 = 82,
113 #[doc = "83: Wide Timer 0"]
114 WTIMER1 = 83,
115 #[doc = "84: Wide Timer 2"]
116 WTIMER2 = 84,
117 #[doc = "85: Wide Timer 3"]
118 WTIMER3 = 85,
119 #[doc = "98: Timer 4"]
120 TIMER4 = 98,
121 #[doc = "99: Timer 5"]
122 TIMER5 = 99,
123 #[doc = "100: Timer 6"]
124 TIMER6 = 100,
125}
126impl From<SOURCESEL_A> for u8 {
127 #[inline(always)]
128 fn from(variant: SOURCESEL_A) -> Self {
129 variant as _
130 }
131}
132#[doc = "Reader of field `SOURCESEL`"]
133pub type SOURCESEL_R = crate::R<u8, SOURCESEL_A>;
134impl SOURCESEL_R {
135 #[doc = r"Get enumerated values variant"]
136 #[inline(always)]
137 pub fn variant(&self) -> crate::Variant<u8, SOURCESEL_A> {
138 use crate::Variant::*;
139 match self.bits {
140 0 => Val(SOURCESEL_A::NONE),
141 1 => Val(SOURCESEL_A::PRSL),
142 2 => Val(SOURCESEL_A::PRS),
143 3 => Val(SOURCESEL_A::PRSH),
144 4 => Val(SOURCESEL_A::ACMP0),
145 5 => Val(SOURCESEL_A::ACMP1),
146 6 => Val(SOURCESEL_A::ADC0),
147 7 => Val(SOURCESEL_A::RTC),
148 8 => Val(SOURCESEL_A::RTCC),
149 9 => Val(SOURCESEL_A::GPIOL),
150 10 => Val(SOURCESEL_A::GPIOH),
151 11 => Val(SOURCESEL_A::LETIMER0),
152 12 => Val(SOURCESEL_A::LETIMER1),
153 13 => Val(SOURCESEL_A::PCNT0),
154 14 => Val(SOURCESEL_A::PCNT1),
155 15 => Val(SOURCESEL_A::PCNT2),
156 16 => Val(SOURCESEL_A::CRYOTIMER),
157 17 => Val(SOURCESEL_A::CMU),
158 23 => Val(SOURCESEL_A::VDAC0),
159 24 => Val(SOURCESEL_A::LESENSEL),
160 25 => Val(SOURCESEL_A::LESENSEH),
161 26 => Val(SOURCESEL_A::LESENSED),
162 27 => Val(SOURCESEL_A::LESENSE),
163 28 => Val(SOURCESEL_A::ACMP2),
164 29 => Val(SOURCESEL_A::ACMP3),
165 30 => Val(SOURCESEL_A::ADC1),
166 48 => Val(SOURCESEL_A::USART0),
167 49 => Val(SOURCESEL_A::USART1),
168 50 => Val(SOURCESEL_A::USART2),
169 51 => Val(SOURCESEL_A::USART3),
170 52 => Val(SOURCESEL_A::USART4),
171 53 => Val(SOURCESEL_A::USART5),
172 54 => Val(SOURCESEL_A::UART0),
173 55 => Val(SOURCESEL_A::UART1),
174 60 => Val(SOURCESEL_A::TIMER0),
175 61 => Val(SOURCESEL_A::TIMER1),
176 62 => Val(SOURCESEL_A::TIMER2),
177 64 => Val(SOURCESEL_A::USB),
178 67 => Val(SOURCESEL_A::CM4),
179 80 => Val(SOURCESEL_A::TIMER3),
180 82 => Val(SOURCESEL_A::WTIMER0),
181 83 => Val(SOURCESEL_A::WTIMER1),
182 84 => Val(SOURCESEL_A::WTIMER2),
183 85 => Val(SOURCESEL_A::WTIMER3),
184 98 => Val(SOURCESEL_A::TIMER4),
185 99 => Val(SOURCESEL_A::TIMER5),
186 100 => Val(SOURCESEL_A::TIMER6),
187 i => Res(i),
188 }
189 }
190 #[doc = "Checks if the value of the field is `NONE`"]
191 #[inline(always)]
192 pub fn is_none(&self) -> bool {
193 *self == SOURCESEL_A::NONE
194 }
195 #[doc = "Checks if the value of the field is `PRSL`"]
196 #[inline(always)]
197 pub fn is_prsl(&self) -> bool {
198 *self == SOURCESEL_A::PRSL
199 }
200 #[doc = "Checks if the value of the field is `PRS`"]
201 #[inline(always)]
202 pub fn is_prs(&self) -> bool {
203 *self == SOURCESEL_A::PRS
204 }
205 #[doc = "Checks if the value of the field is `PRSH`"]
206 #[inline(always)]
207 pub fn is_prsh(&self) -> bool {
208 *self == SOURCESEL_A::PRSH
209 }
210 #[doc = "Checks if the value of the field is `ACMP0`"]
211 #[inline(always)]
212 pub fn is_acmp0(&self) -> bool {
213 *self == SOURCESEL_A::ACMP0
214 }
215 #[doc = "Checks if the value of the field is `ACMP1`"]
216 #[inline(always)]
217 pub fn is_acmp1(&self) -> bool {
218 *self == SOURCESEL_A::ACMP1
219 }
220 #[doc = "Checks if the value of the field is `ADC0`"]
221 #[inline(always)]
222 pub fn is_adc0(&self) -> bool {
223 *self == SOURCESEL_A::ADC0
224 }
225 #[doc = "Checks if the value of the field is `RTC`"]
226 #[inline(always)]
227 pub fn is_rtc(&self) -> bool {
228 *self == SOURCESEL_A::RTC
229 }
230 #[doc = "Checks if the value of the field is `RTCC`"]
231 #[inline(always)]
232 pub fn is_rtcc(&self) -> bool {
233 *self == SOURCESEL_A::RTCC
234 }
235 #[doc = "Checks if the value of the field is `GPIOL`"]
236 #[inline(always)]
237 pub fn is_gpiol(&self) -> bool {
238 *self == SOURCESEL_A::GPIOL
239 }
240 #[doc = "Checks if the value of the field is `GPIOH`"]
241 #[inline(always)]
242 pub fn is_gpioh(&self) -> bool {
243 *self == SOURCESEL_A::GPIOH
244 }
245 #[doc = "Checks if the value of the field is `LETIMER0`"]
246 #[inline(always)]
247 pub fn is_letimer0(&self) -> bool {
248 *self == SOURCESEL_A::LETIMER0
249 }
250 #[doc = "Checks if the value of the field is `LETIMER1`"]
251 #[inline(always)]
252 pub fn is_letimer1(&self) -> bool {
253 *self == SOURCESEL_A::LETIMER1
254 }
255 #[doc = "Checks if the value of the field is `PCNT0`"]
256 #[inline(always)]
257 pub fn is_pcnt0(&self) -> bool {
258 *self == SOURCESEL_A::PCNT0
259 }
260 #[doc = "Checks if the value of the field is `PCNT1`"]
261 #[inline(always)]
262 pub fn is_pcnt1(&self) -> bool {
263 *self == SOURCESEL_A::PCNT1
264 }
265 #[doc = "Checks if the value of the field is `PCNT2`"]
266 #[inline(always)]
267 pub fn is_pcnt2(&self) -> bool {
268 *self == SOURCESEL_A::PCNT2
269 }
270 #[doc = "Checks if the value of the field is `CRYOTIMER`"]
271 #[inline(always)]
272 pub fn is_cryotimer(&self) -> bool {
273 *self == SOURCESEL_A::CRYOTIMER
274 }
275 #[doc = "Checks if the value of the field is `CMU`"]
276 #[inline(always)]
277 pub fn is_cmu(&self) -> bool {
278 *self == SOURCESEL_A::CMU
279 }
280 #[doc = "Checks if the value of the field is `VDAC0`"]
281 #[inline(always)]
282 pub fn is_vdac0(&self) -> bool {
283 *self == SOURCESEL_A::VDAC0
284 }
285 #[doc = "Checks if the value of the field is `LESENSEL`"]
286 #[inline(always)]
287 pub fn is_lesensel(&self) -> bool {
288 *self == SOURCESEL_A::LESENSEL
289 }
290 #[doc = "Checks if the value of the field is `LESENSEH`"]
291 #[inline(always)]
292 pub fn is_lesenseh(&self) -> bool {
293 *self == SOURCESEL_A::LESENSEH
294 }
295 #[doc = "Checks if the value of the field is `LESENSED`"]
296 #[inline(always)]
297 pub fn is_lesensed(&self) -> bool {
298 *self == SOURCESEL_A::LESENSED
299 }
300 #[doc = "Checks if the value of the field is `LESENSE`"]
301 #[inline(always)]
302 pub fn is_lesense(&self) -> bool {
303 *self == SOURCESEL_A::LESENSE
304 }
305 #[doc = "Checks if the value of the field is `ACMP2`"]
306 #[inline(always)]
307 pub fn is_acmp2(&self) -> bool {
308 *self == SOURCESEL_A::ACMP2
309 }
310 #[doc = "Checks if the value of the field is `ACMP3`"]
311 #[inline(always)]
312 pub fn is_acmp3(&self) -> bool {
313 *self == SOURCESEL_A::ACMP3
314 }
315 #[doc = "Checks if the value of the field is `ADC1`"]
316 #[inline(always)]
317 pub fn is_adc1(&self) -> bool {
318 *self == SOURCESEL_A::ADC1
319 }
320 #[doc = "Checks if the value of the field is `USART0`"]
321 #[inline(always)]
322 pub fn is_usart0(&self) -> bool {
323 *self == SOURCESEL_A::USART0
324 }
325 #[doc = "Checks if the value of the field is `USART1`"]
326 #[inline(always)]
327 pub fn is_usart1(&self) -> bool {
328 *self == SOURCESEL_A::USART1
329 }
330 #[doc = "Checks if the value of the field is `USART2`"]
331 #[inline(always)]
332 pub fn is_usart2(&self) -> bool {
333 *self == SOURCESEL_A::USART2
334 }
335 #[doc = "Checks if the value of the field is `USART3`"]
336 #[inline(always)]
337 pub fn is_usart3(&self) -> bool {
338 *self == SOURCESEL_A::USART3
339 }
340 #[doc = "Checks if the value of the field is `USART4`"]
341 #[inline(always)]
342 pub fn is_usart4(&self) -> bool {
343 *self == SOURCESEL_A::USART4
344 }
345 #[doc = "Checks if the value of the field is `USART5`"]
346 #[inline(always)]
347 pub fn is_usart5(&self) -> bool {
348 *self == SOURCESEL_A::USART5
349 }
350 #[doc = "Checks if the value of the field is `UART0`"]
351 #[inline(always)]
352 pub fn is_uart0(&self) -> bool {
353 *self == SOURCESEL_A::UART0
354 }
355 #[doc = "Checks if the value of the field is `UART1`"]
356 #[inline(always)]
357 pub fn is_uart1(&self) -> bool {
358 *self == SOURCESEL_A::UART1
359 }
360 #[doc = "Checks if the value of the field is `TIMER0`"]
361 #[inline(always)]
362 pub fn is_timer0(&self) -> bool {
363 *self == SOURCESEL_A::TIMER0
364 }
365 #[doc = "Checks if the value of the field is `TIMER1`"]
366 #[inline(always)]
367 pub fn is_timer1(&self) -> bool {
368 *self == SOURCESEL_A::TIMER1
369 }
370 #[doc = "Checks if the value of the field is `TIMER2`"]
371 #[inline(always)]
372 pub fn is_timer2(&self) -> bool {
373 *self == SOURCESEL_A::TIMER2
374 }
375 #[doc = "Checks if the value of the field is `USB`"]
376 #[inline(always)]
377 pub fn is_usb(&self) -> bool {
378 *self == SOURCESEL_A::USB
379 }
380 #[doc = "Checks if the value of the field is `CM4`"]
381 #[inline(always)]
382 pub fn is_cm4(&self) -> bool {
383 *self == SOURCESEL_A::CM4
384 }
385 #[doc = "Checks if the value of the field is `TIMER3`"]
386 #[inline(always)]
387 pub fn is_timer3(&self) -> bool {
388 *self == SOURCESEL_A::TIMER3
389 }
390 #[doc = "Checks if the value of the field is `WTIMER0`"]
391 #[inline(always)]
392 pub fn is_wtimer0(&self) -> bool {
393 *self == SOURCESEL_A::WTIMER0
394 }
395 #[doc = "Checks if the value of the field is `WTIMER1`"]
396 #[inline(always)]
397 pub fn is_wtimer1(&self) -> bool {
398 *self == SOURCESEL_A::WTIMER1
399 }
400 #[doc = "Checks if the value of the field is `WTIMER2`"]
401 #[inline(always)]
402 pub fn is_wtimer2(&self) -> bool {
403 *self == SOURCESEL_A::WTIMER2
404 }
405 #[doc = "Checks if the value of the field is `WTIMER3`"]
406 #[inline(always)]
407 pub fn is_wtimer3(&self) -> bool {
408 *self == SOURCESEL_A::WTIMER3
409 }
410 #[doc = "Checks if the value of the field is `TIMER4`"]
411 #[inline(always)]
412 pub fn is_timer4(&self) -> bool {
413 *self == SOURCESEL_A::TIMER4
414 }
415 #[doc = "Checks if the value of the field is `TIMER5`"]
416 #[inline(always)]
417 pub fn is_timer5(&self) -> bool {
418 *self == SOURCESEL_A::TIMER5
419 }
420 #[doc = "Checks if the value of the field is `TIMER6`"]
421 #[inline(always)]
422 pub fn is_timer6(&self) -> bool {
423 *self == SOURCESEL_A::TIMER6
424 }
425}
426#[doc = "Write proxy for field `SOURCESEL`"]
427pub struct SOURCESEL_W<'a> {
428 w: &'a mut W,
429}
430impl<'a> SOURCESEL_W<'a> {
431 #[doc = r"Writes `variant` to the field"]
432 #[inline(always)]
433 pub fn variant(self, variant: SOURCESEL_A) -> &'a mut W {
434 unsafe { self.bits(variant.into()) }
435 }
436 #[doc = "No source selected"]
437 #[inline(always)]
438 pub fn none(self) -> &'a mut W {
439 self.variant(SOURCESEL_A::NONE)
440 }
441 #[doc = "Peripheral Reflex System"]
442 #[inline(always)]
443 pub fn prsl(self) -> &'a mut W {
444 self.variant(SOURCESEL_A::PRSL)
445 }
446 #[doc = "Peripheral Reflex System"]
447 #[inline(always)]
448 pub fn prs(self) -> &'a mut W {
449 self.variant(SOURCESEL_A::PRS)
450 }
451 #[doc = "Peripheral Reflex System"]
452 #[inline(always)]
453 pub fn prsh(self) -> &'a mut W {
454 self.variant(SOURCESEL_A::PRSH)
455 }
456 #[doc = "Analog Comparator 0"]
457 #[inline(always)]
458 pub fn acmp0(self) -> &'a mut W {
459 self.variant(SOURCESEL_A::ACMP0)
460 }
461 #[doc = "Analog Comparator 1"]
462 #[inline(always)]
463 pub fn acmp1(self) -> &'a mut W {
464 self.variant(SOURCESEL_A::ACMP1)
465 }
466 #[doc = "Analog to Digital Converter 0"]
467 #[inline(always)]
468 pub fn adc0(self) -> &'a mut W {
469 self.variant(SOURCESEL_A::ADC0)
470 }
471 #[doc = "Real-Time Counter"]
472 #[inline(always)]
473 pub fn rtc(self) -> &'a mut W {
474 self.variant(SOURCESEL_A::RTC)
475 }
476 #[doc = "Real-Time Counter and Calendar"]
477 #[inline(always)]
478 pub fn rtcc(self) -> &'a mut W {
479 self.variant(SOURCESEL_A::RTCC)
480 }
481 #[doc = "General purpose Input/Output"]
482 #[inline(always)]
483 pub fn gpiol(self) -> &'a mut W {
484 self.variant(SOURCESEL_A::GPIOL)
485 }
486 #[doc = "General purpose Input/Output"]
487 #[inline(always)]
488 pub fn gpioh(self) -> &'a mut W {
489 self.variant(SOURCESEL_A::GPIOH)
490 }
491 #[doc = "Low Energy Timer 0"]
492 #[inline(always)]
493 pub fn letimer0(self) -> &'a mut W {
494 self.variant(SOURCESEL_A::LETIMER0)
495 }
496 #[doc = "Low Energy Timer 1"]
497 #[inline(always)]
498 pub fn letimer1(self) -> &'a mut W {
499 self.variant(SOURCESEL_A::LETIMER1)
500 }
501 #[doc = "Pulse Counter 0"]
502 #[inline(always)]
503 pub fn pcnt0(self) -> &'a mut W {
504 self.variant(SOURCESEL_A::PCNT0)
505 }
506 #[doc = "Pulse Counter 1"]
507 #[inline(always)]
508 pub fn pcnt1(self) -> &'a mut W {
509 self.variant(SOURCESEL_A::PCNT1)
510 }
511 #[doc = "Pulse Counter 2"]
512 #[inline(always)]
513 pub fn pcnt2(self) -> &'a mut W {
514 self.variant(SOURCESEL_A::PCNT2)
515 }
516 #[doc = "CryoTimer"]
517 #[inline(always)]
518 pub fn cryotimer(self) -> &'a mut W {
519 self.variant(SOURCESEL_A::CRYOTIMER)
520 }
521 #[doc = "Clock Management Unit"]
522 #[inline(always)]
523 pub fn cmu(self) -> &'a mut W {
524 self.variant(SOURCESEL_A::CMU)
525 }
526 #[doc = "Digital to Analog Converter 0"]
527 #[inline(always)]
528 pub fn vdac0(self) -> &'a mut W {
529 self.variant(SOURCESEL_A::VDAC0)
530 }
531 #[doc = "Low Energy Sensor Interface"]
532 #[inline(always)]
533 pub fn lesensel(self) -> &'a mut W {
534 self.variant(SOURCESEL_A::LESENSEL)
535 }
536 #[doc = "Low Energy Sensor Interface"]
537 #[inline(always)]
538 pub fn lesenseh(self) -> &'a mut W {
539 self.variant(SOURCESEL_A::LESENSEH)
540 }
541 #[doc = "Low Energy Sensor Interface"]
542 #[inline(always)]
543 pub fn lesensed(self) -> &'a mut W {
544 self.variant(SOURCESEL_A::LESENSED)
545 }
546 #[doc = "Low Energy Sensor Interface"]
547 #[inline(always)]
548 pub fn lesense(self) -> &'a mut W {
549 self.variant(SOURCESEL_A::LESENSE)
550 }
551 #[doc = "Analog Comparator 1"]
552 #[inline(always)]
553 pub fn acmp2(self) -> &'a mut W {
554 self.variant(SOURCESEL_A::ACMP2)
555 }
556 #[doc = "Analog Comparator 3"]
557 #[inline(always)]
558 pub fn acmp3(self) -> &'a mut W {
559 self.variant(SOURCESEL_A::ACMP3)
560 }
561 #[doc = "Analog to Digital Converter 0"]
562 #[inline(always)]
563 pub fn adc1(self) -> &'a mut W {
564 self.variant(SOURCESEL_A::ADC1)
565 }
566 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
567 #[inline(always)]
568 pub fn usart0(self) -> &'a mut W {
569 self.variant(SOURCESEL_A::USART0)
570 }
571 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
572 #[inline(always)]
573 pub fn usart1(self) -> &'a mut W {
574 self.variant(SOURCESEL_A::USART1)
575 }
576 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
577 #[inline(always)]
578 pub fn usart2(self) -> &'a mut W {
579 self.variant(SOURCESEL_A::USART2)
580 }
581 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
582 #[inline(always)]
583 pub fn usart3(self) -> &'a mut W {
584 self.variant(SOURCESEL_A::USART3)
585 }
586 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
587 #[inline(always)]
588 pub fn usart4(self) -> &'a mut W {
589 self.variant(SOURCESEL_A::USART4)
590 }
591 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
592 #[inline(always)]
593 pub fn usart5(self) -> &'a mut W {
594 self.variant(SOURCESEL_A::USART5)
595 }
596 #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
597 #[inline(always)]
598 pub fn uart0(self) -> &'a mut W {
599 self.variant(SOURCESEL_A::UART0)
600 }
601 #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
602 #[inline(always)]
603 pub fn uart1(self) -> &'a mut W {
604 self.variant(SOURCESEL_A::UART1)
605 }
606 #[doc = "Timer 0"]
607 #[inline(always)]
608 pub fn timer0(self) -> &'a mut W {
609 self.variant(SOURCESEL_A::TIMER0)
610 }
611 #[doc = "Timer 1"]
612 #[inline(always)]
613 pub fn timer1(self) -> &'a mut W {
614 self.variant(SOURCESEL_A::TIMER1)
615 }
616 #[doc = "Timer 2"]
617 #[inline(always)]
618 pub fn timer2(self) -> &'a mut W {
619 self.variant(SOURCESEL_A::TIMER2)
620 }
621 #[doc = "Universal Serial Bus Interface"]
622 #[inline(always)]
623 pub fn usb(self) -> &'a mut W {
624 self.variant(SOURCESEL_A::USB)
625 }
626 #[doc = "`1000011`"]
627 #[inline(always)]
628 pub fn cm4(self) -> &'a mut W {
629 self.variant(SOURCESEL_A::CM4)
630 }
631 #[doc = "Timer 3"]
632 #[inline(always)]
633 pub fn timer3(self) -> &'a mut W {
634 self.variant(SOURCESEL_A::TIMER3)
635 }
636 #[doc = "Wide Timer 0"]
637 #[inline(always)]
638 pub fn wtimer0(self) -> &'a mut W {
639 self.variant(SOURCESEL_A::WTIMER0)
640 }
641 #[doc = "Wide Timer 0"]
642 #[inline(always)]
643 pub fn wtimer1(self) -> &'a mut W {
644 self.variant(SOURCESEL_A::WTIMER1)
645 }
646 #[doc = "Wide Timer 2"]
647 #[inline(always)]
648 pub fn wtimer2(self) -> &'a mut W {
649 self.variant(SOURCESEL_A::WTIMER2)
650 }
651 #[doc = "Wide Timer 3"]
652 #[inline(always)]
653 pub fn wtimer3(self) -> &'a mut W {
654 self.variant(SOURCESEL_A::WTIMER3)
655 }
656 #[doc = "Timer 4"]
657 #[inline(always)]
658 pub fn timer4(self) -> &'a mut W {
659 self.variant(SOURCESEL_A::TIMER4)
660 }
661 #[doc = "Timer 5"]
662 #[inline(always)]
663 pub fn timer5(self) -> &'a mut W {
664 self.variant(SOURCESEL_A::TIMER5)
665 }
666 #[doc = "Timer 6"]
667 #[inline(always)]
668 pub fn timer6(self) -> &'a mut W {
669 self.variant(SOURCESEL_A::TIMER6)
670 }
671 #[doc = r"Writes raw bits to the field"]
672 #[inline(always)]
673 pub unsafe fn bits(self, value: u8) -> &'a mut W {
674 self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
675 self.w
676 }
677}
678#[doc = "Edge Detect Select\n\nValue on reset: 0"]
679#[derive(Clone, Copy, Debug, PartialEq)]
680#[repr(u8)]
681pub enum EDSEL_A {
682 #[doc = "0: Signal is left as it is"]
683 OFF = 0,
684 #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
685 POSEDGE = 1,
686 #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
687 NEGEDGE = 2,
688 #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
689 BOTHEDGES = 3,
690}
691impl From<EDSEL_A> for u8 {
692 #[inline(always)]
693 fn from(variant: EDSEL_A) -> Self {
694 variant as _
695 }
696}
697#[doc = "Reader of field `EDSEL`"]
698pub type EDSEL_R = crate::R<u8, EDSEL_A>;
699impl EDSEL_R {
700 #[doc = r"Get enumerated values variant"]
701 #[inline(always)]
702 pub fn variant(&self) -> EDSEL_A {
703 match self.bits {
704 0 => EDSEL_A::OFF,
705 1 => EDSEL_A::POSEDGE,
706 2 => EDSEL_A::NEGEDGE,
707 3 => EDSEL_A::BOTHEDGES,
708 _ => unreachable!(),
709 }
710 }
711 #[doc = "Checks if the value of the field is `OFF`"]
712 #[inline(always)]
713 pub fn is_off(&self) -> bool {
714 *self == EDSEL_A::OFF
715 }
716 #[doc = "Checks if the value of the field is `POSEDGE`"]
717 #[inline(always)]
718 pub fn is_posedge(&self) -> bool {
719 *self == EDSEL_A::POSEDGE
720 }
721 #[doc = "Checks if the value of the field is `NEGEDGE`"]
722 #[inline(always)]
723 pub fn is_negedge(&self) -> bool {
724 *self == EDSEL_A::NEGEDGE
725 }
726 #[doc = "Checks if the value of the field is `BOTHEDGES`"]
727 #[inline(always)]
728 pub fn is_bothedges(&self) -> bool {
729 *self == EDSEL_A::BOTHEDGES
730 }
731}
732#[doc = "Write proxy for field `EDSEL`"]
733pub struct EDSEL_W<'a> {
734 w: &'a mut W,
735}
736impl<'a> EDSEL_W<'a> {
737 #[doc = r"Writes `variant` to the field"]
738 #[inline(always)]
739 pub fn variant(self, variant: EDSEL_A) -> &'a mut W {
740 {
741 self.bits(variant.into())
742 }
743 }
744 #[doc = "Signal is left as it is"]
745 #[inline(always)]
746 pub fn off(self) -> &'a mut W {
747 self.variant(EDSEL_A::OFF)
748 }
749 #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
750 #[inline(always)]
751 pub fn posedge(self) -> &'a mut W {
752 self.variant(EDSEL_A::POSEDGE)
753 }
754 #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
755 #[inline(always)]
756 pub fn negedge(self) -> &'a mut W {
757 self.variant(EDSEL_A::NEGEDGE)
758 }
759 #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
760 #[inline(always)]
761 pub fn bothedges(self) -> &'a mut W {
762 self.variant(EDSEL_A::BOTHEDGES)
763 }
764 #[doc = r"Writes raw bits to the field"]
765 #[inline(always)]
766 pub fn bits(self, value: u8) -> &'a mut W {
767 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
768 self.w
769 }
770}
771#[doc = "Reader of field `STRETCH`"]
772pub type STRETCH_R = crate::R<bool, bool>;
773#[doc = "Write proxy for field `STRETCH`"]
774pub struct STRETCH_W<'a> {
775 w: &'a mut W,
776}
777impl<'a> STRETCH_W<'a> {
778 #[doc = r"Sets the field bit"]
779 #[inline(always)]
780 pub fn set_bit(self) -> &'a mut W {
781 self.bit(true)
782 }
783 #[doc = r"Clears the field bit"]
784 #[inline(always)]
785 pub fn clear_bit(self) -> &'a mut W {
786 self.bit(false)
787 }
788 #[doc = r"Writes raw bits to the field"]
789 #[inline(always)]
790 pub fn bit(self, value: bool) -> &'a mut W {
791 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
792 self.w
793 }
794}
795#[doc = "Reader of field `INV`"]
796pub type INV_R = crate::R<bool, bool>;
797#[doc = "Write proxy for field `INV`"]
798pub struct INV_W<'a> {
799 w: &'a mut W,
800}
801impl<'a> INV_W<'a> {
802 #[doc = r"Sets the field bit"]
803 #[inline(always)]
804 pub fn set_bit(self) -> &'a mut W {
805 self.bit(true)
806 }
807 #[doc = r"Clears the field bit"]
808 #[inline(always)]
809 pub fn clear_bit(self) -> &'a mut W {
810 self.bit(false)
811 }
812 #[doc = r"Writes raw bits to the field"]
813 #[inline(always)]
814 pub fn bit(self, value: bool) -> &'a mut W {
815 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
816 self.w
817 }
818}
819#[doc = "Reader of field `ORPREV`"]
820pub type ORPREV_R = crate::R<bool, bool>;
821#[doc = "Write proxy for field `ORPREV`"]
822pub struct ORPREV_W<'a> {
823 w: &'a mut W,
824}
825impl<'a> ORPREV_W<'a> {
826 #[doc = r"Sets the field bit"]
827 #[inline(always)]
828 pub fn set_bit(self) -> &'a mut W {
829 self.bit(true)
830 }
831 #[doc = r"Clears the field bit"]
832 #[inline(always)]
833 pub fn clear_bit(self) -> &'a mut W {
834 self.bit(false)
835 }
836 #[doc = r"Writes raw bits to the field"]
837 #[inline(always)]
838 pub fn bit(self, value: bool) -> &'a mut W {
839 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
840 self.w
841 }
842}
843#[doc = "Reader of field `ANDNEXT`"]
844pub type ANDNEXT_R = crate::R<bool, bool>;
845#[doc = "Write proxy for field `ANDNEXT`"]
846pub struct ANDNEXT_W<'a> {
847 w: &'a mut W,
848}
849impl<'a> ANDNEXT_W<'a> {
850 #[doc = r"Sets the field bit"]
851 #[inline(always)]
852 pub fn set_bit(self) -> &'a mut W {
853 self.bit(true)
854 }
855 #[doc = r"Clears the field bit"]
856 #[inline(always)]
857 pub fn clear_bit(self) -> &'a mut W {
858 self.bit(false)
859 }
860 #[doc = r"Writes raw bits to the field"]
861 #[inline(always)]
862 pub fn bit(self, value: bool) -> &'a mut W {
863 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
864 self.w
865 }
866}
867#[doc = "Reader of field `ASYNC`"]
868pub type ASYNC_R = crate::R<bool, bool>;
869#[doc = "Write proxy for field `ASYNC`"]
870pub struct ASYNC_W<'a> {
871 w: &'a mut W,
872}
873impl<'a> ASYNC_W<'a> {
874 #[doc = r"Sets the field bit"]
875 #[inline(always)]
876 pub fn set_bit(self) -> &'a mut W {
877 self.bit(true)
878 }
879 #[doc = r"Clears the field bit"]
880 #[inline(always)]
881 pub fn clear_bit(self) -> &'a mut W {
882 self.bit(false)
883 }
884 #[doc = r"Writes raw bits to the field"]
885 #[inline(always)]
886 pub fn bit(self, value: bool) -> &'a mut W {
887 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
888 self.w
889 }
890}
891impl R {
892 #[doc = "Bits 0:2 - Signal Select"]
893 #[inline(always)]
894 pub fn sigsel(&self) -> SIGSEL_R {
895 SIGSEL_R::new((self.bits & 0x07) as u8)
896 }
897 #[doc = "Bits 8:14 - Source Select"]
898 #[inline(always)]
899 pub fn sourcesel(&self) -> SOURCESEL_R {
900 SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
901 }
902 #[doc = "Bits 20:21 - Edge Detect Select"]
903 #[inline(always)]
904 pub fn edsel(&self) -> EDSEL_R {
905 EDSEL_R::new(((self.bits >> 20) & 0x03) as u8)
906 }
907 #[doc = "Bit 25 - Stretch Channel Output"]
908 #[inline(always)]
909 pub fn stretch(&self) -> STRETCH_R {
910 STRETCH_R::new(((self.bits >> 25) & 0x01) != 0)
911 }
912 #[doc = "Bit 26 - Invert Channel"]
913 #[inline(always)]
914 pub fn inv(&self) -> INV_R {
915 INV_R::new(((self.bits >> 26) & 0x01) != 0)
916 }
917 #[doc = "Bit 27 - Or Previous"]
918 #[inline(always)]
919 pub fn orprev(&self) -> ORPREV_R {
920 ORPREV_R::new(((self.bits >> 27) & 0x01) != 0)
921 }
922 #[doc = "Bit 28 - And Next"]
923 #[inline(always)]
924 pub fn andnext(&self) -> ANDNEXT_R {
925 ANDNEXT_R::new(((self.bits >> 28) & 0x01) != 0)
926 }
927 #[doc = "Bit 30 - Asynchronous Reflex"]
928 #[inline(always)]
929 pub fn async(&self) -> ASYNC_R {
930 ASYNC_R::new(((self.bits >> 30) & 0x01) != 0)
931 }
932}
933impl W {
934 #[doc = "Bits 0:2 - Signal Select"]
935 #[inline(always)]
936 pub fn sigsel(&mut self) -> SIGSEL_W {
937 SIGSEL_W { w: self }
938 }
939 #[doc = "Bits 8:14 - Source Select"]
940 #[inline(always)]
941 pub fn sourcesel(&mut self) -> SOURCESEL_W {
942 SOURCESEL_W { w: self }
943 }
944 #[doc = "Bits 20:21 - Edge Detect Select"]
945 #[inline(always)]
946 pub fn edsel(&mut self) -> EDSEL_W {
947 EDSEL_W { w: self }
948 }
949 #[doc = "Bit 25 - Stretch Channel Output"]
950 #[inline(always)]
951 pub fn stretch(&mut self) -> STRETCH_W {
952 STRETCH_W { w: self }
953 }
954 #[doc = "Bit 26 - Invert Channel"]
955 #[inline(always)]
956 pub fn inv(&mut self) -> INV_W {
957 INV_W { w: self }
958 }
959 #[doc = "Bit 27 - Or Previous"]
960 #[inline(always)]
961 pub fn orprev(&mut self) -> ORPREV_W {
962 ORPREV_W { w: self }
963 }
964 #[doc = "Bit 28 - And Next"]
965 #[inline(always)]
966 pub fn andnext(&mut self) -> ANDNEXT_W {
967 ANDNEXT_W { w: self }
968 }
969 #[doc = "Bit 30 - Asynchronous Reflex"]
970 #[inline(always)]
971 pub fn async(&mut self) -> ASYNC_W {
972 ASYNC_W { w: self }
973 }
974}