[−][src]Enum efm32gg11b820::prs::ch6_ctrl::EDSELW
Values that can be written to the field EDSEL
Variants
OFF
Signal is left as it is
POSEDGE
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
NEGEDGE
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
BOTHEDGES
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal
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