Struct efm32gg11b820::adc0::scanctrlx::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn vrefsel(&self) -> VREFSELR[src]
Bits 0:2 - Scan Channel Reference Selection
pub fn vrefattfix(&self) -> VREFATTFIXR[src]
Bit 3 - Enable Fixed Scaling on VREF
pub fn vrefatt(&self) -> VREFATTR[src]
Bits 4:7 - Code for VREF Attenuation Factor When VREFSEL is 1, 2 or 5
pub fn vinatt(&self) -> VINATTR[src]
Bits 8:11 - Code for VIN Attenuation Factor
pub fn dvl(&self) -> DVLR[src]
Bits 12:13 - Scan DV Level Select
pub fn fifoofact(&self) -> FIFOOFACTR[src]
Bit 14 - Scan FIFO Overflow Action
pub fn prsmode(&self) -> PRSMODER[src]
Bit 16 - Scan PRS Trigger Mode
pub fn prssel(&self) -> PRSSELR[src]
Bits 17:21 - Scan Sequence PRS Trigger Select
pub fn convstartdelay(&self) -> CONVSTARTDELAYR[src]
Bits 22:26 - Delay Next Conversion Start If CONVSTARTDELAYEN is Set
pub fn convstartdelayen(&self) -> CONVSTARTDELAYENR[src]
Bit 27 - Enable Delaying Next Conversion Start
pub fn repdelay(&self) -> REPDELAYR[src]
Bits 29:31 - REPDELAY Select for SCAN REP Mode