Struct efm32gg11b820::usart3::ien::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
fn bits(&self) -> u32[src]
Value of the register as raw bits
fn txc(&self) -> TXCR[src]
Bit 0 - TXC Interrupt Enable
fn txbl(&self) -> TXBLR[src]
Bit 1 - TXBL Interrupt Enable
fn rxdatav(&self) -> RXDATAVR[src]
Bit 2 - RXDATAV Interrupt Enable
fn rxfull(&self) -> RXFULLR[src]
Bit 3 - RXFULL Interrupt Enable
fn rxof(&self) -> RXOFR[src]
Bit 4 - RXOF Interrupt Enable
fn rxuf(&self) -> RXUFR[src]
Bit 5 - RXUF Interrupt Enable
fn txof(&self) -> TXOFR[src]
Bit 6 - TXOF Interrupt Enable
fn txuf(&self) -> TXUFR[src]
Bit 7 - TXUF Interrupt Enable
fn perr(&self) -> PERRR[src]
Bit 8 - PERR Interrupt Enable
fn ferr(&self) -> FERRR[src]
Bit 9 - FERR Interrupt Enable
fn mpaf(&self) -> MPAFR[src]
Bit 10 - MPAF Interrupt Enable
fn ssm(&self) -> SSMR[src]
Bit 11 - SSM Interrupt Enable
fn ccf(&self) -> CCFR[src]
Bit 12 - CCF Interrupt Enable
fn txidle(&self) -> TXIDLER[src]
Bit 13 - TXIDLE Interrupt Enable
fn tcmp0(&self) -> TCMP0R[src]
Bit 14 - TCMP0 Interrupt Enable
fn tcmp1(&self) -> TCMP1R[src]
Bit 15 - TCMP1 Interrupt Enable
fn tcmp2(&self) -> TCMP2R[src]
Bit 16 - TCMP2 Interrupt Enable