efm32gg11b820_pac/usb/
hc8_splt.rs

1#[doc = "Register `HC8_SPLT` reader"]
2pub struct R(crate::R<HC8_SPLT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HC8_SPLT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HC8_SPLT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HC8_SPLT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HC8_SPLT` writer"]
17pub struct W(crate::W<HC8_SPLT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HC8_SPLT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HC8_SPLT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HC8_SPLT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PRTADDR` reader - Port Address"]
38pub type PRTADDR_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `PRTADDR` writer - Port Address"]
40pub type PRTADDR_W<'a> = crate::FieldWriter<'a, u32, HC8_SPLT_SPEC, u8, u8, 7, 0>;
41#[doc = "Field `HUBADDR` reader - Hub Address"]
42pub type HUBADDR_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `HUBADDR` writer - Hub Address"]
44pub type HUBADDR_W<'a> = crate::FieldWriter<'a, u32, HC8_SPLT_SPEC, u8, u8, 7, 7>;
45#[doc = "Field `XACTPOS` reader - Transaction Position"]
46pub type XACTPOS_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `XACTPOS` writer - Transaction Position"]
48pub type XACTPOS_W<'a> = crate::FieldWriter<'a, u32, HC8_SPLT_SPEC, u8, u8, 2, 14>;
49#[doc = "Field `COMPSPLT` reader - Do Complete Split"]
50pub type COMPSPLT_R = crate::BitReader<bool>;
51#[doc = "Field `COMPSPLT` writer - Do Complete Split"]
52pub type COMPSPLT_W<'a> = crate::BitWriter<'a, u32, HC8_SPLT_SPEC, bool, 16>;
53#[doc = "Field `SPLTENA` reader - Split Enable"]
54pub type SPLTENA_R = crate::BitReader<bool>;
55#[doc = "Field `SPLTENA` writer - Split Enable"]
56pub type SPLTENA_W<'a> = crate::BitWriter<'a, u32, HC8_SPLT_SPEC, bool, 31>;
57impl R {
58    #[doc = "Bits 0:6 - Port Address"]
59    #[inline(always)]
60    pub fn prtaddr(&self) -> PRTADDR_R {
61        PRTADDR_R::new((self.bits & 0x7f) as u8)
62    }
63    #[doc = "Bits 7:13 - Hub Address"]
64    #[inline(always)]
65    pub fn hubaddr(&self) -> HUBADDR_R {
66        HUBADDR_R::new(((self.bits >> 7) & 0x7f) as u8)
67    }
68    #[doc = "Bits 14:15 - Transaction Position"]
69    #[inline(always)]
70    pub fn xactpos(&self) -> XACTPOS_R {
71        XACTPOS_R::new(((self.bits >> 14) & 3) as u8)
72    }
73    #[doc = "Bit 16 - Do Complete Split"]
74    #[inline(always)]
75    pub fn compsplt(&self) -> COMPSPLT_R {
76        COMPSPLT_R::new(((self.bits >> 16) & 1) != 0)
77    }
78    #[doc = "Bit 31 - Split Enable"]
79    #[inline(always)]
80    pub fn spltena(&self) -> SPLTENA_R {
81        SPLTENA_R::new(((self.bits >> 31) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bits 0:6 - Port Address"]
86    #[inline(always)]
87    pub fn prtaddr(&mut self) -> PRTADDR_W {
88        PRTADDR_W::new(self)
89    }
90    #[doc = "Bits 7:13 - Hub Address"]
91    #[inline(always)]
92    pub fn hubaddr(&mut self) -> HUBADDR_W {
93        HUBADDR_W::new(self)
94    }
95    #[doc = "Bits 14:15 - Transaction Position"]
96    #[inline(always)]
97    pub fn xactpos(&mut self) -> XACTPOS_W {
98        XACTPOS_W::new(self)
99    }
100    #[doc = "Bit 16 - Do Complete Split"]
101    #[inline(always)]
102    pub fn compsplt(&mut self) -> COMPSPLT_W {
103        COMPSPLT_W::new(self)
104    }
105    #[doc = "Bit 31 - Split Enable"]
106    #[inline(always)]
107    pub fn spltena(&mut self) -> SPLTENA_W {
108        SPLTENA_W::new(self)
109    }
110    #[doc = "Writes raw bits to the register."]
111    #[inline(always)]
112    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
113        self.0.bits(bits);
114        self
115    }
116}
117#[doc = "Host Channel x Split Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc8_splt](index.html) module"]
118pub struct HC8_SPLT_SPEC;
119impl crate::RegisterSpec for HC8_SPLT_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [hc8_splt::R](R) reader structure"]
123impl crate::Readable for HC8_SPLT_SPEC {
124    type Reader = R;
125}
126#[doc = "`write(|w| ..)` method takes [hc8_splt::W](W) writer structure"]
127impl crate::Writable for HC8_SPLT_SPEC {
128    type Writer = W;
129}
130#[doc = "`reset()` method sets HC8_SPLT to value 0"]
131impl crate::Resettable for HC8_SPLT_SPEC {
132    #[inline(always)]
133    fn reset_value() -> Self::Ux {
134        0
135    }
136}
efm32gg11b820_pac/usb/hc8_splt.rs

efm32gg11b820_pac/usb/
hc8_splt.rs
